UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenCloudOS-Kernel/drivers/dma/mediatek/Makefile

5 lines
167 B
Makefile
Raw Normal View History

treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 20:07:45 +08:00
# SPDX-License-Identifier: GPL-2.0-only
dmaengine: mediatek: Add MediaTek UART APDMA support Add 8250 UART APDMA to support MediaTek UART. If MediaTek UART is enabled by SERIAL_8250_MT6577, and we can enable this driver to offload the UART device moving bytes. Signed-off-by: Long Cheng <long.cheng@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-04-27 11:36:30 +08:00
obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has a single ring is dedicated to memory-to-memory transfer through ring based descriptor management. Even though there is only one physical ring available inside HSDMA, the driver can be easily extended to the support of multiple virtual channels processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-03-15 15:40:36 +08:00
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Signed-off-by: Shun-Chih Yu <shun-chih.yu@mediatek.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-10-18 15:49:11 +08:00
obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o