License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
|
|
|
# SPDX-License-Identifier: GPL-2.0
|
2007-11-15 20:49:44 +08:00
|
|
|
if (BF561)
|
|
|
|
|
|
|
|
|
|
source "arch/blackfin/mach-bf561/boards/Kconfig"
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
|
|
|
|
|
|
|
|
menu "BF561 Specific Configuration"
|
|
|
|
|
|
2009-01-07 23:14:39 +08:00
|
|
|
if (!SMP)
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
|
|
|
|
2009-01-07 23:14:39 +08:00
|
|
|
comment "Core B Support"
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
|
|
|
|
|
|
|
|
config BF561_COREB
|
2009-05-14 22:55:50 +08:00
|
|
|
bool "Enable Core B loader"
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
|
|
|
default y
|
|
|
|
|
|
2009-01-07 23:14:39 +08:00
|
|
|
endif
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
|
|
|
|
|
|
|
|
comment "Interrupt Priority Assignment"
|
|
|
|
|
|
|
|
|
|
menu "Priority"
|
|
|
|
|
|
|
|
|
|
config IRQ_PLL_WAKEUP
|
|
|
|
|
int "PLL Wakeup Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_DMA1_ERROR
|
|
|
|
|
int "DMA1 Error (generic)"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_DMA2_ERROR
|
|
|
|
|
int "DMA2 Error (generic)"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_IMDMA_ERROR
|
|
|
|
|
int "IMDMA Error (generic)"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_PPI0_ERROR
|
|
|
|
|
int "PPI0 Error Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_PPI1_ERROR
|
|
|
|
|
int "PPI1 Error Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_SPORT0_ERROR
|
|
|
|
|
int "SPORT0 Error Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_SPORT1_ERROR
|
|
|
|
|
int "SPORT1 Error Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_SPI_ERROR
|
|
|
|
|
int "SPI Error Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_UART_ERROR
|
|
|
|
|
int "UART Error Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_RESERVED_ERROR
|
|
|
|
|
int "Reserved Interrupt"
|
|
|
|
|
default 7
|
|
|
|
|
config IRQ_DMA1_0
|
|
|
|
|
int "DMA1 0 Interrupt(PPI1)"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_1
|
|
|
|
|
int "DMA1 1 Interrupt(PPI2)"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_2
|
|
|
|
|
int "DMA1 2 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_3
|
|
|
|
|
int "DMA1 3 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_4
|
|
|
|
|
int "DMA1 4 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_5
|
|
|
|
|
int "DMA1 5 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_6
|
|
|
|
|
int "DMA1 6 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_7
|
|
|
|
|
int "DMA1 7 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_8
|
|
|
|
|
int "DMA1 8 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_9
|
|
|
|
|
int "DMA1 9 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_10
|
|
|
|
|
int "DMA1 10 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_11
|
|
|
|
|
int "DMA1 11 Interrupt"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA2_0
|
|
|
|
|
int "DMA2 0 (SPORT0 RX)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_1
|
|
|
|
|
int "DMA2 1 (SPORT0 TX)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_2
|
|
|
|
|
int "DMA2 2 (SPORT1 RX)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_3
|
|
|
|
|
int "DMA2 3 (SPORT2 TX)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_4
|
|
|
|
|
int "DMA2 4 (SPI)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_5
|
|
|
|
|
int "DMA2 5 (UART RX)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_6
|
|
|
|
|
int "DMA2 6 (UART TX)"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_7
|
|
|
|
|
int "DMA2 7 Interrupt"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_8
|
|
|
|
|
int "DMA2 8 Interrupt"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_9
|
|
|
|
|
int "DMA2 9 Interrupt"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_10
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int "DMA2 10 Interrupt"
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default 9
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config IRQ_DMA2_11
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int "DMA2 11 Interrupt"
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default 9
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config IRQ_TIMER0
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int "TIMER 0 Interrupt"
|
2009-05-15 19:01:59 +08:00
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default 7 if TICKSOURCE_GPTMR0
|
2009-01-07 23:14:39 +08:00
|
|
|
default 8
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
|
|
|
config IRQ_TIMER1
|
|
|
|
|
int "TIMER 1 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER2
|
|
|
|
|
int "TIMER 2 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER3
|
|
|
|
|
int "TIMER 3 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER4
|
|
|
|
|
int "TIMER 4 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER5
|
|
|
|
|
int "TIMER 5 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER6
|
|
|
|
|
int "TIMER 6 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER7
|
|
|
|
|
int "TIMER 7 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER8
|
|
|
|
|
int "TIMER 8 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER9
|
|
|
|
|
int "TIMER 9 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER10
|
|
|
|
|
int "TIMER 10 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_TIMER11
|
|
|
|
|
int "TIMER 11 Interrupt"
|
|
|
|
|
default 10
|
|
|
|
|
config IRQ_PROG0_INTA
|
|
|
|
|
int "Programmable Flags0 A (8)"
|
|
|
|
|
default 11
|
|
|
|
|
config IRQ_PROG0_INTB
|
|
|
|
|
int "Programmable Flags0 B (8)"
|
|
|
|
|
default 11
|
|
|
|
|
config IRQ_PROG1_INTA
|
|
|
|
|
int "Programmable Flags1 A (8)"
|
|
|
|
|
default 11
|
|
|
|
|
config IRQ_PROG1_INTB
|
|
|
|
|
int "Programmable Flags1 B (8)"
|
|
|
|
|
default 11
|
|
|
|
|
config IRQ_PROG2_INTA
|
|
|
|
|
int "Programmable Flags2 A (8)"
|
|
|
|
|
default 11
|
|
|
|
|
config IRQ_PROG2_INTB
|
|
|
|
|
int "Programmable Flags2 B (8)"
|
|
|
|
|
default 11
|
|
|
|
|
config IRQ_DMA1_WRRD0
|
|
|
|
|
int "MDMA1 0 write/read INT"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA1_WRRD1
|
|
|
|
|
int "MDMA1 1 write/read INT"
|
|
|
|
|
default 8
|
|
|
|
|
config IRQ_DMA2_WRRD0
|
|
|
|
|
int "MDMA2 0 write/read INT"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_DMA2_WRRD1
|
|
|
|
|
int "MDMA2 1 write/read INT"
|
|
|
|
|
default 9
|
|
|
|
|
config IRQ_IMDMA_WRRD0
|
|
|
|
|
int "IMDMA 0 write/read INT"
|
|
|
|
|
default 12
|
|
|
|
|
config IRQ_IMDMA_WRRD1
|
|
|
|
|
int "IMDMA 1 write/read INT"
|
|
|
|
|
default 12
|
|
|
|
|
config IRQ_WDTIMER
|
|
|
|
|
int "Watch Dog Timer"
|
|
|
|
|
default 13
|
|
|
|
|
|
|
|
|
|
help
|
|
|
|
|
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
|
|
|
|
|
This applies to all the above. It is not recommended to assign the
|
|
|
|
|
highest priority number 7 to UART or any other device.
|
|
|
|
|
|
|
|
|
|
endmenu
|
|
|
|
|
|
|
|
|
|
endmenu
|
|
|
|
|
|
|
|
|
|
endif
|