arm64: Add sysreg header generation scripting
The arm64 kernel requires some metadata for each system register it may
need to access. Currently we have:
* A SYS_<regname> definition which sorresponds to a sys_reg() macro.
This is used both to look up a sysreg by encoding (e.g. in KVM), and
also to generate code to access a sysreg where the assembler is
unaware of the specific sysreg encoding.
Where assemblers support the S3_<op1>_C<crn>_C<crm>_<op2> syntax for
system registers, we could use this rather than manually assembling
the instructions. However, we don't have consistent definitions for
these and we currently still need to handle toolchains that lack this
feature.
* A set of <regname>_<fieldname>_SHIFT and <regname>_<fieldname>_MASK
definitions, which can be used to extract fields from the register, or
to construct a register from a set of fields.
These do not follow the convention used by <linux/bitfield.h>, and the
masks are not shifted into place, preventing their use in FIELD_PREP()
and FIELD_GET(). We require the SHIFT definitions for inline assembly
(and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot
only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and
unshifted MASK is tedious and error-prone and life is much easier when
they can be relied up to exist when writing code.
* A set of <regname>_<fieldname>_<valname> definitions for each
enumerated value a field may hold. These are used when identifying the
presence of features.
Atop of this, other code has to build up metadata at runtime (e.g. the
sets of RES0/RES1 bits in a register).
This patch adds scripting so that we can have an easier-to-manage
canonical representation of this metadata, from which we can generate
all the definitions necessary for various use-cases, e.g.
| #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0
| #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
| #define SYS_ID_AA64ISAR0_EL1_Op0 3
| #define SYS_ID_AA64ISAR0_EL1_Op1 0
| #define SYS_ID_AA64ISAR0_EL1_CRn 0
| #define SYS_ID_AA64ISAR0_EL1_CRm 6
| #define SYS_ID_AA64ISAR0_EL1_Op2 0
| #define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60)
| #define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60)
| #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60
| #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4
| #define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000)
| #define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001)
The script requires that all bits in the register be specified and that
there be no overlapping fields. This helps the script spot errors in the
input but means that the few registers which change layout at runtime
depending on things like virtualisation settings will need some manual
handling. No actual register conversions are done here but a header for
the register data with some documention of the format is provided.
For cases where multiple registers share a layout (eg, when identical
controls are provided at multiple ELs) the register fields can be
defined once and referenced from the actual registers, currently we do
not generate actual defines for the individual registers.
At the moment this is only intended to express metadata from the
architecture, and does not handle policy imposed by the kernel, such as
values exposed to userspace or VMs. In future this could be extended to
express such information.
This script was mostly written by Mark Rutland but has been extended by
Mark Brown to improve validation of input and better integrate with the
kernel.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Co-Developed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220503170233.507788-9-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:29 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# System register metadata
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# Each System register is described by a Sysreg block:
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# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
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# <field>
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# ...
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# EndSysreg
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# Within a Sysreg block, each field can be described as one of:
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# Res0 <msb>[:<lsb>]
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# Res1 <msb>[:<lsb>]
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# Field <msb>[:<lsb>] <name>
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# Enum <msb>[:<lsb>] <name>
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# <enumval> <enumname>
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# ...
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# EndEnum
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# Alternatively if multiple registers share the same layout then
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# a SysregFields block can be used to describe the shared layout
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# SysregFields <fieldsname>
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# <field>
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# ...
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# EndSysregFields
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# and referenced from within the Sysreg:
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# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
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# Fields <fieldsname>
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# EndSysreg
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# For ID registers we adopt a few conventions for translating the
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# language in the ARM into defines:
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#
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# NI - Not implemented
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# IMP - Implemented
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#
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# In general it is recommended that new enumeration items be named for the
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# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
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# item ACCDATA) though it may be more taseful to do something else.
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2022-05-04 01:02:31 +08:00
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Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
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Enum 63:60 RNDR
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 59:56 TLB
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0b0000 NI
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0b0001 OS
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0b0010 RANGE
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EndEnum
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Enum 55:52 TS
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0b0000 NI
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0b0001 FLAGM
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0b0010 FLAGM2
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EndEnum
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Enum 51:48 FHM
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 47:44 DP
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 43:40 SM4
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 39:36 SM3
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 35:32 SHA3
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 31:28 RDM
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 27:24 TME
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 23:20 ATOMIC
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0b0000 NI
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0b0010 IMP
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EndEnum
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Enum 19:16 CRC32
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 15:12 SHA2
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0b0000 NI
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0b0001 SHA256
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0b0010 SHA512
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EndEnum
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Enum 11:8 SHA1
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 7:4 AES
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0b0000 NI
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0b0001 AES
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0b0010 PMULL
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EndEnum
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Res0 3:0
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EndSysreg
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2022-05-04 01:02:32 +08:00
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2022-05-04 01:02:33 +08:00
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Sysreg SCTLR_EL1 3 0 1 0 0
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Field 63 TIDCP
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Field 62 SPINMASK
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Field 61 NMI
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Field 60 EnTP2
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Res0 59:58
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Field 57 EPAN
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Field 56 EnALS
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Field 55 EnAS0
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Field 54 EnASR
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Field 53 TME
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Field 52 TME0
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Field 51 TMT
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Field 50 TMT0
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Field 49:46 TWEDEL
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Field 45 TWEDEn
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Field 44 DSSBS
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Field 43 ATA
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Field 42 ATA0
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Enum 41:40 TCF
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0b00 NONE
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0b01 SYNC
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0b10 ASYNC
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0b11 ASYMM
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EndEnum
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Enum 39:38 TCF0
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0b00 NONE
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0b01 SYNC
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0b10 ASYNC
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0b11 ASYMM
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EndEnum
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Field 37 ITFSB
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Field 36 BT1
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Field 35 BT0
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Res0 34
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Field 33 MSCEn
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Field 32 CMOW
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Field 31 EnIA
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Field 30 EnIB
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Field 29 LSMAOE
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Field 28 nTLSMD
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Field 27 EnDA
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Field 26 UCI
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Field 25 EE
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Field 24 E0E
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Field 23 SPAN
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Field 22 EIS
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Field 21 IESB
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Field 20 TSCXT
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Field 19 WXN
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Field 18 nTWE
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Res0 17
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Field 16 nTWI
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Field 15 UCT
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Field 14 DZE
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Field 13 EnDB
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Field 12 I
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Field 11 EOS
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Field 10 EnRCTX
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Field 9 UMA
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Field 8 SED
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Field 7 ITD
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Field 6 nAA
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Field 5 CP15BEN
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Field 4 SA0
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Field 3 SA
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Field 2 C
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Field 1 A
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Field 0 M
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EndSysreg
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2022-05-11 00:12:03 +08:00
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SysregFields SMCR_ELx
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Res0 63:32
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Field 31 FA64
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Res0 30:9
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Raz 8:4
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Field 3:0 LEN
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EndSysregFields
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Sysreg SMCR_EL1 3 0 1 2 6
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Fields SMCR_ELx
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EndSysreg
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2022-05-11 00:12:04 +08:00
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Sysreg SMIDR_EL1 3 1 0 0 6
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Res0 63:32
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Field 31:24 IMPLEMENTER
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Field 23:16 REVISION
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Field 15 SMPS
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Res0 14:12
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Field 11:0 AFFINITY
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EndSysreg
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2022-05-11 00:12:05 +08:00
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Sysreg SMPRIMAP_EL2 3 4 1 2 5
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Field 63:60 P15
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Field 59:56 P14
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Field 55:52 P13
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Field 51:48 P12
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Field 47:44 P11
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Field 43:40 P10
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Field 39:36 F9
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Field 35:32 P8
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Field 31:28 P7
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Field 27:24 P6
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Field 23:20 P5
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Field 19:16 P4
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Field 15:12 P3
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Field 11:8 P2
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Field 7:4 P1
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Field 3:0 P0
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EndSysreg
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2022-05-11 00:12:03 +08:00
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Sysreg SMCR_EL2 3 4 1 2 6
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Fields SMCR_ELx
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EndSysreg
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Sysreg SMCR_EL12 3 5 1 2 6
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Fields SMCR_ELx
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EndSysreg
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2022-05-04 01:02:32 +08:00
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SysregFields TTBRx_EL1
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Field 63:48 ASID
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Field 47:1 BADDR
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Field 0 CnP
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EndSysregFields
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Sysreg TTBR0_EL1 3 0 2 0 0
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Fields TTBRx_EL1
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EndSysreg
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Sysreg TTBR1_EL1 3 0 2 0 1
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Fields TTBRx_EL1
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EndSysreg
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