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OpenCloudOS-Kernel/drivers/clocksource/timer-imx-gpt.c

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i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
/*
* linux/arch/arm/plat-mxc/time.c
*
* Copyright (C) 2000-2001 Deep Blue Solutions
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
ARM: imx: enable delaytimer on the imx timer The imx can support timer-based delays, so implement this. Skips past jiffy calibration. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-01-22 19:35:44 +08:00
#include <linux/delay.h>
ARM i.MX timer: request correct clock We used to pass the timer clock directly to mxc_timer_init. We should instead request the correct clock. This is an intermediate step: For now we request the clock in the timer code when NULL is passed as clock. Also, the gpt on some i.MX have an additional ipg clock which can be gated. Request and enable this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-03-09 16:29:27 +08:00
#include <linux/err.h>
sched_clock: Make ARM's sched_clock generic for all architectures Nothing about the sched_clock implementation in the ARM port is specific to the architecture. Generalize the code so that other architectures can use it by selecting GENERIC_SCHED_CLOCK. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [jstultz: Merge minor collisions with other patches in my tree] Signed-off-by: John Stultz <john.stultz@linaro.org>
2013-06-02 14:39:40 +08:00
#include <linux/sched_clock.h>
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
#include <linux/slab.h>
ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05 23:57:45 +08:00
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
ARM: imx: define an enum for gpt timer device type Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 11:41:39 +08:00
#include <soc/imx/timer.h>
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
mxc: refactor timer code to use timer versions Refactor the timer code into version 1 and version 2. Essentially there are 2 versions of the timer hardware on Freescale MXC hardware. Version 1 is found on MX1/MXL, MX21 and MX27. Version 2 is found on MX25, MX31, MX35, MX37, MX51, and future parts. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
2009-12-04 16:34:51 +08:00
/*
ARM: imx: Correct the comments in time.c The comments were corrected as the following to reflect the real situation of Freescale MXC timer IP block. There are totally 4 version of the timer on Freescale i.MX SoCs. Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-04-30 05:40:27 +08:00
* There are 4 versions of the timer hardware on Freescale MXC hardware.
* - MX1/MXL
* - MX21, MX27.
* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
* - MX6DL, MX6SX, MX6Q(rev1.1+)
mxc: refactor timer code to use timer versions Refactor the timer code into version 1 and version 2. Essentially there are 2 versions of the timer hardware on Freescale MXC hardware. Version 1 is found on MX1/MXL, MX21 and MX27. Version 2 is found on MX25, MX31, MX35, MX37, MX51, and future parts. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
2009-12-04 16:34:51 +08:00
*/
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
/* defines common for all i.MX */
#define MXC_TCTL 0x00
mxc: refactor timer code to use timer versions Refactor the timer code into version 1 and version 2. Essentially there are 2 versions of the timer hardware on Freescale MXC hardware. Version 1 is found on MX1/MXL, MX21 and MX27. Version 2 is found on MX25, MX31, MX35, MX37, MX51, and future parts. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
2009-12-04 16:34:51 +08:00
#define MXC_TCTL_TEN (1 << 0) /* Enable module */
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
#define MXC_TPRER 0x04
/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
#define MX1_2_TCTL_IRQEN (1 << 4)
#define MX1_2_TCTL_FRR (1 << 8)
#define MX1_2_TCMP 0x08
#define MX1_2_TCN 0x10
#define MX1_2_TSTAT 0x14
/* MX21, MX27 */
#define MX2_TSTAT_CAPT (1 << 1)
#define MX2_TSTAT_COMP (1 << 0)
ARM: imx: source gpt per clk from OSC for system timer On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-11 11:29:42 +08:00
/* MX31, MX35, MX25, MX5, MX6 */
mxc: Change gpt timer code to be more generic by using V2 instead of MX3 Replace mx3_ with v2_ since the register layout is the same for all SoCs using version 2 of the timer (mx25, mx31, mx37 and now mx51) Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-04-22 02:34:36 +08:00
#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG (1 << 6)
ARM: i.MX: change timer clock from ipg to perclk Contrary to the ipg clock the perclk rate is not changed or gated in low power mode, so we choose perclk for gpt. With the port to the common clock framework as a side effect the timer used the rate returned from the peripheral clock but the hardware was still programmed to use the ipg clock, so this patch only changes the hardware to really use the clock it already assumed. Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-15 15:34:40 +08:00
#define V2_TCTL_CLK_PER (2 << 6)
ARM: imx: source gpt per clk from OSC for system timer On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-11 11:29:42 +08:00
#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
mxc: Change gpt timer code to be more generic by using V2 instead of MX3 Replace mx3_ with v2_ since the register layout is the same for all SoCs using version 2 of the timer (mx25, mx31, mx37 and now mx51) Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-04-22 02:34:36 +08:00
#define V2_TCTL_FRR (1 << 9)
ARM: imx: source gpt per clk from OSC for system timer On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-11 11:29:42 +08:00
#define V2_TCTL_24MEN (1 << 10)
#define V2_TPRER_PRE24M 12
mxc: Change gpt timer code to be more generic by using V2 instead of MX3 Replace mx3_ with v2_ since the register layout is the same for all SoCs using version 2 of the timer (mx25, mx31, mx37 and now mx51) Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-04-22 02:34:36 +08:00
#define V2_IR 0x0c
#define V2_TSTAT 0x08
#define V2_TSTAT_OF1 (1 << 0)
#define V2_TCN 0x24
#define V2_TCMP 0x10
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: source gpt per clk from OSC for system timer On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-11 11:29:42 +08:00
#define V2_TIMER_RATE_OSC_DIV8 3000000
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
struct imx_timer {
ARM: imx: define an enum for gpt timer device type Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 11:41:39 +08:00
enum imx_gpt_type type;
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
void __iomem *base;
int irq;
struct clk *clk_per;
struct clk *clk_ipg;
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
const struct imx_gpt_data *gpt;
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
struct clock_event_device ced;
enum clock_event_mode cem;
struct irqaction act;
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
};
struct imx_gpt_data {
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
int reg_tstat;
int reg_tcn;
int reg_tcmp;
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
void (*gpt_setup_tctl)(struct imx_timer *imxtm);
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
void (*gpt_irq_enable)(struct imx_timer *imxtm);
void (*gpt_irq_disable)(struct imx_timer *imxtm);
void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
ARM: imx: set up .set_next_event hook via imx_gpt_data Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 15:51:41 +08:00
int (*set_next_event)(unsigned long evt,
struct clock_event_device *ced);
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
};
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
{
return container_of(ced, struct imx_timer, ced);
}
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
{
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
unsigned int tmp;
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
tmp = readl_relaxed(imxtm->base + MXC_TCTL);
writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
}
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
#define imx21_gpt_irq_disable imx1_gpt_irq_disable
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
{
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
writel_relaxed(0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
{
unsigned int tmp;
tmp = readl_relaxed(imxtm->base + MXC_TCTL);
writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_enable imx1_gpt_irq_enable
static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
{
writel_relaxed(1<<0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
}
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
{
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
imxtm->base + MX1_2_TSTAT);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
}
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
}
#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
clocksource: convert ARM 32-bit up counting clocksources Convert ixp4xx, lpc32xx, mxc, netx, pxa, sa1100, tcc8k, tegra and u300 to use the generic mmio clocksource recently introduced. Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Krzysztof Halasa <khc@pm.waw.pl> Acked-by: Eric Miao <eric.y.miao@gmail.com> Acked-by: "Hans J. Koch" <hjk@hansjkoch.de> Acked-by: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Olof Johansson <olof@lixom.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-08 21:09:47 +08:00
static void __iomem *sched_clock_reg;
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: Switch to sched_clock_register() The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface. Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-11-16 07:26:12 +08:00
static u64 notrace mxc_read_sched_clock(void)
ARM: mxc: Add sched_clock to mxc platform Add sched_clock using cyc_to_sched_clock and update_sched_clock with HAVE_SCHED_CLOCK tested on iMX27 and iMX35 Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-03-17 20:44:30 +08:00
{
ARM: imx: use relaxed IO accessor in timer driver Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-19 18:47:47 +08:00
return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
ARM: mxc: Add sched_clock to mxc platform Add sched_clock using cyc_to_sched_clock and update_sched_clock with HAVE_SCHED_CLOCK tested on iMX27 and iMX35 Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-03-17 20:44:30 +08:00
}
ARM: imx: enable delaytimer on the imx timer The imx can support timer-based delays, so implement this. Skips past jiffy calibration. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-01-22 19:35:44 +08:00
static struct delay_timer imx_delay_timer;
static unsigned long imx_read_current_timer(void)
{
ARM: imx: use relaxed IO accessor in timer driver Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-19 18:47:47 +08:00
return readl_relaxed(sched_clock_reg);
ARM: imx: enable delaytimer on the imx timer The imx can support timer-based delays, so implement this. Skips past jiffy calibration. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-01-22 19:35:44 +08:00
}
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
static int __init mxc_clocksource_init(struct imx_timer *imxtm)
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
{
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
unsigned int c = clk_get_rate(imxtm->clk_per);
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: enable delaytimer on the imx timer The imx can support timer-based delays, so implement this. Skips past jiffy calibration. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-01-22 19:35:44 +08:00
imx_delay_timer.read_current_timer = &imx_read_current_timer;
imx_delay_timer.freq = c;
register_current_timer_delay(&imx_delay_timer);
clocksource: convert ARM 32-bit up counting clocksources Convert ixp4xx, lpc32xx, mxc, netx, pxa, sa1100, tcc8k, tegra and u300 to use the generic mmio clocksource recently introduced. Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Krzysztof Halasa <khc@pm.waw.pl> Acked-by: Eric Miao <eric.y.miao@gmail.com> Acked-by: "Hans J. Koch" <hjk@hansjkoch.de> Acked-by: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Olof Johansson <olof@lixom.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-08 21:09:47 +08:00
sched_clock_reg = reg;
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: Switch to sched_clock_register() The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface. Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-11-16 07:26:12 +08:00
sched_clock_register(mxc_read_sched_clock, 32, c);
clocksource: convert ARM 32-bit up counting clocksources Convert ixp4xx, lpc32xx, mxc, netx, pxa, sa1100, tcc8k, tegra and u300 to use the generic mmio clocksource recently introduced. Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Krzysztof Halasa <khc@pm.waw.pl> Acked-by: Eric Miao <eric.y.miao@gmail.com> Acked-by: "Hans J. Koch" <hjk@hansjkoch.de> Acked-by: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Olof Johansson <olof@lixom.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-08 21:09:47 +08:00
return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
clocksource_mmio_readl_up);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
}
/* clock event */
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
static int mx1_2_set_next_event(unsigned long evt,
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
struct clock_event_device *ced)
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
{
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
struct imx_timer *imxtm = to_imx_timer(ced);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
unsigned long tcmp;
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
-ETIME : 0;
}
mxc: Change gpt timer code to be more generic by using V2 instead of MX3 Replace mx3_ with v2_ since the register layout is the same for all SoCs using version 2 of the timer (mx25, mx31, mx37 and now mx51) Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-04-22 02:34:36 +08:00
static int v2_set_next_event(unsigned long evt,
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
struct clock_event_device *ced)
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
{
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
struct imx_timer *imxtm = to_imx_timer(ced);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
unsigned long tcmp;
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
writel_relaxed(tcmp, imxtm->base + V2_TCMP);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: return zero in case next event gets a large increment The return of v2_set_next_event() will lead to an infinite loop in tick_handle_oneshot_broadcast() - "goto again;" with imx6q WAIT mode (to be enabled). This happens because when global event did not expire any CPU local events, the broadcast device will be rearmed to a CPU local next_event, which could be far away from now and result in a max_delta_tick programming in set_next_event(). Fix the problem by detecting those next events with increments larger than 0x7fffffff, and simply return zero in that case. It leaves mx1_2_set_next_event() unchanged since only v2_set_next_event() will be running with imx6q WAIT mode support. Thanks Russell King for helping understand the problem. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-12-06 22:54:41 +08:00
return evt < 0x7fffffff &&
ARM: imx: get rid of variable timer_base We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:23:28 +08:00
(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
-ETIME : 0;
}
#ifdef DEBUG
static const char *clock_event_mode_label[] = {
[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
ARM: imx: add missing item to the list of clock event modes This prevents an out-of-bounds access to the clock_event_mode_label when debugging. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-07-17 04:07:06 +08:00
[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
[CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
};
#endif /* DEBUG */
static void mxc_set_mode(enum clock_event_mode mode,
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
struct clock_event_device *ced)
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
{
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
struct imx_timer *imxtm = to_imx_timer(ced);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
unsigned long flags;
/*
* The timer interrupt generation is disabled at least
* for enough time to call mxc_set_next_event()
*/
local_irq_save(flags);
/* Disable interrupt in GPT module */
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
imxtm->gpt->gpt_irq_disable(imxtm);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
if (mode != imxtm->cem) {
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
/* Set event time into far-far future */
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
/* Clear pending interrupt */
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
imxtm->gpt->gpt_irq_acknowledge(imxtm);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
}
#ifdef DEBUG
printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
clock_event_mode_label[imxtm->cem],
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
clock_event_mode_label[mode]);
#endif /* DEBUG */
/* Remember timer mode */
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
imxtm->cem = mode;
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
local_irq_restore(flags);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
"supported for i.MX\n");
break;
case CLOCK_EVT_MODE_ONESHOT:
/*
* Do not put overhead of interrupt enable/disable into
* mxc_set_next_event(), the core has about 4 minutes
* to call mxc_set_next_event() or shutdown clock after
* mode switching
*/
local_irq_save(flags);
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
imxtm->gpt->gpt_irq_enable(imxtm);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
local_irq_restore(flags);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
/* Left event sources disabled, no more interrupts appear */
break;
}
}
/*
* IRQ handler for the timer
*/
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
struct clock_event_device *ced = dev_id;
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
struct imx_timer *imxtm = to_imx_timer(ced);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
uint32_t tstat;
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
imxtm->gpt->gpt_irq_acknowledge(imxtm);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
ced->event_handler(ced);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
return IRQ_HANDLED;
}
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
static int __init mxc_clockevent_init(struct imx_timer *imxtm)
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
{
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
struct clock_event_device *ced = &imxtm->ced;
struct irqaction *act = &imxtm->act;
imxtm->cem = CLOCK_EVT_MODE_UNUSED;
ced->name = "mxc_timer1";
ced->features = CLOCK_EVT_FEAT_ONESHOT;
ced->set_mode = mxc_set_mode;
ced->set_next_event = imxtm->gpt->set_next_event;
ced->rating = 200;
ced->cpumask = cpumask_of(0);
clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
ARM: use clockevents_config_and_register() where possible The clockevent core is able to figure out the best mult and shift, calculate min_delta_ns and max_delta_ns, with the necessary info passed into clockevents_config_and_register(). Use this combined configure and register function where possible to make the codes less error prone and gain some positive diff stat. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Anton Vorontsov <cbouatmailru@gmail.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Tested-by: Roland Stigge <stigge@antcom.de> Acked-by: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: David Brown <davidb@codeaurora.org> Tested-by: Tony Lindgren <tony@atomide.com> Acked-by: Barry Song <baohua.song@csr.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Cc: Lennert Buytenhek <buytenh@wantstofly.org> Cc: Wan ZongShun <mcuos.com@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-01-12 19:50:05 +08:00
0xff, 0xfffffffe);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
ARM: imx: move clock event variables into imx_timer Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 16:38:49 +08:00
act->name = "i.MX Timer Tick";
act->flags = IRQF_TIMER | IRQF_IRQPOLL;
act->handler = mxc_timer_interrupt;
act->dev_id = ced;
return setup_irq(imxtm->irq, act);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
}
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
u32 tctl_val;
tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
u32 tctl_val;
tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
tctl_val |= V2_TCTL_CLK_OSC_DIV8;
else
tctl_val |= V2_TCTL_CLK_PER;
writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
{
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
u32 tctl_val;
tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
tctl_val |= V2_TCTL_CLK_OSC_DIV8;
/* 24 / 8 = 3 MHz */
writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
tctl_val |= V2_TCTL_24MEN;
} else {
tctl_val |= V2_TCTL_CLK_PER;
}
writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
ARM i.MX timer: request correct clock We used to pass the timer clock directly to mxc_timer_init. We should instead request the correct clock. This is an intermediate step: For now we request the clock in the timer code when NULL is passed as clock. Also, the gpt on some i.MX have an additional ipg clock which can be gated. Request and enable this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-03-09 16:29:27 +08:00
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
static const struct imx_gpt_data imx1_gpt_data = {
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
.reg_tstat = MX1_2_TSTAT,
.reg_tcn = MX1_2_TCN,
.reg_tcmp = MX1_2_TCMP,
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
.gpt_irq_enable = imx1_gpt_irq_enable,
.gpt_irq_disable = imx1_gpt_irq_disable,
.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
.gpt_setup_tctl = imx1_gpt_setup_tctl,
ARM: imx: set up .set_next_event hook via imx_gpt_data Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 15:51:41 +08:00
.set_next_event = mx1_2_set_next_event,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
};
static const struct imx_gpt_data imx21_gpt_data = {
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
.reg_tstat = MX1_2_TSTAT,
.reg_tcn = MX1_2_TCN,
.reg_tcmp = MX1_2_TCMP,
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
.gpt_irq_enable = imx21_gpt_irq_enable,
.gpt_irq_disable = imx21_gpt_irq_disable,
.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
.gpt_setup_tctl = imx21_gpt_setup_tctl,
ARM: imx: set up .set_next_event hook via imx_gpt_data Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 15:51:41 +08:00
.set_next_event = mx1_2_set_next_event,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
};
static const struct imx_gpt_data imx31_gpt_data = {
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
.reg_tstat = V2_TSTAT,
.reg_tcn = V2_TCN,
.reg_tcmp = V2_TCMP,
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
.gpt_irq_enable = imx31_gpt_irq_enable,
.gpt_irq_disable = imx31_gpt_irq_disable,
.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
.gpt_setup_tctl = imx31_gpt_setup_tctl,
ARM: imx: set up .set_next_event hook via imx_gpt_data Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 15:51:41 +08:00
.set_next_event = v2_set_next_event,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
};
static const struct imx_gpt_data imx6dl_gpt_data = {
ARM: imx: define gpt register offset per device type It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 21:39:55 +08:00
.reg_tstat = V2_TSTAT,
.reg_tcn = V2_TCN,
.reg_tcmp = V2_TCMP,
ARM: imx: provide gpt device specific irq functions It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 22:42:55 +08:00
.gpt_irq_enable = imx6dl_gpt_irq_enable,
.gpt_irq_disable = imx6dl_gpt_irq_disable,
.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
ARM: imx: set up .set_next_event hook via imx_gpt_data Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 15:51:41 +08:00
.set_next_event = v2_set_next_event,
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
};
static void __init _mxc_timer_init(struct imx_timer *imxtm)
{
switch (imxtm->type) {
case GPT_TYPE_IMX1:
imxtm->gpt = &imx1_gpt_data;
break;
case GPT_TYPE_IMX21:
imxtm->gpt = &imx21_gpt_data;
break;
case GPT_TYPE_IMX31:
imxtm->gpt = &imx31_gpt_data;
break;
case GPT_TYPE_IMX6DL:
imxtm->gpt = &imx6dl_gpt_data;
break;
default:
BUG();
}
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
if (IS_ERR(imxtm->clk_per)) {
ARM i.MX: remove now unnecessary argument from mxc_timer_init As the timer code now does a clk_get to get its clock we don't need the struct clk argument anymore. This also changes the alternative EPIT timer to do a clk_get. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-16 18:29:53 +08:00
pr_err("i.MX timer: unable to get clk\n");
return;
ARM i.MX timer: request correct clock We used to pass the timer clock directly to mxc_timer_init. We should instead request the correct clock. This is an intermediate step: For now we request the clock in the timer code when NULL is passed as clock. Also, the gpt on some i.MX have an additional ipg clock which can be gated. Request and enable this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-03-09 16:29:27 +08:00
}
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
if (!IS_ERR(imxtm->clk_ipg))
clk_prepare_enable(imxtm->clk_ipg);
ARM i.MX: remove now unnecessary argument from mxc_timer_init As the timer code now does a clk_get to get its clock we don't need the struct clk argument anymore. This also changes the alternative EPIT timer to do a clk_get. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-16 18:29:53 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
clk_prepare_enable(imxtm->clk_per);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
/*
* Initialise to a known state (all timers off, and timing reset)
*/
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
writel_relaxed(0, imxtm->base + MXC_TCTL);
writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
mxc timer: make compile time independent Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-02-19 03:58:40 +08:00
ARM: imx: setup tctl register in device specific function It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 14:24:41 +08:00
imxtm->gpt->gpt_setup_tctl(imxtm);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
/* init and register the timer to the framework */
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
mxc_clocksource_init(imxtm);
mxc_clockevent_init(imxtm);
i.MXC family: Adding timer support This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-05 16:02:50 +08:00
}
ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05 23:57:45 +08:00
ARM: imx: define an enum for gpt timer device type Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 11:41:39 +08:00
void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case. Use of_clk_get_by_name() for timer clocks for DT case. This patch eliminates a lot of unneeded clk_register_clkdev() calls for GPT. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-27 17:04:46 +08:00
{
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
struct imx_timer *imxtm;
imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
BUG_ON(!imxtm);
ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case. Use of_clk_get_by_name() for timer clocks for DT case. This patch eliminates a lot of unneeded clk_register_clkdev() calls for GPT. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-27 17:04:46 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
ARM: i.MX: Remove excess variable Base address for driver is global, there are no need to use intermediate variable for it. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-27 17:04:47 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
imxtm->base = ioremap(pbase, SZ_4K);
BUG_ON(!imxtm->base);
ARM: imx: define an enum for gpt timer device type Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 11:41:39 +08:00
imxtm->type = type;
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
_mxc_timer_init(imxtm);
ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case. Use of_clk_get_by_name() for timer clocks for DT case. This patch eliminates a lot of unneeded clk_register_clkdev() calls for GPT. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-27 17:04:46 +08:00
}
ARM: imx: initialize gpt device type for DT boot Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 13:38:20 +08:00
static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05 23:57:45 +08:00
{
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
struct imx_timer *imxtm;
static int initialized;
ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05 23:57:45 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
/* Support one instance only */
if (initialized)
ARM: i.MX: Use CLOCKSOURCE_OF_DECLARE() for DT targets This patch uses clocksource_of_init() call for DT targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-13 13:34:00 +08:00
return;
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
BUG_ON(!imxtm);
ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05 23:57:45 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
imxtm->base = of_iomap(np, 0);
WARN_ON(!imxtm->base);
imxtm->irq = irq_of_parse_and_map(np, 0);
imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case. Use of_clk_get_by_name() for timer clocks for DT case. This patch eliminates a lot of unneeded clk_register_clkdev() calls for GPT. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-27 17:04:46 +08:00
ARM: imx: source gpt per clk from OSC for system timer On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-11 11:29:42 +08:00
/* Try osc_per first, and fall back to per otherwise */
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
if (IS_ERR(imxtm->clk_per))
imxtm->clk_per = of_clk_get_by_name(np, "per");
ARM: imx: initialize gpt device type for DT boot Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 13:38:20 +08:00
imxtm->type = type;
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
_mxc_timer_init(imxtm);
ARM: imx: source gpt per clk from OSC for system timer On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-11 11:29:42 +08:00
ARM: imx: move timer resources into a structure Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-22 13:53:45 +08:00
initialized = 1;
ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-04-05 23:57:45 +08:00
}
ARM: imx: initialize gpt device type for DT boot Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 13:38:20 +08:00
static void __init imx1_timer_init_dt(struct device_node *np)
{
mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}
static void __init imx21_timer_init_dt(struct device_node *np)
{
mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}
static void __init imx31_timer_init_dt(struct device_node *np)
{
enum imx_gpt_type type = GPT_TYPE_IMX31;
/*
* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
* GPT device, while they actually have different programming model.
* This is a workaround to keep the existing i.MX6DL/S DTBs continue
* working with the new kernel.
*/
if (of_machine_is_compatible("fsl,imx6dl"))
type = GPT_TYPE_IMX6DL;
mxc_timer_init_dt(np, type);
}
static void __init imx6dl_timer_init_dt(struct device_node *np)
{
mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}
CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
clocksource/imx: Define clocksource for mx27 The rework of the imx clocksource driver missed to add an entry for imx27 which results in a boot failure on those machines. Add the proper CLOCKSOURCE_OF_DECLARE() entry for imx27 and map it to the imx21 init. Fixes: bef11c881ba5 'ARM: imx: initialize gpt device type for DT boot' Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: daniel.lezcano@linaro.org Cc: fabio.estevam@freescale.com Cc: shawnguo@kernel.org Cc: kernel@pengutronix.de Link: http://lkml.kernel.org/r/1435439504-406-1-git-send-email-tremyfr@gmail.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-28 05:11:44 +08:00
CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
ARM: imx: initialize gpt device type for DT boot Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-05-15 13:38:20 +08:00
CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);