2005-11-10 22:26:53 +08:00
|
|
|
/*
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 13:09:12 +08:00
|
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* OMAP clock: data structure definitions, function prototypes, shared macros
|
2005-11-10 22:26:53 +08:00
|
|
|
*
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 13:09:12 +08:00
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* Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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2005-11-10 22:26:53 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_OMAP_CLOCK_H
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#define __ARCH_ARM_OMAP_CLOCK_H
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2009-12-09 07:21:29 +08:00
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#include <linux/list.h>
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2005-11-10 22:26:53 +08:00
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struct module;
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2008-03-18 16:35:15 +08:00
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struct clk;
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2008-08-19 16:08:44 +08:00
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struct clockdomain;
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2008-03-18 16:35:15 +08:00
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2008-11-04 22:02:46 +08:00
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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2010-02-25 03:05:54 +08:00
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void (*find_idlest)(struct clk *, void __iomem **,
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u8 *, u8 *);
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void (*find_companion)(struct clk *, void __iomem **,
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u8 *);
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2008-11-04 22:02:46 +08:00
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};
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2010-02-13 04:26:48 +08:00
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#ifdef CONFIG_ARCH_OMAP2PLUS
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2008-03-18 16:35:15 +08:00
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struct clksel_rate {
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u32 val;
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2008-11-05 05:50:46 +08:00
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u8 div;
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2008-03-18 16:35:15 +08:00
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u8 flags;
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};
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 13:09:12 +08:00
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/**
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* struct dpll_data - DPLL registers and integration data
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* @mult_div1_reg: register containing the DPLL M and N bitfields
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* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
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* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
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* @clk_bypass: struct clk pointer to the clock's bypass clock input
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* @clk_ref: struct clk pointer to the clock's reference clock input
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* @control_reg: register containing the DPLL mode bitfield
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg
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* @rate_tolerance: maximum variance allowed from target rate (in Hz)
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
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* @max_multiplier: maximum valid non-bypass multiplier value (actual)
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* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
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* @min_divider: minimum valid non-bypass divider value (actual)
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* @max_divider: maximum valid non-bypass divider value (actual)
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* @modes: possible values of @enable_mask
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* @autoidle_reg: register containing the DPLL autoidle mode bitfield
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* @idlest_reg: register containing the DPLL idle status bitfield
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* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
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* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
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* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
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* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
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* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
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* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
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* @flags: DPLL type/features (see below)
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*
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* Possible values for @flags:
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* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
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* NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
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* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
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*
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically
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* correct to only have one @clk_bypass pointer.
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*
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* XXX @rate_tolerance should probably be deprecated - currently there
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* don't seem to be any usecases for DPLL rounding that is not exact.
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*
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
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* @last_rounded_n) should be separated from the runtime-fixed fields
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* and placed into a differenct structure, so that the runtime-fixed data
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* can be placed into read-only space.
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2010-02-23 13:09:08 +08:00
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*/
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2008-03-18 16:35:15 +08:00
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struct dpll_data {
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void __iomem *mult_div1_reg;
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u32 mult_mask;
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u32 div1_mask;
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[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 21:29:22 +08:00
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struct clk *clk_bypass;
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struct clk *clk_ref;
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void __iomem *control_reg;
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u32 enable_mask;
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2008-11-05 05:50:46 +08:00
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unsigned int rate_tolerance;
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unsigned long last_rounded_rate;
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 17:24:46 +08:00
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u16 last_rounded_m;
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 13:09:12 +08:00
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u16 max_multiplier;
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 17:24:46 +08:00
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u8 last_rounded_n;
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2009-01-29 03:08:44 +08:00
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u8 min_divider;
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 17:24:46 +08:00
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u8 max_divider;
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2008-07-03 17:24:45 +08:00
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u8 modes;
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OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 13:09:12 +08:00
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|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
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2008-11-05 05:50:46 +08:00
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void __iomem *autoidle_reg;
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void __iomem *idlest_reg;
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u32 autoidle_mask;
|
2009-01-28 10:12:47 +08:00
|
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|
u32 freqsel_mask;
|
2009-01-29 03:08:17 +08:00
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|
|
u32 idlest_mask;
|
2008-03-18 17:24:28 +08:00
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|
u8 auto_recal_bit;
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|
u8 recal_en_bit;
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|
|
u8 recal_st_bit;
|
2010-02-23 13:09:08 +08:00
|
|
|
u8 flags;
|
2008-03-18 17:24:28 +08:00
|
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# endif
|
2008-03-18 16:35:15 +08:00
|
|
|
};
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#endif
|
2005-11-10 22:26:53 +08:00
|
|
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|
struct clk {
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|
struct list_head node;
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2008-11-04 22:02:46 +08:00
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const struct clkops *ops;
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2005-11-10 22:26:53 +08:00
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const char *name;
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struct clk *parent;
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2009-01-31 18:05:51 +08:00
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struct list_head children;
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struct list_head sibling; /* node for children */
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2005-11-10 22:26:53 +08:00
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unsigned long rate;
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void __iomem *enable_reg;
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2009-02-12 18:12:59 +08:00
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unsigned long (*recalc)(struct clk *);
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2005-11-10 22:26:53 +08:00
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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2008-11-05 05:50:46 +08:00
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__u8 enable_bit;
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__s8 usecount;
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2010-01-27 11:12:57 +08:00
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u8 fixed_div;
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2010-02-23 13:09:18 +08:00
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u8 flags;
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2010-02-13 04:26:48 +08:00
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#ifdef CONFIG_ARCH_OMAP2PLUS
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2008-03-18 16:35:15 +08:00
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void __iomem *clksel_reg;
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u32 clksel_mask;
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const struct clksel *clksel;
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 17:24:46 +08:00
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struct dpll_data *dpll_data;
|
2008-08-19 16:08:44 +08:00
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const char *clkdm_name;
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struct clockdomain *clkdm;
|
2008-03-18 16:35:15 +08:00
|
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|
#else
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__u8 rate_offset;
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|
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__u8 src_offset;
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|
|
#endif
|
2008-07-03 17:24:41 +08:00
|
|
|
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
|
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struct dentry *dent; /* For visible tree hierarchy */
|
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|
#endif
|
2005-11-10 22:26:53 +08:00
|
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|
};
|
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|
2008-05-22 23:38:50 +08:00
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|
struct cpufreq_frequency_table;
|
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|
2005-11-10 22:26:53 +08:00
|
|
|
struct clk_functions {
|
|
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|
int (*clk_enable)(struct clk *clk);
|
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|
void (*clk_disable)(struct clk *clk);
|
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|
|
long (*clk_round_rate)(struct clk *clk, unsigned long rate);
|
|
|
|
|
int (*clk_set_rate)(struct clk *clk, unsigned long rate);
|
|
|
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|
int (*clk_set_parent)(struct clk *clk, struct clk *parent);
|
|
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|
|
void (*clk_allow_idle)(struct clk *clk);
|
|
|
|
|
void (*clk_deny_idle)(struct clk *clk);
|
2006-09-25 18:27:20 +08:00
|
|
|
void (*clk_disable_unused)(struct clk *clk);
|
2008-05-22 23:38:50 +08:00
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
|
void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
|
2010-01-09 06:23:16 +08:00
|
|
|
void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
|
2008-05-22 23:38:50 +08:00
|
|
|
#endif
|
2005-11-10 22:26:53 +08:00
|
|
|
};
|
|
|
|
|
|
2010-01-27 11:13:11 +08:00
|
|
|
extern int mpurate;
|
2005-11-10 22:26:53 +08:00
|
|
|
|
2009-01-28 10:12:50 +08:00
|
|
|
extern int clk_init(struct clk_functions *custom_clocks);
|
2009-05-13 07:50:30 +08:00
|
|
|
extern void clk_preinit(struct clk *clk);
|
2005-11-10 22:26:53 +08:00
|
|
|
extern int clk_register(struct clk *clk);
|
2009-01-31 18:05:51 +08:00
|
|
|
extern void clk_reparent(struct clk *child, struct clk *parent);
|
2005-11-10 22:26:53 +08:00
|
|
|
extern void clk_unregister(struct clk *clk);
|
|
|
|
|
extern void propagate_rate(struct clk *clk);
|
2008-03-18 16:35:15 +08:00
|
|
|
extern void recalculate_root_clocks(void);
|
2009-02-12 18:12:59 +08:00
|
|
|
extern unsigned long followparent_recalc(struct clk *clk);
|
2008-03-18 16:35:15 +08:00
|
|
|
extern void clk_enable_init_clocks(void);
|
2010-01-27 11:12:57 +08:00
|
|
|
unsigned long omap_fixed_divisor_recalc(struct clk *clk);
|
2009-01-28 10:13:38 +08:00
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
|
extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
|
2010-01-09 06:23:16 +08:00
|
|
|
extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
|
2009-01-28 10:13:38 +08:00
|
|
|
#endif
|
2005-11-10 22:26:53 +08:00
|
|
|
|
2008-11-05 00:35:03 +08:00
|
|
|
extern const struct clkops clkops_null;
|
|
|
|
|
|
2005-11-10 22:26:53 +08:00
|
|
|
/* Clock flags */
|
2010-02-23 13:09:18 +08:00
|
|
|
#define RATE_FIXED (1 << 0) /* Fixed clock rate */
|
|
|
|
|
#define ENABLE_REG_32BIT (1 << 1) /* Use 32-bit access */
|
|
|
|
|
#define CLOCK_IDLE_CONTROL (1 << 2)
|
|
|
|
|
#define CLOCK_NO_IDLE_PARENT (1 << 3)
|
2010-02-23 13:09:24 +08:00
|
|
|
#define ENABLE_ON_INIT (1 << 4) /* Enable upon framework init */
|
|
|
|
|
#define INVERT_ENABLE (1 << 5) /* 0 enables, 1 disables */
|
|
|
|
|
#define ALWAYS_ENABLED (1 << 6)
|
2008-03-18 16:35:15 +08:00
|
|
|
|
|
|
|
|
/* Clksel_rate flags */
|
|
|
|
|
#define DEFAULT_RATE (1 << 0)
|
|
|
|
|
#define RATE_IN_242X (1 << 1)
|
|
|
|
|
#define RATE_IN_243X (1 << 2)
|
|
|
|
|
#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 13:09:12 +08:00
|
|
|
#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
|
2010-02-23 13:09:09 +08:00
|
|
|
#define RATE_IN_36XX (1 << 5)
|
|
|
|
|
#define RATE_IN_4430 (1 << 6)
|
2008-03-18 16:35:15 +08:00
|
|
|
|
|
|
|
|
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
|
|
|
|
|
|
2005-11-10 22:26:53 +08:00
|
|
|
|
|
|
|
|
#endif
|