2017-03-04 07:37:23 +08:00
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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2019-06-10 06:07:57 +08:00
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#include <linux/module.h>
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#include <linux/pci.h>
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2017-03-04 07:37:23 +08:00
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v3_1.h"
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2017-11-15 18:39:21 +08:00
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#include "mp/mp_9_0_offset.h"
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#include "mp/mp_9_0_sh_mask.h"
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2017-11-24 10:29:00 +08:00
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#include "gc/gc_9_0_offset.h"
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2017-11-15 16:01:30 +08:00
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#include "sdma0/sdma0_4_0_offset.h"
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2017-11-23 14:54:48 +08:00
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#include "nbio/nbio_6_1_offset.h"
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2017-03-04 07:37:23 +08:00
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2018-11-02 22:00:16 +08:00
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#include "oss/osssys_4_0_offset.h"
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#include "oss/osssys_4_0_sh_mask.h"
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2017-03-04 07:37:23 +08:00
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MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
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MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
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2018-03-07 11:18:09 +08:00
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MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
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MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
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2018-04-20 13:36:54 +08:00
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2017-03-04 07:37:23 +08:00
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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2018-05-12 12:31:12 +08:00
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static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554};
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2019-02-25 18:41:02 +08:00
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static bool psp_v3_1_support_vmr_ring(struct psp_context *psp);
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static int psp_v3_1_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type);
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2018-01-24 05:17:24 +08:00
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static int psp_v3_1_init_microcode(struct psp_context *psp)
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2017-03-04 07:37:23 +08:00
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{
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struct amdgpu_device *adev = psp->adev;
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const char *chip_name;
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char fw_name[30];
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int err = 0;
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const struct psp_firmware_header_v1_0 *hdr;
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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chip_name = "vega10";
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break;
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2018-02-07 09:34:22 +08:00
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case CHIP_VEGA12:
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chip_name = "vega12";
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break;
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2017-03-04 07:37:23 +08:00
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default: BUG();
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}
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
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err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
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if (err)
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goto out;
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err = amdgpu_ucode_validate(adev->psp.sos_fw);
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if (err)
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goto out;
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hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
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adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
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adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
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adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
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adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
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le32_to_cpu(hdr->sos_size_bytes);
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adev->psp.sys_start_addr = (uint8_t *)hdr +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes);
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adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
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le32_to_cpu(hdr->sos_offset_bytes);
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
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err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
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if (err)
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goto out;
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err = amdgpu_ucode_validate(adev->psp.asd_fw);
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if (err)
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goto out;
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hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
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adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
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adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
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adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
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adev->psp.asd_start_addr = (uint8_t *)hdr +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes);
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return 0;
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out:
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if (err) {
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dev_err(adev->dev,
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"psp v3.1: Failed to load firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->psp.sos_fw);
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adev->psp.sos_fw = NULL;
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release_firmware(adev->psp.asd_fw);
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adev->psp.asd_fw = NULL;
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}
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return err;
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}
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2018-01-24 05:17:24 +08:00
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static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
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2017-03-04 07:37:23 +08:00
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{
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int ret;
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uint32_t psp_gfxdrv_command_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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2017-03-22 10:16:05 +08:00
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uint32_t sol_reg;
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2017-03-28 19:48:10 +08:00
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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2017-06-13 01:45:30 +08:00
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sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
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2017-03-28 19:48:10 +08:00
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if (sol_reg)
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return 0;
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2017-03-04 07:37:23 +08:00
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/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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if (ret)
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return ret;
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2017-03-22 10:16:05 +08:00
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memset(psp->fw_pri_buf, 0, PSP_1_MEG);
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2017-03-04 07:37:23 +08:00
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/* Copy PSP System Driver binary to memory */
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2017-03-22 10:16:05 +08:00
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memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
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2017-03-04 07:37:23 +08:00
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2018-10-17 06:47:54 +08:00
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/* Provide the sys driver to bootloader */
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2017-06-13 01:45:30 +08:00
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
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2017-03-22 10:16:05 +08:00
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(uint32_t)(psp->fw_pri_mc_addr >> 20));
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2019-07-11 22:02:02 +08:00
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psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
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2017-06-13 01:45:30 +08:00
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
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2017-03-04 07:37:23 +08:00
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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return ret;
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}
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2018-05-12 12:31:12 +08:00
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static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
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{
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int i;
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if (ver == adev->psp.sos_fw_version)
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return true;
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/*
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* Double check if the latest four legacy versions.
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* If yes, it is still the right version.
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*/
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for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) {
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if (sos_old_versions[i] == adev->psp.sos_fw_version)
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return true;
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}
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return false;
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}
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2018-01-24 05:17:24 +08:00
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static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
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2017-03-04 07:37:23 +08:00
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{
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int ret;
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unsigned int psp_gfxdrv_command_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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2018-05-12 12:31:12 +08:00
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uint32_t sol_reg, ver;
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2017-03-28 19:48:10 +08:00
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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2017-06-13 01:45:30 +08:00
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sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
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2018-12-12 18:08:24 +08:00
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if (sol_reg) {
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psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
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printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
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2017-03-28 19:48:10 +08:00
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return 0;
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2018-12-12 18:08:24 +08:00
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}
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2017-03-04 07:37:23 +08:00
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/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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if (ret)
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return ret;
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2017-03-22 10:16:05 +08:00
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memset(psp->fw_pri_buf, 0, PSP_1_MEG);
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2017-03-04 07:37:23 +08:00
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/* Copy Secure OS binary to PSP memory */
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2017-03-22 10:16:05 +08:00
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memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
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2017-03-04 07:37:23 +08:00
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2018-10-17 06:47:54 +08:00
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/* Provide the PSP secure OS to bootloader */
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2017-06-13 01:45:30 +08:00
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
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2017-03-22 10:16:05 +08:00
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(uint32_t)(psp->fw_pri_mc_addr >> 20));
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2019-07-11 22:02:02 +08:00
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psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
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2017-06-13 01:45:30 +08:00
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
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2017-03-04 07:37:23 +08:00
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
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2017-06-13 01:45:30 +08:00
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RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
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2017-03-04 07:37:23 +08:00
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0, true);
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2018-05-12 12:31:12 +08:00
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ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
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if (!psp_v3_1_match_version(adev, ver))
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DRM_WARN("SOS version doesn't match\n");
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2017-03-04 07:37:23 +08:00
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return ret;
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}
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2018-01-24 05:17:24 +08:00
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static int psp_v3_1_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type)
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2017-03-04 07:37:23 +08:00
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{
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int ret = 0;
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struct psp_ring *ring;
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struct amdgpu_device *adev = psp->adev;
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ring = &psp->km_ring;
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ring->ring_type = ring_type;
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/* allocate 4k Page of Local Frame Buffer memory for ring */
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ring->ring_size = 0x1000;
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ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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if (ret) {
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ring->ring_size = 0;
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return ret;
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}
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2017-03-21 18:36:57 +08:00
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return 0;
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}
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2018-11-02 22:00:16 +08:00
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static void psp_v3_1_reroute_ih(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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uint32_t tmp;
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/* Change IH ring for VMC */
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tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
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mdelay(20);
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psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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/* Change IH ring for UMC */
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tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
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|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
|
|
|
|
|
|
|
|
mdelay(20);
|
|
|
|
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
|
|
|
|
0x80000000, 0x8000FFFF, false);
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static int psp_v3_1_ring_create(struct psp_context *psp,
|
|
|
|
enum psp_ring_type ring_type)
|
2017-03-21 18:36:57 +08:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
unsigned int psp_ring_reg = 0;
|
|
|
|
struct psp_ring *ring = &psp->km_ring;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
|
2018-11-02 22:00:16 +08:00
|
|
|
psp_v3_1_reroute_ih(psp);
|
|
|
|
|
2019-02-25 18:41:02 +08:00
|
|
|
if (psp_v3_1_support_vmr_ring(psp)) {
|
|
|
|
ret = psp_v3_1_ring_stop(psp, ring_type);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write low address of the ring to C2PMSG_102 */
|
|
|
|
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
|
|
|
|
/* Write high address of the ring to C2PMSG_103 */
|
|
|
|
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
|
|
|
|
/* No size initialization for sriov */
|
|
|
|
/* Write the ring initialization command to C2PMSG_101 */
|
|
|
|
psp_ring_reg = ring_type;
|
|
|
|
psp_ring_reg = psp_ring_reg << 16;
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
|
|
|
|
|
|
|
|
/* there might be hardware handshake issue which needs delay */
|
|
|
|
mdelay(20);
|
|
|
|
|
|
|
|
/* Wait for response flag (bit 31) in C2PMSG_101 */
|
|
|
|
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
|
|
|
|
mmMP0_SMN_C2PMSG_101), 0x80000000,
|
|
|
|
0x8000FFFF, false);
|
|
|
|
} else {
|
|
|
|
|
|
|
|
/* Write low address of the ring to C2PMSG_69 */
|
|
|
|
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
|
|
|
|
/* Write high address of the ring to C2PMSG_70 */
|
|
|
|
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
|
|
|
|
/* Write size of ring to C2PMSG_71 */
|
|
|
|
psp_ring_reg = ring->ring_size;
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
|
|
|
|
/* Write the ring initialization command to C2PMSG_64 */
|
|
|
|
psp_ring_reg = ring_type;
|
|
|
|
psp_ring_reg = psp_ring_reg << 16;
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
|
|
|
|
|
|
|
|
/* there might be hardware handshake issue which needs delay */
|
|
|
|
mdelay(20);
|
|
|
|
|
|
|
|
/* Wait for response flag (bit 31) in C2PMSG_64 */
|
|
|
|
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
|
|
|
|
mmMP0_SMN_C2PMSG_64), 0x80000000,
|
|
|
|
0x8000FFFF, false);
|
2017-03-04 07:37:23 +08:00
|
|
|
|
2019-02-25 18:41:02 +08:00
|
|
|
}
|
2017-03-04 07:37:23 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static int psp_v3_1_ring_stop(struct psp_context *psp,
|
|
|
|
enum psp_ring_type ring_type)
|
2017-04-17 20:50:18 +08:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
unsigned int psp_ring_reg = 0;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
|
2019-02-25 18:41:02 +08:00
|
|
|
if (psp_v3_1_support_vmr_ring(psp)) {
|
|
|
|
/* Write the Destroy GPCOM ring command to C2PMSG_101 */
|
|
|
|
psp_ring_reg = GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING;
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
|
|
|
|
|
|
|
|
/* there might be handshake issue which needs delay */
|
|
|
|
mdelay(20);
|
|
|
|
|
|
|
|
/* Wait for response flag (bit 31) in C2PMSG_101 */
|
|
|
|
ret = psp_wait_for(psp,
|
|
|
|
SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
|
|
|
|
0x80000000, 0x80000000, false);
|
|
|
|
} else {
|
|
|
|
/* Write the ring destroy command to C2PMSG_64 */
|
|
|
|
psp_ring_reg = 3 << 16;
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
|
|
|
|
|
|
|
|
/* there might be handshake issue which needs delay */
|
|
|
|
mdelay(20);
|
|
|
|
|
|
|
|
/* Wait for response flag (bit 31) in C2PMSG_64 */
|
|
|
|
ret = psp_wait_for(psp,
|
|
|
|
SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
|
|
|
|
0x80000000, 0x80000000, false);
|
|
|
|
}
|
2017-04-17 20:50:18 +08:00
|
|
|
|
2017-09-08 13:04:52 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static int psp_v3_1_ring_destroy(struct psp_context *psp,
|
|
|
|
enum psp_ring_type ring_type)
|
2017-09-08 13:04:52 +08:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct psp_ring *ring = &psp->km_ring;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
|
|
|
|
ret = psp_v3_1_ring_stop(psp, ring_type);
|
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("Fail to stop psp ring\n");
|
|
|
|
|
2017-06-02 10:42:28 +08:00
|
|
|
amdgpu_bo_free_kernel(&adev->firmware.rbuf,
|
|
|
|
&ring->ring_mem_mc_addr,
|
|
|
|
(void **)&ring->ring_mem);
|
|
|
|
|
2017-04-17 20:50:18 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static int psp_v3_1_cmd_submit(struct psp_context *psp,
|
|
|
|
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
|
|
|
|
int index)
|
2017-03-04 07:37:23 +08:00
|
|
|
{
|
|
|
|
unsigned int psp_write_ptr_reg = 0;
|
|
|
|
struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
|
|
|
|
struct psp_ring *ring = &psp->km_ring;
|
2017-10-16 16:51:28 +08:00
|
|
|
struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
|
|
|
|
struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
|
|
|
|
ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
|
2017-03-04 07:37:23 +08:00
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
uint32_t ring_size_dw = ring->ring_size / 4;
|
|
|
|
uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
|
|
|
|
|
|
|
|
/* KM (GPCOM) prepare write pointer */
|
2019-02-25 18:41:02 +08:00
|
|
|
if (psp_v3_1_support_vmr_ring(psp))
|
|
|
|
psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
|
|
|
|
else
|
|
|
|
psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
|
2017-03-04 07:37:23 +08:00
|
|
|
|
|
|
|
/* Update KM RB frame pointer to new frame */
|
|
|
|
/* write_frame ptr increments by size of rb_frame in bytes */
|
|
|
|
/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
|
|
|
|
if ((psp_write_ptr_reg % ring_size_dw) == 0)
|
2017-10-16 16:51:28 +08:00
|
|
|
write_frame = ring_buffer_start;
|
2017-03-04 07:37:23 +08:00
|
|
|
else
|
2017-10-16 16:51:28 +08:00
|
|
|
write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
|
|
|
|
/* Check invalid write_frame ptr address */
|
|
|
|
if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
|
|
|
|
DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
|
|
|
|
ring_buffer_start, ring_buffer_end, write_frame);
|
|
|
|
DRM_ERROR("write_frame is pointing to address out of bounds\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-03-04 07:37:23 +08:00
|
|
|
|
|
|
|
/* Initialize KM RB frame */
|
|
|
|
memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
|
|
|
|
|
|
|
|
/* Update KM RB frame */
|
2017-06-23 06:26:33 +08:00
|
|
|
write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
|
|
|
|
write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
|
|
|
|
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
|
|
|
|
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
|
2017-03-04 07:37:23 +08:00
|
|
|
write_frame->fence_value = index;
|
2019-09-18 04:12:18 +08:00
|
|
|
amdgpu_asic_flush_hdp(adev, NULL);
|
2017-03-04 07:37:23 +08:00
|
|
|
|
|
|
|
/* Update the write Pointer in DWORDs */
|
|
|
|
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
|
2019-02-25 18:41:02 +08:00
|
|
|
if (psp_v3_1_support_vmr_ring(psp)) {
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
|
|
|
|
/* send interrupt to PSP for SRIOV ring write pointer update */
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
|
|
|
|
GFX_CTRL_CMD_ID_CONSUME_CMD);
|
|
|
|
} else
|
|
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
|
2017-03-04 07:37:23 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2017-11-30 02:51:32 +08:00
|
|
|
psp_v3_1_sram_map(struct amdgpu_device *adev,
|
2018-01-24 05:17:24 +08:00
|
|
|
unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
|
|
|
|
unsigned int *sram_data_reg_offset,
|
|
|
|
enum AMDGPU_UCODE_ID ucode_id)
|
2017-03-04 07:37:23 +08:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
switch(ucode_id) {
|
|
|
|
/* TODO: needs to confirm */
|
|
|
|
#if 0
|
|
|
|
case AMDGPU_UCODE_ID_SMC:
|
|
|
|
*sram_offset = 0;
|
|
|
|
*sram_addr_reg_offset = 0;
|
|
|
|
*sram_data_reg_offset = 0;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_CE:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_PFP:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_ME:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_MEC1:
|
|
|
|
*sram_offset = 0x10000;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_CP_MEC2:
|
|
|
|
*sram_offset = 0x10000;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_RLC_G:
|
|
|
|
*sram_offset = 0x2000;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_SDMA0:
|
|
|
|
*sram_offset = 0x0;
|
|
|
|
*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
|
|
|
|
*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* TODO: needs to confirm */
|
|
|
|
#if 0
|
|
|
|
case AMDGPU_UCODE_ID_SDMA1:
|
|
|
|
*sram_offset = ;
|
|
|
|
*sram_addr_reg_offset = ;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_UVD:
|
|
|
|
*sram_offset = ;
|
|
|
|
*sram_addr_reg_offset = ;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_VCE:
|
|
|
|
*sram_offset = ;
|
|
|
|
*sram_addr_reg_offset = ;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
case AMDGPU_UCODE_ID_MAXIMUM:
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
|
|
|
struct amdgpu_firmware_info *ucode,
|
|
|
|
enum AMDGPU_UCODE_ID ucode_type)
|
2017-03-04 07:37:23 +08:00
|
|
|
{
|
|
|
|
int err = 0;
|
|
|
|
unsigned int fw_sram_reg_val = 0;
|
|
|
|
unsigned int fw_sram_addr_reg_offset = 0;
|
|
|
|
unsigned int fw_sram_data_reg_offset = 0;
|
|
|
|
unsigned int ucode_size;
|
|
|
|
uint32_t *ucode_mem = NULL;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
|
2017-11-30 02:51:32 +08:00
|
|
|
err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
|
2017-03-04 07:37:23 +08:00
|
|
|
&fw_sram_data_reg_offset, ucode_type);
|
|
|
|
if (err)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
|
|
|
|
|
|
|
|
ucode_size = ucode->ucode_size;
|
|
|
|
ucode_mem = (uint32_t *)ucode->kaddr;
|
2017-04-04 23:36:20 +08:00
|
|
|
while (ucode_size) {
|
2017-03-04 07:37:23 +08:00
|
|
|
fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
|
|
|
|
|
|
|
|
if (*ucode_mem != fw_sram_reg_val)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
ucode_mem++;
|
|
|
|
/* 4 bytes */
|
|
|
|
ucode_size -= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
|
2017-03-04 07:37:23 +08:00
|
|
|
{
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
2017-04-04 23:40:13 +08:00
|
|
|
uint32_t reg;
|
2017-03-04 07:37:23 +08:00
|
|
|
|
2019-02-25 15:02:44 +08:00
|
|
|
reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
|
2017-04-04 23:40:13 +08:00
|
|
|
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
|
2017-03-04 07:37:23 +08:00
|
|
|
}
|
2017-09-14 16:25:19 +08:00
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static int psp_v3_1_mode1_reset(struct psp_context *psp)
|
2017-09-14 16:25:19 +08:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
uint32_t offset;
|
|
|
|
struct amdgpu_device *adev = psp->adev;
|
|
|
|
|
|
|
|
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
|
|
|
|
|
|
|
|
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
DRM_INFO("psp is not working correctly before mode1 reset!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*send the mode 1 reset command*/
|
2018-11-17 02:22:38 +08:00
|
|
|
WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
|
2017-09-14 16:25:19 +08:00
|
|
|
|
2018-12-01 01:24:33 +08:00
|
|
|
msleep(500);
|
2017-09-14 16:25:19 +08:00
|
|
|
|
|
|
|
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
|
|
|
|
|
|
|
|
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
DRM_INFO("psp mode 1 reset failed!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_INFO("psp mode1 reset succeed \n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2018-01-24 05:17:24 +08:00
|
|
|
|
2019-02-25 18:41:02 +08:00
|
|
|
static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
|
|
|
|
{
|
2019-07-30 17:32:27 +08:00
|
|
|
if (amdgpu_sriov_vf(psp->adev))
|
2019-02-25 18:41:02 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-01-24 05:17:24 +08:00
|
|
|
static const struct psp_funcs psp_v3_1_funcs = {
|
|
|
|
.init_microcode = psp_v3_1_init_microcode,
|
|
|
|
.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
|
|
|
|
.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
|
|
|
|
.ring_init = psp_v3_1_ring_init,
|
|
|
|
.ring_create = psp_v3_1_ring_create,
|
|
|
|
.ring_stop = psp_v3_1_ring_stop,
|
|
|
|
.ring_destroy = psp_v3_1_ring_destroy,
|
|
|
|
.cmd_submit = psp_v3_1_cmd_submit,
|
|
|
|
.compare_sram_data = psp_v3_1_compare_sram_data,
|
|
|
|
.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
|
|
|
|
.mode1_reset = psp_v3_1_mode1_reset,
|
2019-02-25 18:41:02 +08:00
|
|
|
.support_vmr_ring = psp_v3_1_support_vmr_ring,
|
2018-01-24 05:17:24 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
void psp_v3_1_set_psp_funcs(struct psp_context *psp)
|
|
|
|
{
|
|
|
|
psp->funcs = &psp_v3_1_funcs;
|
|
|
|
}
|