2021-11-20 00:32:15 +08:00
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====================
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eBPF Instruction Set
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====================
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2021-12-23 18:19:04 +08:00
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Registers and calling convention
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================================
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eBPF has 10 general purpose registers and a read-only frame pointer register,
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all of which are 64-bits wide.
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The eBPF calling convention is defined as:
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* R0: return value from function calls, and exit value for eBPF programs
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* R1 - R5: arguments for function calls
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* R6 - R9: callee saved registers that function calls will preserve
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* R10: read-only frame pointer to access stack
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R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if
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necessary across calls.
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2021-11-20 00:32:15 +08:00
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2022-01-04 02:35:51 +08:00
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Instruction encoding
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====================
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eBPF uses 64-bit instructions with the following encoding:
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============= ======= =============== ==================== ============
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32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
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============= ======= =============== ==================== ============
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immediate offset source register destination register opcode
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============= ======= =============== ==================== ============
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Note that most instructions do not use all of the fields.
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Unused fields shall be cleared to zero.
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2021-12-23 18:19:05 +08:00
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Instruction classes
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2022-01-04 02:35:51 +08:00
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-------------------
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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The three LSB bits of the 'opcode' field store the instruction class:
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2021-11-20 00:32:15 +08:00
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2022-01-04 02:35:53 +08:00
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========= ===== ===============================
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class value description
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========= ===== ===============================
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BPF_LD 0x00 non-standard load operations
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BPF_LDX 0x01 load into register operations
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BPF_ST 0x02 store from immediate operations
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BPF_STX 0x03 store from register operations
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BPF_ALU 0x04 32-bit arithmetic operations
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BPF_JMP 0x05 64-bit jump operations
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BPF_JMP32 0x06 32-bit jump operations
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BPF_ALU64 0x07 64-bit arithmetic operations
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========= ===== ===============================
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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Arithmetic and jump instructions
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================================
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For arithmetic and jump instructions (BPF_ALU, BPF_ALU64, BPF_JMP and
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BPF_JMP32), the 8-bit 'opcode' field is divided into three parts:
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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============== ====== =================
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4 bits (MSB) 1 bit 3 bits (LSB)
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============== ====== =================
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operation code source instruction class
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============== ====== =================
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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The 4th bit encodes the source operand:
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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====== ===== ========================================
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source value description
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====== ===== ========================================
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BPF_K 0x00 use 32-bit immediate as source operand
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BPF_X 0x08 use 'src_reg' register as source operand
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====== ===== ========================================
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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The four MSB bits store the operation code.
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2021-11-20 00:32:15 +08:00
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2022-01-04 02:35:52 +08:00
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Arithmetic instructions
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-----------------------
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BPF_ALU uses 32-bit wide operands while BPF_ALU64 uses 64-bit wide operands for
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otherwise identical operations.
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The code field encodes the operation as below:
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2021-12-23 18:19:05 +08:00
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======== ===== =========================
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code value description
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======== ===== =========================
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2021-11-20 00:32:15 +08:00
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BPF_ADD 0x00
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BPF_SUB 0x10
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BPF_MUL 0x20
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BPF_DIV 0x30
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BPF_OR 0x40
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BPF_AND 0x50
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BPF_LSH 0x60
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BPF_RSH 0x70
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BPF_NEG 0x80
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BPF_MOD 0x90
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BPF_XOR 0xa0
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2021-12-23 18:19:05 +08:00
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BPF_MOV 0xb0 mov reg to reg
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BPF_ARSH 0xc0 sign extending shift right
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BPF_END 0xd0 endianness conversion
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======== ===== =========================
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2021-11-20 00:32:15 +08:00
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2022-01-04 02:35:52 +08:00
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BPF_ADD | BPF_X | BPF_ALU means::
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dst_reg = (u32) dst_reg + (u32) src_reg;
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BPF_ADD | BPF_X | BPF_ALU64 means::
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dst_reg = dst_reg + src_reg
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BPF_XOR | BPF_K | BPF_ALU means::
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src_reg = (u32) src_reg ^ (u32) imm32
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BPF_XOR | BPF_K | BPF_ALU64 means::
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src_reg = src_reg ^ imm32
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Jump instructions
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-----------------
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BPF_JMP32 uses 32-bit wide operands while BPF_JMP uses 64-bit wide operands for
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otherwise identical operations.
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The code field encodes the operation as below:
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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======== ===== =========================
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code value description
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======== ===== =========================
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BPF_JA 0x00 BPF_JMP only
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2021-11-20 00:32:15 +08:00
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BPF_JEQ 0x10
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BPF_JGT 0x20
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BPF_JGE 0x30
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BPF_JSET 0x40
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2021-12-23 18:19:05 +08:00
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BPF_JNE 0x50 jump '!='
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BPF_JSGT 0x60 signed '>'
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BPF_JSGE 0x70 signed '>='
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BPF_CALL 0x80 function call
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BPF_EXIT 0x90 function return
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BPF_JLT 0xa0 unsigned '<'
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BPF_JLE 0xb0 unsigned '<='
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BPF_JSLT 0xc0 signed '<'
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BPF_JSLE 0xd0 signed '<='
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======== ===== =========================
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2021-12-23 18:19:04 +08:00
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2022-01-04 02:35:52 +08:00
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The eBPF program needs to store the return value into register R0 before doing a
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BPF_EXIT.
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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Load and store instructions
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===========================
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For load and store instructions (BPF_LD, BPF_LDX, BPF_ST and BPF_STX), the
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8-bit 'opcode' field is divided as:
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============ ====== =================
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3 bits (MSB) 2 bits 3 bits (LSB)
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============ ====== =================
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mode size instruction class
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============ ====== =================
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The size modifier is one of:
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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============= ===== =====================
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size modifier value description
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============= ===== =====================
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BPF_W 0x00 word (4 bytes)
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BPF_H 0x08 half word (2 bytes)
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BPF_B 0x10 byte
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BPF_DW 0x18 double word (8 bytes)
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============= ===== =====================
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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The mode modifier is one of:
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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============= ===== =====================
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mode modifier value description
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============= ===== =====================
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BPF_IMM 0x00 used for 64-bit mov
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BPF_ABS 0x20
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BPF_IND 0x40
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BPF_MEM 0x60
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BPF_ATOMIC 0xc0 atomic operations
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============= ===== =====================
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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BPF_MEM | <size> | BPF_STX means::
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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*(size *) (dst_reg + off) = src_reg
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2021-12-23 18:19:05 +08:00
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BPF_MEM | <size> | BPF_ST means::
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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*(size *) (dst_reg + off) = imm32
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BPF_MEM | <size> | BPF_LDX means::
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dst_reg = *(size *) (src_reg + off)
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Where size is one of: BPF_B or BPF_H or BPF_W or BPF_DW.
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Atomic operations
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-----------------
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2021-11-20 00:32:15 +08:00
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2021-12-23 18:19:05 +08:00
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eBPF includes atomic operations, which use the immediate field for extra
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encoding::
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.imm = BPF_ADD, .code = BPF_ATOMIC | BPF_W | BPF_STX: lock xadd *(u32 *)(dst_reg + off16) += src_reg
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.imm = BPF_ADD, .code = BPF_ATOMIC | BPF_DW | BPF_STX: lock xadd *(u64 *)(dst_reg + off16) += src_reg
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The basic atomic operations supported are::
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BPF_ADD
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BPF_AND
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BPF_OR
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BPF_XOR
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Each having equivalent semantics with the ``BPF_ADD`` example, that is: the
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memory location addresed by ``dst_reg + off`` is atomically modified, with
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``src_reg`` as the other operand. If the ``BPF_FETCH`` flag is set in the
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immediate, then these operations also overwrite ``src_reg`` with the
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value that was in memory before it was modified.
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The more special operations are::
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BPF_XCHG
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This atomically exchanges ``src_reg`` with the value addressed by ``dst_reg +
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off``. ::
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BPF_CMPXCHG
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This atomically compares the value addressed by ``dst_reg + off`` with
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``R0``. If they match it is replaced with ``src_reg``. In either case, the
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value that was there before is zero-extended and loaded back to ``R0``.
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Note that 1 and 2 byte atomic operations are not supported.
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Clang can generate atomic instructions by default when ``-mcpu=v3`` is
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enabled. If a lower version for ``-mcpu`` is set, the only atomic instruction
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Clang can generate is ``BPF_ADD`` *without* ``BPF_FETCH``. If you need to enable
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the atomics features, while keeping a lower ``-mcpu`` version, you can use
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``-Xclang -target-feature -Xclang +alu32``.
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You may encounter ``BPF_XADD`` - this is a legacy name for ``BPF_ATOMIC``,
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referring to the exclusive-add operation encoded when the immediate field is
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zero.
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2021-12-23 18:19:05 +08:00
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16-byte instructions
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--------------------
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2021-11-20 00:32:15 +08:00
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eBPF has one 16-byte instruction: ``BPF_LD | BPF_DW | BPF_IMM`` which consists
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of two consecutive ``struct bpf_insn`` 8-byte blocks and interpreted as single
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instruction that loads 64-bit immediate value into a dst_reg.
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2021-12-23 18:19:06 +08:00
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Packet access instructions
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--------------------------
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eBPF has two non-generic instructions: (BPF_ABS | <size> | BPF_LD) and
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(BPF_IND | <size> | BPF_LD) which are used to access packet data.
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They had to be carried over from classic BPF to have strong performance of
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socket filters running in eBPF interpreter. These instructions can only
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be used when interpreter context is a pointer to ``struct sk_buff`` and
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have seven implicit operands. Register R6 is an implicit input that must
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contain pointer to sk_buff. Register R0 is an implicit output which contains
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the data fetched from the packet. Registers R1-R5 are scratch registers
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and must not be used to store the data across BPF_ABS | BPF_LD or
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BPF_IND | BPF_LD instructions.
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These instructions have implicit program exit condition as well. When
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eBPF program is trying to access the data beyond the packet boundary,
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the interpreter will abort the execution of the program. JIT compilers
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therefore must preserve this property. src_reg and imm32 fields are
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explicit inputs to these instructions.
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For example, BPF_IND | BPF_W | BPF_LD means::
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R0 = ntohl(*(u32 *) (((struct sk_buff *) R6)->data + src_reg + imm32))
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and R1 - R5 are clobbered.
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