2009-04-08 07:16:42 +08:00
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/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <linux/i2c.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2011-08-31 06:16:33 +08:00
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#include <linux/export.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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2009-04-08 07:16:42 +08:00
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#include "intel_drv.h"
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2012-10-03 01:01:07 +08:00
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#include <drm/i915_drm.h>
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2009-04-08 07:16:42 +08:00
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#include "i915_drv.h"
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#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
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2010-10-08 07:01:06 +08:00
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/**
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* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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* @intel_dp: DP struct
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*
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* If a CPU or PCH DP output is attached to an eDP panel, this function
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* will return true, and false otherwise.
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*/
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static bool is_edp(struct intel_dp *intel_dp)
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{
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2012-10-27 05:05:46 +08:00
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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2010-10-08 07:01:06 +08:00
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}
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2013-05-08 18:14:06 +08:00
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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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return intel_dig_port->base.base.dev;
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}
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2010-09-09 23:20:55 +08:00
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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
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{
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2012-10-27 05:05:44 +08:00
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return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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2010-09-09 23:20:55 +08:00
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}
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2010-08-04 20:50:23 +08:00
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static void intel_dp_link_down(struct intel_dp *intel_dp);
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2009-04-08 07:16:42 +08:00
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static int
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2010-08-04 20:50:23 +08:00
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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2009-04-08 07:16:42 +08:00
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{
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2011-07-08 02:10:58 +08:00
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int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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2009-04-08 07:16:42 +08:00
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switch (max_link_bw) {
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case DP_LINK_BW_1_62:
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case DP_LINK_BW_2_7:
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break;
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default:
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max_link_bw = DP_LINK_BW_1_62;
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break;
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}
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return max_link_bw;
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}
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2011-10-15 00:43:49 +08:00
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/*
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* The units on the numbers in the next two are... bizarre. Examples will
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* make it clearer; this one parallels an example in the eDP spec.
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*
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* intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
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*
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* 270000 * 1 * 8 / 10 == 216000
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*
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* The actual data capacity of that configuration is 2.16Gbit/s, so the
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* units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
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* or equivalently, kilopixels per second - so for 1680x1050R it'd be
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* 119000. At 18bpp that's 2142000 kilobits per second.
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*
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* Thus the strange-looking division by 10 in intel_dp_link_required, to
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* get the result in decakilobits instead of kilobits.
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*/
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2009-04-08 07:16:42 +08:00
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static int
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2012-01-26 00:16:25 +08:00
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intel_dp_link_required(int pixel_clock, int bpp)
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2009-04-08 07:16:42 +08:00
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{
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2011-10-15 00:43:49 +08:00
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return (pixel_clock * bpp + 9) / 10;
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2009-04-08 07:16:42 +08:00
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}
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2010-06-30 09:46:17 +08:00
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static int
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intel_dp_max_data_rate(int max_link_clock, int max_lanes)
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{
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return (max_link_clock * max_lanes * 8) / 10;
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}
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2009-04-08 07:16:42 +08:00
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static int
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intel_dp_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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2010-09-09 23:20:55 +08:00
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struct intel_dp *intel_dp = intel_attached_dp(connector);
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2012-10-19 19:51:50 +08:00
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struct intel_connector *intel_connector = to_intel_connector(connector);
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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2013-03-27 07:44:59 +08:00
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int target_clock = mode->clock;
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int max_rate, mode_rate, max_lanes, max_link_clock;
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2009-04-08 07:16:42 +08:00
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2012-10-19 19:51:50 +08:00
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if (is_edp(intel_dp) && fixed_mode) {
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if (mode->hdisplay > fixed_mode->hdisplay)
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2010-07-19 16:43:14 +08:00
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return MODE_PANEL;
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2012-10-19 19:51:50 +08:00
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if (mode->vdisplay > fixed_mode->vdisplay)
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2010-07-19 16:43:14 +08:00
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return MODE_PANEL;
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2013-04-03 05:42:31 +08:00
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target_clock = fixed_mode->clock;
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2010-07-19 16:43:14 +08:00
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}
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2013-03-27 07:44:59 +08:00
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max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
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max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
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mode_rate = intel_dp_link_required(target_clock, 18);
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if (mode_rate > max_rate)
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2012-04-10 16:42:36 +08:00
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return MODE_CLOCK_HIGH;
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2009-04-08 07:16:42 +08:00
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if (mode->clock < 10000)
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return MODE_CLOCK_LOW;
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2012-05-23 17:30:55 +08:00
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if (mode->flags & DRM_MODE_FLAG_DBLCLK)
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return MODE_H_ILLEGAL;
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2009-04-08 07:16:42 +08:00
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return MODE_OK;
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}
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static uint32_t
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pack_aux(uint8_t *src, int src_bytes)
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{
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int i;
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uint32_t v = 0;
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if (src_bytes > 4)
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src_bytes = 4;
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for (i = 0; i < src_bytes; i++)
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v |= ((uint32_t) src[i]) << ((3-i) * 8);
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return v;
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}
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static void
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unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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{
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int i;
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if (dst_bytes > 4)
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dst_bytes = 4;
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for (i = 0; i < dst_bytes; i++)
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dst[i] = src >> ((3-i) * 8);
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}
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2009-06-12 13:31:31 +08:00
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/* hrawclock is 1/4 the FSB frequency */
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static int
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intel_hrawclk(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t clkcfg;
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2012-09-27 21:43:01 +08:00
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/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
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if (IS_VALLEYVIEW(dev))
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return 200;
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2009-06-12 13:31:31 +08:00
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clkcfg = I915_READ(CLKCFG);
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switch (clkcfg & CLKCFG_FSB_MASK) {
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case CLKCFG_FSB_400:
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return 100;
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case CLKCFG_FSB_533:
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return 133;
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case CLKCFG_FSB_667:
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return 166;
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case CLKCFG_FSB_800:
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return 200;
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case CLKCFG_FSB_1067:
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return 266;
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case CLKCFG_FSB_1333:
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return 333;
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/* these two are just a guess; one of them might be right */
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case CLKCFG_FSB_1600:
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case CLKCFG_FSB_1600_ALT:
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return 400;
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default:
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return 133;
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}
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}
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2011-09-30 06:53:27 +08:00
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static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
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{
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2012-10-27 05:05:45 +08:00
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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2011-09-30 06:53:27 +08:00
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struct drm_i915_private *dev_priv = dev->dev_private;
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2013-03-29 00:55:41 +08:00
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u32 pp_stat_reg;
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2011-09-30 06:53:27 +08:00
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2013-03-29 00:55:41 +08:00
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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return (I915_READ(pp_stat_reg) & PP_ON) != 0;
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2011-09-30 06:53:27 +08:00
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}
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static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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2012-10-27 05:05:45 +08:00
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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2011-09-30 06:53:27 +08:00
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struct drm_i915_private *dev_priv = dev->dev_private;
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2013-03-29 00:55:41 +08:00
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u32 pp_ctrl_reg;
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2011-09-30 06:53:27 +08:00
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2013-03-29 00:55:41 +08:00
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
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2011-09-30 06:53:27 +08:00
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}
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2011-09-20 04:54:47 +08:00
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static void
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intel_dp_check_edp(struct intel_dp *intel_dp)
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{
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2012-10-27 05:05:45 +08:00
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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2011-09-20 04:54:47 +08:00
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struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-29 00:55:41 +08:00
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u32 pp_stat_reg, pp_ctrl_reg;
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2011-09-30 06:53:27 +08:00
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2011-09-20 04:54:47 +08:00
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if (!is_edp(intel_dp))
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return;
|
2013-03-29 00:55:41 +08:00
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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2011-09-30 06:53:27 +08:00
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if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
|
2011-09-20 04:54:47 +08:00
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|
|
WARN(1, "eDP powered off while attempting aux channel communication.\n");
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|
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DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
|
2013-03-29 00:55:41 +08:00
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|
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I915_READ(pp_stat_reg),
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|
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I915_READ(pp_ctrl_reg));
|
2011-09-20 04:54:47 +08:00
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}
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}
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|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
static uint32_t
|
|
|
|
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-19 06:00:25 +08:00
|
|
|
uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
uint32_t status;
|
|
|
|
bool done;
|
|
|
|
|
2012-12-02 04:03:59 +08:00
|
|
|
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
if (has_aux_irq)
|
2013-02-19 06:00:24 +08:00
|
|
|
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
|
|
|
|
msecs_to_jiffies(10));
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
else
|
|
|
|
done = wait_for_atomic(C, 10) == 0;
|
|
|
|
if (!done)
|
|
|
|
DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
|
|
|
|
has_aux_irq);
|
|
|
|
#undef C
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static int
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_aux_ch(struct intel_dp *intel_dp,
|
2009-04-08 07:16:42 +08:00
|
|
|
uint8_t *send, int send_bytes,
|
|
|
|
uint8_t *recv, int recv_size)
|
|
|
|
{
|
2012-10-27 05:05:50 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-19 06:00:25 +08:00
|
|
|
uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
|
2009-04-08 07:16:42 +08:00
|
|
|
uint32_t ch_data = ch_ctl + 4;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
int i, ret, recv_bytes;
|
2009-04-08 07:16:42 +08:00
|
|
|
uint32_t status;
|
2009-06-12 13:31:31 +08:00
|
|
|
uint32_t aux_clock_divider;
|
2012-06-15 04:15:00 +08:00
|
|
|
int try, precharge;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
|
|
|
|
|
|
|
|
/* dp aux is extremely sensitive to irq latency, hence request the
|
|
|
|
* lowest possible wakeup latency and so prevent the cpu from going into
|
|
|
|
* deep sleep states.
|
|
|
|
*/
|
|
|
|
pm_qos_update_request(&dev_priv->pm_qos, 0);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-09-20 04:54:47 +08:00
|
|
|
intel_dp_check_edp(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
/* The clock divider is based off the hrawclk,
|
2009-06-12 13:31:31 +08:00
|
|
|
* and would like to run at 2MHz. So, take the
|
|
|
|
* hrawclk value and divide by 2 and use that
|
2010-09-09 03:42:00 +08:00
|
|
|
*
|
|
|
|
* Note that PCH attached eDP panels should use a 125MHz input
|
|
|
|
* clock divider.
|
2009-04-08 07:16:42 +08:00
|
|
|
*/
|
2013-05-16 19:40:35 +08:00
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
aux_clock_divider = 100;
|
|
|
|
} else if (intel_dig_port->port == PORT_A) {
|
2012-11-24 01:30:39 +08:00
|
|
|
if (HAS_DDI(dev))
|
2013-05-04 04:23:42 +08:00
|
|
|
aux_clock_divider = DIV_ROUND_CLOSEST(
|
|
|
|
intel_ddi_get_cdclk_freq(dev_priv), 2000);
|
2012-09-27 21:43:01 +08:00
|
|
|
else if (IS_GEN6(dev) || IS_GEN7(dev))
|
2011-11-17 08:26:07 +08:00
|
|
|
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
|
2010-04-08 09:43:27 +08:00
|
|
|
else
|
|
|
|
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
|
2013-04-09 13:11:00 +08:00
|
|
|
} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
|
|
|
|
/* Workaround for non-ULT HSW */
|
|
|
|
aux_clock_divider = 74;
|
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
2012-10-21 02:57:44 +08:00
|
|
|
aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
|
2013-04-09 13:11:00 +08:00
|
|
|
} else {
|
2009-07-24 01:00:31 +08:00
|
|
|
aux_clock_divider = intel_hrawclk(dev) / 2;
|
2013-04-09 13:11:00 +08:00
|
|
|
}
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2012-06-15 04:15:00 +08:00
|
|
|
if (IS_GEN6(dev))
|
|
|
|
precharge = 3;
|
|
|
|
else
|
|
|
|
precharge = 5;
|
|
|
|
|
2011-08-02 06:02:20 +08:00
|
|
|
/* Try to wait for any previous AUX channel activity */
|
|
|
|
for (try = 0; try < 3; try++) {
|
2012-12-02 04:03:59 +08:00
|
|
|
status = I915_READ_NOTRACE(ch_ctl);
|
2011-08-02 06:02:20 +08:00
|
|
|
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
|
|
|
break;
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (try == 3) {
|
|
|
|
WARN(1, "dp_aux_ch not started status 0x%08x\n",
|
|
|
|
I915_READ(ch_ctl));
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -EBUSY;
|
|
|
|
goto out;
|
2010-08-19 01:12:56 +08:00
|
|
|
}
|
|
|
|
|
2009-06-12 13:31:31 +08:00
|
|
|
/* Must try at least 3 times according to DP spec */
|
|
|
|
for (try = 0; try < 5; try++) {
|
|
|
|
/* Load the send data into the aux channel data registers */
|
2010-08-19 01:12:56 +08:00
|
|
|
for (i = 0; i < send_bytes; i += 4)
|
|
|
|
I915_WRITE(ch_data + i,
|
|
|
|
pack_aux(send + i, send_bytes - i));
|
2011-08-17 03:34:10 +08:00
|
|
|
|
2009-06-12 13:31:31 +08:00
|
|
|
/* Send the command and wait for it to complete */
|
2010-08-19 01:12:56 +08:00
|
|
|
I915_WRITE(ch_ctl,
|
|
|
|
DP_AUX_CH_CTL_SEND_BUSY |
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
|
2010-08-19 01:12:56 +08:00
|
|
|
DP_AUX_CH_CTL_TIME_OUT_400us |
|
|
|
|
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
|
|
|
(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
|
|
|
|
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
|
|
|
|
DP_AUX_CH_CTL_DONE |
|
|
|
|
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
|
|
|
DP_AUX_CH_CTL_RECEIVE_ERROR);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
|
|
|
|
status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
|
2011-08-17 03:34:10 +08:00
|
|
|
|
2009-06-12 13:31:31 +08:00
|
|
|
/* Clear done status and any errors */
|
2010-08-19 01:12:56 +08:00
|
|
|
I915_WRITE(ch_ctl,
|
|
|
|
status |
|
|
|
|
DP_AUX_CH_CTL_DONE |
|
|
|
|
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
|
|
|
DP_AUX_CH_CTL_RECEIVE_ERROR);
|
2011-07-27 03:39:46 +08:00
|
|
|
|
|
|
|
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
|
|
|
DP_AUX_CH_CTL_RECEIVE_ERROR))
|
|
|
|
continue;
|
2010-08-19 01:12:56 +08:00
|
|
|
if (status & DP_AUX_CH_CTL_DONE)
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((status & DP_AUX_CH_CTL_DONE) == 0) {
|
2009-06-29 06:42:17 +08:00
|
|
|
DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -EBUSY;
|
|
|
|
goto out;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for timeout or receive error.
|
|
|
|
* Timeouts occur when the sink is not connected
|
|
|
|
*/
|
2009-06-12 13:30:32 +08:00
|
|
|
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
|
2009-06-29 06:42:17 +08:00
|
|
|
DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -EIO;
|
|
|
|
goto out;
|
2009-06-12 13:30:32 +08:00
|
|
|
}
|
2009-06-29 06:42:17 +08:00
|
|
|
|
|
|
|
/* Timeouts occur when the device isn't connected, so they're
|
|
|
|
* "normal" -- don't fill the kernel log with these */
|
2009-06-12 13:30:32 +08:00
|
|
|
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto out;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Unload any bytes sent back from the other side */
|
|
|
|
recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
|
|
|
|
DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
|
|
|
|
if (recv_bytes > recv_size)
|
|
|
|
recv_bytes = recv_size;
|
2011-08-17 03:34:10 +08:00
|
|
|
|
2010-08-19 01:12:56 +08:00
|
|
|
for (i = 0; i < recv_bytes; i += 4)
|
|
|
|
unpack_aux(I915_READ(ch_data + i),
|
|
|
|
recv + i, recv_bytes - i);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = recv_bytes;
|
|
|
|
out:
|
|
|
|
pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
|
|
|
|
|
|
|
|
return ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write data to the aux channel in native mode */
|
|
|
|
static int
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_aux_native_write(struct intel_dp *intel_dp,
|
2009-04-08 07:16:42 +08:00
|
|
|
uint16_t address, uint8_t *send, int send_bytes)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
uint8_t msg[20];
|
|
|
|
int msg_bytes;
|
|
|
|
uint8_t ack;
|
|
|
|
|
2011-09-20 04:54:47 +08:00
|
|
|
intel_dp_check_edp(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
if (send_bytes > 16)
|
|
|
|
return -1;
|
|
|
|
msg[0] = AUX_NATIVE_WRITE << 4;
|
|
|
|
msg[1] = address >> 8;
|
2009-07-24 01:00:30 +08:00
|
|
|
msg[2] = address & 0xff;
|
2009-04-08 07:16:42 +08:00
|
|
|
msg[3] = send_bytes - 1;
|
|
|
|
memcpy(&msg[4], send, send_bytes);
|
|
|
|
msg_bytes = send_bytes + 4;
|
|
|
|
for (;;) {
|
2010-08-04 20:50:23 +08:00
|
|
|
ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
|
2009-04-08 07:16:42 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
|
|
|
break;
|
|
|
|
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
|
|
|
|
udelay(100);
|
|
|
|
else
|
2009-06-12 13:30:32 +08:00
|
|
|
return -EIO;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
return send_bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write a single byte to the aux channel in native mode */
|
|
|
|
static int
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
|
2009-04-08 07:16:42 +08:00
|
|
|
uint16_t address, uint8_t byte)
|
|
|
|
{
|
2010-08-04 20:50:23 +08:00
|
|
|
return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* read bytes from a native aux channel */
|
|
|
|
static int
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_aux_native_read(struct intel_dp *intel_dp,
|
2009-04-08 07:16:42 +08:00
|
|
|
uint16_t address, uint8_t *recv, int recv_bytes)
|
|
|
|
{
|
|
|
|
uint8_t msg[4];
|
|
|
|
int msg_bytes;
|
|
|
|
uint8_t reply[20];
|
|
|
|
int reply_bytes;
|
|
|
|
uint8_t ack;
|
|
|
|
int ret;
|
|
|
|
|
2011-09-20 04:54:47 +08:00
|
|
|
intel_dp_check_edp(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
msg[0] = AUX_NATIVE_READ << 4;
|
|
|
|
msg[1] = address >> 8;
|
|
|
|
msg[2] = address & 0xff;
|
|
|
|
msg[3] = recv_bytes - 1;
|
|
|
|
|
|
|
|
msg_bytes = 4;
|
|
|
|
reply_bytes = recv_bytes + 1;
|
|
|
|
|
|
|
|
for (;;) {
|
2010-08-04 20:50:23 +08:00
|
|
|
ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
|
2009-04-08 07:16:42 +08:00
|
|
|
reply, reply_bytes);
|
2009-06-12 13:30:32 +08:00
|
|
|
if (ret == 0)
|
|
|
|
return -EPROTO;
|
|
|
|
if (ret < 0)
|
2009-04-08 07:16:42 +08:00
|
|
|
return ret;
|
|
|
|
ack = reply[0];
|
|
|
|
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
|
|
|
|
memcpy(recv, reply + 1, ret - 1);
|
|
|
|
return ret - 1;
|
|
|
|
}
|
|
|
|
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
|
|
|
|
udelay(100);
|
|
|
|
else
|
2009-06-12 13:30:32 +08:00
|
|
|
return -EIO;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2009-12-04 08:55:24 +08:00
|
|
|
intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
|
|
|
|
uint8_t write_byte, uint8_t *read_byte)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2009-12-04 08:55:24 +08:00
|
|
|
struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
|
2010-08-04 20:50:23 +08:00
|
|
|
struct intel_dp *intel_dp = container_of(adapter,
|
|
|
|
struct intel_dp,
|
|
|
|
adapter);
|
2009-12-04 08:55:24 +08:00
|
|
|
uint16_t address = algo_data->address;
|
|
|
|
uint8_t msg[5];
|
|
|
|
uint8_t reply[2];
|
2010-12-09 00:10:21 +08:00
|
|
|
unsigned retry;
|
2009-12-04 08:55:24 +08:00
|
|
|
int msg_bytes;
|
|
|
|
int reply_bytes;
|
|
|
|
int ret;
|
|
|
|
|
2011-09-20 04:54:47 +08:00
|
|
|
intel_dp_check_edp(intel_dp);
|
2009-12-04 08:55:24 +08:00
|
|
|
/* Set up the command byte */
|
|
|
|
if (mode & MODE_I2C_READ)
|
|
|
|
msg[0] = AUX_I2C_READ << 4;
|
|
|
|
else
|
|
|
|
msg[0] = AUX_I2C_WRITE << 4;
|
|
|
|
|
|
|
|
if (!(mode & MODE_I2C_STOP))
|
|
|
|
msg[0] |= AUX_I2C_MOT << 4;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2009-12-04 08:55:24 +08:00
|
|
|
msg[1] = address >> 8;
|
|
|
|
msg[2] = address;
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case MODE_I2C_WRITE:
|
|
|
|
msg[3] = 0;
|
|
|
|
msg[4] = write_byte;
|
|
|
|
msg_bytes = 5;
|
|
|
|
reply_bytes = 1;
|
|
|
|
break;
|
|
|
|
case MODE_I2C_READ:
|
|
|
|
msg[3] = 0;
|
|
|
|
msg_bytes = 4;
|
|
|
|
reply_bytes = 2;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
msg_bytes = 3;
|
|
|
|
reply_bytes = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-12-09 00:10:21 +08:00
|
|
|
for (retry = 0; retry < 5; retry++) {
|
|
|
|
ret = intel_dp_aux_ch(intel_dp,
|
|
|
|
msg, msg_bytes,
|
|
|
|
reply, reply_bytes);
|
2009-12-04 08:55:24 +08:00
|
|
|
if (ret < 0) {
|
2009-12-08 12:03:47 +08:00
|
|
|
DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
|
2009-12-04 08:55:24 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2010-12-09 00:10:21 +08:00
|
|
|
|
|
|
|
switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
|
|
|
|
case AUX_NATIVE_REPLY_ACK:
|
|
|
|
/* I2C-over-AUX Reply field is only valid
|
|
|
|
* when paired with AUX ACK.
|
|
|
|
*/
|
|
|
|
break;
|
|
|
|
case AUX_NATIVE_REPLY_NACK:
|
|
|
|
DRM_DEBUG_KMS("aux_ch native nack\n");
|
|
|
|
return -EREMOTEIO;
|
|
|
|
case AUX_NATIVE_REPLY_DEFER:
|
|
|
|
udelay(100);
|
|
|
|
continue;
|
|
|
|
default:
|
|
|
|
DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
|
|
|
|
reply[0]);
|
|
|
|
return -EREMOTEIO;
|
|
|
|
}
|
|
|
|
|
2009-12-04 08:55:24 +08:00
|
|
|
switch (reply[0] & AUX_I2C_REPLY_MASK) {
|
|
|
|
case AUX_I2C_REPLY_ACK:
|
|
|
|
if (mode == MODE_I2C_READ) {
|
|
|
|
*read_byte = reply[1];
|
|
|
|
}
|
|
|
|
return reply_bytes - 1;
|
|
|
|
case AUX_I2C_REPLY_NACK:
|
2010-12-09 00:10:21 +08:00
|
|
|
DRM_DEBUG_KMS("aux_i2c nack\n");
|
2009-12-04 08:55:24 +08:00
|
|
|
return -EREMOTEIO;
|
|
|
|
case AUX_I2C_REPLY_DEFER:
|
2010-12-09 00:10:21 +08:00
|
|
|
DRM_DEBUG_KMS("aux_i2c defer\n");
|
2009-12-04 08:55:24 +08:00
|
|
|
udelay(100);
|
|
|
|
break;
|
|
|
|
default:
|
2010-12-09 00:10:21 +08:00
|
|
|
DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
|
2009-12-04 08:55:24 +08:00
|
|
|
return -EREMOTEIO;
|
|
|
|
}
|
|
|
|
}
|
2010-12-09 00:10:21 +08:00
|
|
|
|
|
|
|
DRM_ERROR("too many retries, giving up\n");
|
|
|
|
return -EREMOTEIO;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_i2c_init(struct intel_dp *intel_dp,
|
2010-03-29 16:13:57 +08:00
|
|
|
struct intel_connector *intel_connector, const char *name)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2011-09-29 07:41:05 +08:00
|
|
|
int ret;
|
|
|
|
|
2009-10-19 15:43:51 +08:00
|
|
|
DRM_DEBUG_KMS("i2c_init %s\n", name);
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp->algo.running = false;
|
|
|
|
intel_dp->algo.address = 0;
|
|
|
|
intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
|
|
|
|
|
2011-08-17 03:34:10 +08:00
|
|
|
memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp->adapter.owner = THIS_MODULE;
|
|
|
|
intel_dp->adapter.class = I2C_CLASS_DDC;
|
2011-08-17 03:34:10 +08:00
|
|
|
strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
|
|
|
|
intel_dp->adapter.algo_data = &intel_dp->algo;
|
|
|
|
intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
|
|
|
|
|
2011-09-29 07:41:05 +08:00
|
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
|
|
|
ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
|
2011-09-19 14:09:52 +08:00
|
|
|
ironlake_edp_panel_vdd_off(intel_dp, false);
|
2011-09-29 07:41:05 +08:00
|
|
|
return ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2013-04-19 17:14:33 +08:00
|
|
|
static void
|
|
|
|
intel_dp_set_clock(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config, int link_bw)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
|
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
if (link_bw == DP_LINK_BW_1_62) {
|
|
|
|
pipe_config->dpll.p1 = 2;
|
|
|
|
pipe_config->dpll.p2 = 10;
|
|
|
|
pipe_config->dpll.n = 2;
|
|
|
|
pipe_config->dpll.m1 = 23;
|
|
|
|
pipe_config->dpll.m2 = 8;
|
|
|
|
} else {
|
|
|
|
pipe_config->dpll.p1 = 1;
|
|
|
|
pipe_config->dpll.p2 = 10;
|
|
|
|
pipe_config->dpll.n = 1;
|
|
|
|
pipe_config->dpll.m1 = 14;
|
|
|
|
pipe_config->dpll.m2 = 2;
|
|
|
|
}
|
|
|
|
pipe_config->clock_set = true;
|
|
|
|
} else if (IS_HASWELL(dev)) {
|
|
|
|
/* Haswell has special-purpose DP DDI clocks. */
|
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
if (link_bw == DP_LINK_BW_1_62) {
|
|
|
|
pipe_config->dpll.n = 1;
|
|
|
|
pipe_config->dpll.p1 = 2;
|
|
|
|
pipe_config->dpll.p2 = 10;
|
|
|
|
pipe_config->dpll.m1 = 12;
|
|
|
|
pipe_config->dpll.m2 = 9;
|
|
|
|
} else {
|
|
|
|
pipe_config->dpll.n = 2;
|
|
|
|
pipe_config->dpll.p1 = 1;
|
|
|
|
pipe_config->dpll.p2 = 10;
|
|
|
|
pipe_config->dpll.m1 = 14;
|
|
|
|
pipe_config->dpll.m2 = 8;
|
|
|
|
}
|
|
|
|
pipe_config->clock_set = true;
|
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
|
|
/* FIXME: Need to figure out optimized DP clocks for vlv. */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
bool
|
2013-03-27 07:44:55 +08:00
|
|
|
intel_dp_compute_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2013-03-27 07:44:55 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2013-03-27 07:44:59 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 07:44:55 +08:00
|
|
|
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2013-04-26 03:55:01 +08:00
|
|
|
struct intel_crtc *intel_crtc = encoder->new_crtc;
|
2012-10-19 19:51:50 +08:00
|
|
|
struct intel_connector *intel_connector = intel_dp->attached_connector;
|
2009-04-08 07:16:42 +08:00
|
|
|
int lane_count, clock;
|
2012-10-23 04:56:43 +08:00
|
|
|
int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
|
2010-08-04 20:50:23 +08:00
|
|
|
int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
|
2012-04-21 02:23:49 +08:00
|
|
|
int bpp, mode_rate;
|
2009-04-08 07:16:42 +08:00
|
|
|
static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
|
2013-06-01 23:16:21 +08:00
|
|
|
int link_avail, link_clock;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
|
2013-03-27 07:44:55 +08:00
|
|
|
pipe_config->has_pch_encoder = true;
|
|
|
|
|
2013-04-03 05:42:31 +08:00
|
|
|
pipe_config->has_dp_encoder = true;
|
|
|
|
|
2012-10-19 19:51:50 +08:00
|
|
|
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
|
|
|
|
intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
|
|
|
|
adjusted_mode);
|
2013-04-26 03:55:01 +08:00
|
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
|
|
intel_gmch_panel_fitting(intel_crtc, pipe_config,
|
|
|
|
intel_connector->panel.fitting_mode);
|
|
|
|
else
|
2013-04-26 03:55:02 +08:00
|
|
|
intel_pch_panel_fitting(intel_crtc, pipe_config,
|
|
|
|
intel_connector->panel.fitting_mode);
|
2010-07-19 16:43:13 +08:00
|
|
|
}
|
|
|
|
|
2012-06-05 00:39:21 +08:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
|
2012-05-23 17:30:55 +08:00
|
|
|
return false;
|
|
|
|
|
2012-04-21 02:23:49 +08:00
|
|
|
DRM_DEBUG_KMS("DP link computation with max lane count %i "
|
|
|
|
"max bw %02x pixel clock %iKHz\n",
|
2012-06-05 00:39:20 +08:00
|
|
|
max_lane_count, bws[max_clock], adjusted_mode->clock);
|
2012-04-21 02:23:49 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
|
|
|
|
* bpc in between. */
|
2013-06-02 01:45:56 +08:00
|
|
|
bpp = pipe_config->pipe_bpp;
|
2013-05-21 15:52:16 +08:00
|
|
|
if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
|
|
|
|
bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
|
2013-02-20 00:45:00 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
for (; bpp >= 6*3; bpp -= 2*3) {
|
2013-06-01 23:16:21 +08:00
|
|
|
mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
|
2013-03-27 07:44:59 +08:00
|
|
|
|
|
|
|
for (clock = 0; clock <= max_clock; clock++) {
|
|
|
|
for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
|
|
|
|
link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
|
|
|
|
link_avail = intel_dp_max_data_rate(link_clock,
|
|
|
|
lane_count);
|
|
|
|
|
|
|
|
if (mode_rate <= link_avail) {
|
|
|
|
goto found;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-04-10 16:42:36 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
return false;
|
2013-01-17 22:31:28 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
found:
|
2013-01-17 22:31:29 +08:00
|
|
|
if (intel_dp->color_range_auto) {
|
|
|
|
/*
|
|
|
|
* See:
|
|
|
|
* CEA-861-E - 5.1 Default Encoding Parameters
|
|
|
|
* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
|
|
|
|
*/
|
2012-12-20 22:41:44 +08:00
|
|
|
if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
|
2013-01-17 22:31:29 +08:00
|
|
|
intel_dp->color_range = DP_COLOR_RANGE_16_235;
|
|
|
|
else
|
|
|
|
intel_dp->color_range = 0;
|
|
|
|
}
|
|
|
|
|
2013-01-17 22:31:28 +08:00
|
|
|
if (intel_dp->color_range)
|
2013-03-27 07:44:56 +08:00
|
|
|
pipe_config->limited_color_range = true;
|
2013-01-17 22:31:28 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
intel_dp->link_bw = bws[clock];
|
|
|
|
intel_dp->lane_count = lane_count;
|
2013-05-04 16:09:18 +08:00
|
|
|
pipe_config->pipe_bpp = bpp;
|
2013-06-01 23:16:21 +08:00
|
|
|
pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
|
2010-06-30 09:46:17 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
|
|
|
|
intel_dp->link_bw, intel_dp->lane_count,
|
2013-06-01 23:16:21 +08:00
|
|
|
pipe_config->port_clock, bpp);
|
2013-03-27 07:44:59 +08:00
|
|
|
DRM_DEBUG_KMS("DP link bw required %i available %i\n",
|
|
|
|
mode_rate, link_avail);
|
|
|
|
|
2013-04-03 05:42:31 +08:00
|
|
|
intel_link_compute_m_n(bpp, lane_count,
|
2013-06-01 23:16:21 +08:00
|
|
|
adjusted_mode->clock, pipe_config->port_clock,
|
2013-04-03 05:42:31 +08:00
|
|
|
&pipe_config->dp_m_n);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-04-19 17:14:33 +08:00
|
|
|
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
|
|
|
|
|
2013-04-03 05:42:31 +08:00
|
|
|
return true;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:33 +08:00
|
|
|
void intel_dp_init_link_config(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
|
|
|
|
intel_dp->link_configuration[0] = intel_dp->link_bw;
|
|
|
|
intel_dp->link_configuration[1] = intel_dp->lane_count;
|
|
|
|
intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
|
|
|
|
/*
|
|
|
|
* Check for DPCD version > 1.1 and enhanced framing support
|
|
|
|
*/
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
|
|
|
|
(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
|
|
|
|
intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-01 23:16:20 +08:00
|
|
|
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
|
2012-11-29 22:59:31 +08:00
|
|
|
{
|
2013-06-01 23:16:20 +08:00
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
|
|
|
|
struct drm_device *dev = crtc->base.dev;
|
2012-11-29 22:59:31 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 dpa_ctl;
|
|
|
|
|
2013-06-01 23:16:21 +08:00
|
|
|
DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
|
2012-11-29 22:59:31 +08:00
|
|
|
dpa_ctl = I915_READ(DP_A);
|
|
|
|
dpa_ctl &= ~DP_PLL_FREQ_MASK;
|
|
|
|
|
2013-06-01 23:16:21 +08:00
|
|
|
if (crtc->config.port_clock == 162000) {
|
2012-11-29 22:59:32 +08:00
|
|
|
/* For a long time we've carried around a ILK-DevA w/a for the
|
|
|
|
* 160MHz clock. If we're really unlucky, it's still required.
|
|
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
|
2012-11-29 22:59:31 +08:00
|
|
|
dpa_ctl |= DP_PLL_FREQ_160MHZ;
|
2013-06-01 23:16:20 +08:00
|
|
|
intel_dp->DP |= DP_PLL_FREQ_160MHZ;
|
2012-11-29 22:59:31 +08:00
|
|
|
} else {
|
|
|
|
dpa_ctl |= DP_PLL_FREQ_270MHZ;
|
2013-06-01 23:16:20 +08:00
|
|
|
intel_dp->DP |= DP_PLL_FREQ_270MHZ;
|
2012-11-29 22:59:31 +08:00
|
|
|
}
|
2012-11-29 22:59:32 +08:00
|
|
|
|
2012-11-29 22:59:31 +08:00
|
|
|
I915_WRITE(DP_A, dpa_ctl);
|
|
|
|
|
|
|
|
POSTING_READ(DP_A);
|
|
|
|
udelay(500);
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static void
|
|
|
|
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
2010-04-08 09:43:27 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2011-11-02 10:54:11 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-08-04 20:50:23 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2013-06-01 23:16:20 +08:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/*
|
2011-11-17 08:26:07 +08:00
|
|
|
* There are four kinds of DP registers:
|
2011-11-02 10:54:11 +08:00
|
|
|
*
|
|
|
|
* IBX PCH
|
2011-11-17 08:26:07 +08:00
|
|
|
* SNB CPU
|
|
|
|
* IVB CPU
|
2011-11-02 10:54:11 +08:00
|
|
|
* CPT PCH
|
|
|
|
*
|
|
|
|
* IBX PCH and CPU are the same for almost everything,
|
|
|
|
* except that the CPU DP PLL is configured in this
|
|
|
|
* register
|
|
|
|
*
|
|
|
|
* CPT PCH is quite different, having many bits moved
|
|
|
|
* to the TRANS_DP_CTL register instead. That
|
|
|
|
* configuration happens (oddly) in ironlake_pch_enable
|
|
|
|
*/
|
2010-04-06 05:57:59 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/* Preserve the BIOS-computed detected bit. This is
|
|
|
|
* supposed to be read-only.
|
|
|
|
*/
|
|
|
|
intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/* Handle DP bits in common between all three register formats */
|
|
|
|
intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
|
2013-04-30 20:01:40 +08:00
|
|
|
intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-05 14:25:34 +08:00
|
|
|
if (intel_dp->has_audio) {
|
|
|
|
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
|
2013-06-01 23:16:20 +08:00
|
|
|
pipe_name(crtc->pipe));
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
|
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-05 14:25:34 +08:00
|
|
|
intel_write_eld(encoder, adjusted_mode);
|
|
|
|
}
|
2012-10-16 02:51:33 +08:00
|
|
|
|
|
|
|
intel_dp_init_link_config(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/* Split out the IBX/CPU vs CPT settings */
|
2009-07-24 01:00:32 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
|
2011-11-17 08:26:07 +08:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_HS_HIGH;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_VS_HIGH;
|
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
|
|
|
|
|
|
|
|
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
|
|
|
|
intel_dp->DP |= DP_ENHANCED_FRAMING;
|
|
|
|
|
2013-06-01 23:16:20 +08:00
|
|
|
intel_dp->DP |= crtc->pipe << 29;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
|
2013-03-29 00:55:40 +08:00
|
|
|
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
|
2013-01-17 22:31:28 +08:00
|
|
|
intel_dp->DP |= intel_dp->color_range;
|
2011-11-02 10:54:11 +08:00
|
|
|
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_HS_HIGH;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_VS_HIGH;
|
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF;
|
|
|
|
|
|
|
|
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
|
|
|
|
intel_dp->DP |= DP_ENHANCED_FRAMING;
|
|
|
|
|
2013-06-01 23:16:20 +08:00
|
|
|
if (crtc->pipe == 1)
|
2011-11-02 10:54:11 +08:00
|
|
|
intel_dp->DP |= DP_PIPEB_SELECT;
|
|
|
|
} else {
|
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
2012-11-29 22:59:31 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (port == PORT_A && !IS_VALLEYVIEW(dev))
|
2013-06-01 23:16:20 +08:00
|
|
|
ironlake_set_pll_cpu_edp(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
|
|
|
|
#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
|
|
|
|
|
|
|
|
#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
|
|
|
|
#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
|
|
|
|
|
|
|
|
#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
|
|
|
|
#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
|
|
|
|
|
|
|
|
static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
|
|
|
|
u32 mask,
|
|
|
|
u32 value)
|
2011-09-19 14:09:52 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-11-02 10:57:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_stat_reg, pp_ctrl_reg;
|
|
|
|
|
|
|
|
pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
2011-09-30 07:51:26 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
|
2013-03-29 00:55:41 +08:00
|
|
|
mask, value,
|
|
|
|
I915_READ(pp_stat_reg),
|
|
|
|
I915_READ(pp_ctrl_reg));
|
2011-09-30 07:51:26 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
|
2013-03-29 00:55:41 +08:00
|
|
|
I915_READ(pp_stat_reg),
|
|
|
|
I915_READ(pp_ctrl_reg));
|
2011-09-30 07:51:26 +08:00
|
|
|
}
|
2011-11-02 10:57:50 +08:00
|
|
|
}
|
2011-09-30 07:51:26 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("Wait for panel power on\n");
|
|
|
|
ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("Wait for panel power off time\n");
|
|
|
|
ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("Wait for panel power cycle\n");
|
|
|
|
ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-11-02 10:34:06 +08:00
|
|
|
/* Read the current pp_control value, unlocking the register if it
|
|
|
|
* is locked
|
|
|
|
*/
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
|
2011-11-02 10:34:06 +08:00
|
|
|
{
|
2013-03-29 00:55:41 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 control;
|
|
|
|
u32 pp_ctrl_reg;
|
|
|
|
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
control = I915_READ(pp_ctrl_reg);
|
2011-11-02 10:34:06 +08:00
|
|
|
|
|
|
|
control &= ~PANEL_UNLOCK_MASK;
|
|
|
|
control |= PANEL_UNLOCK_REGS;
|
|
|
|
return control;
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
|
2012-10-24 04:30:07 +08:00
|
|
|
void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
|
2011-01-25 09:10:54 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-01-25 09:10:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_stat_reg, pp_ctrl_reg;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
DRM_DEBUG_KMS("Turn eDP VDD on\n");
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
WARN(intel_dp->want_panel_vdd,
|
|
|
|
"eDP VDD already requested on\n");
|
|
|
|
|
|
|
|
intel_dp->want_panel_vdd = true;
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
if (ironlake_edp_have_panel_vdd(intel_dp)) {
|
|
|
|
DRM_DEBUG_KMS("eDP VDD already on\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
if (!ironlake_edp_have_panel_power(intel_dp))
|
|
|
|
ironlake_wait_panel_power_cycle(intel_dp);
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2011-01-25 09:10:54 +08:00
|
|
|
pp |= EDP_FORCE_VDD;
|
2011-09-30 06:53:27 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
|
|
|
DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
|
|
|
|
I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
|
2011-09-30 06:53:27 +08:00
|
|
|
/*
|
|
|
|
* If the panel wasn't on, delay before accessing aux channel
|
|
|
|
*/
|
|
|
|
if (!ironlake_edp_have_panel_power(intel_dp)) {
|
2011-09-19 14:09:52 +08:00
|
|
|
DRM_DEBUG_KMS("eDP was not running\n");
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
msleep(intel_dp->panel_power_up_delay);
|
|
|
|
}
|
2011-01-25 09:10:54 +08:00
|
|
|
}
|
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
|
2011-01-25 09:10:54 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-01-25 09:10:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_stat_reg, pp_ctrl_reg;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2012-12-02 08:05:46 +08:00
|
|
|
WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
|
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
pp &= ~EDP_FORCE_VDD;
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
/* Make sure sequencer is idle before allowing subsequent activity */
|
|
|
|
DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
|
|
|
|
I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
|
2011-11-02 10:57:50 +08:00
|
|
|
msleep(intel_dp->panel_power_down_delay);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
}
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
static void ironlake_panel_vdd_work(struct work_struct *__work)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
|
|
|
|
struct intel_dp, panel_vdd_work);
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
|
2011-11-01 02:30:10 +08:00
|
|
|
mutex_lock(&dev->mode_config.mutex);
|
2011-09-19 14:09:52 +08:00
|
|
|
ironlake_panel_vdd_off_sync(intel_dp);
|
2011-11-01 02:30:10 +08:00
|
|
|
mutex_unlock(&dev->mode_config.mutex);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
|
2012-10-24 04:30:07 +08:00
|
|
|
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
|
2011-09-19 14:09:52 +08:00
|
|
|
{
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
|
|
|
|
WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
|
2011-11-02 11:01:35 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
intel_dp->want_panel_vdd = false;
|
|
|
|
|
|
|
|
if (sync) {
|
|
|
|
ironlake_panel_vdd_off_sync(intel_dp);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Queue the timer to fire a long
|
|
|
|
* time from now (relative to the power down delay)
|
|
|
|
* to keep the panel power up across a sequence of operations
|
|
|
|
*/
|
|
|
|
schedule_delayed_work(&intel_dp->panel_vdd_work,
|
|
|
|
msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
|
|
|
|
}
|
2011-01-25 09:10:54 +08:00
|
|
|
}
|
|
|
|
|
2012-10-24 04:30:07 +08:00
|
|
|
void ironlake_edp_panel_on(struct intel_dp *intel_dp)
|
2010-07-23 04:18:19 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2010-07-23 04:18:19 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-11-02 10:57:50 +08:00
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
2011-09-19 14:09:52 +08:00
|
|
|
return;
|
2011-11-02 10:57:50 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Turn eDP power on\n");
|
|
|
|
|
|
|
|
if (ironlake_edp_have_panel_power(intel_dp)) {
|
|
|
|
DRM_DEBUG_KMS("eDP power already on\n");
|
2011-09-30 07:05:34 +08:00
|
|
|
return;
|
2011-11-02 10:57:50 +08:00
|
|
|
}
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
ironlake_wait_panel_power_cycle(intel_dp);
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2011-09-30 07:33:01 +08:00
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
/* ILK workaround: disable reset around power sequence */
|
|
|
|
pp &= ~PANEL_POWER_RESET;
|
|
|
|
I915_WRITE(PCH_PP_CONTROL, pp);
|
|
|
|
POSTING_READ(PCH_PP_CONTROL);
|
|
|
|
}
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2011-09-20 04:59:29 +08:00
|
|
|
pp |= POWER_TARGET_ON;
|
2011-11-02 10:57:50 +08:00
|
|
|
if (!IS_GEN5(dev))
|
|
|
|
pp |= PANEL_POWER_RESET;
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
ironlake_wait_panel_on(intel_dp);
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-09-30 07:33:01 +08:00
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
|
|
|
|
I915_WRITE(PCH_PP_CONTROL, pp);
|
|
|
|
POSTING_READ(PCH_PP_CONTROL);
|
|
|
|
}
|
2010-07-23 04:18:19 +08:00
|
|
|
}
|
|
|
|
|
2012-10-24 04:30:07 +08:00
|
|
|
void ironlake_edp_panel_off(struct intel_dp *intel_dp)
|
2010-07-23 04:18:19 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2010-07-23 04:18:19 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-11-02 10:57:50 +08:00
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_DEBUG_KMS("Turn eDP power off\n");
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2012-05-20 23:14:50 +08:00
|
|
|
WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
drm/i915: reorder edp disabling to fix ivb MacBook Air
eDP is tons of fun. It turns out that at least the new MacBook Air 5,1
model absolutely doesn't like the new force vdd dance we've introduced
in
commit 6cb49835da0426f69a2931bc2a0a8156344b0e41
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sun May 20 17:14:50 2012 +0200
drm/i915: enable vdd when switching off the eDP panel
But that patch also tried to fix some neat edp sequence issue with the
force_vdd timings. Closer inspection reveals that we've raised
force_vdd only to do the aux channel communication dp_sink_dpms. If we
move the edp_panel_off below that, we don't need any force_vdd for the
disable sequence, which makes the Air happy.
Unfortunately the reporter of the original bug that the above commit
fixed is travelling, so we can't test whether this regresses things.
But my theory is that since we don't check for any power-off ->
force_vdd-on delays in edp_panel_vdd_on, this was the actual
root-cause of this failure. With that force_vdd dance completely
eliminated, I'm hopeful the original bug stays fixed, too.
For reference the old bug, which hopefully doesn't get broken by this:
https://bugzilla.kernel.org/show_bug.cgi?id=43163
In any case, regression fixers win over plain bugfixes, so this needs
to go in asap.
v2: The crucial pieces seems to be to clear the force_vdd flag
uncoditionally, too, in edp_panel_off. Looks like this is left behind
by the firmware somehow.
v3: The Apple firmware seems to switch off the panel on it's own, hence
we still need to keep force_vdd on, but properly clear it when switching
the panel off.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=45671
Tested-by: Roberto Romer <sildurin@gmail.com>
Tested-by: Daniel Wagner <wagi@monom.org>
Tested-by: Keith Packard <keithp@keithp.com>
Cc: stable@vger.kernel.org
Cc: Keith Packard <keithp@keithp.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-13 04:17:14 +08:00
|
|
|
/* We need to switch off panel power _and_ force vdd, for otherwise some
|
|
|
|
* panels get very unhappy and cease to work. */
|
|
|
|
pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2010-07-23 04:18:19 +08:00
|
|
|
|
drm/i915: reorder edp disabling to fix ivb MacBook Air
eDP is tons of fun. It turns out that at least the new MacBook Air 5,1
model absolutely doesn't like the new force vdd dance we've introduced
in
commit 6cb49835da0426f69a2931bc2a0a8156344b0e41
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sun May 20 17:14:50 2012 +0200
drm/i915: enable vdd when switching off the eDP panel
But that patch also tried to fix some neat edp sequence issue with the
force_vdd timings. Closer inspection reveals that we've raised
force_vdd only to do the aux channel communication dp_sink_dpms. If we
move the edp_panel_off below that, we don't need any force_vdd for the
disable sequence, which makes the Air happy.
Unfortunately the reporter of the original bug that the above commit
fixed is travelling, so we can't test whether this regresses things.
But my theory is that since we don't check for any power-off ->
force_vdd-on delays in edp_panel_vdd_on, this was the actual
root-cause of this failure. With that force_vdd dance completely
eliminated, I'm hopeful the original bug stays fixed, too.
For reference the old bug, which hopefully doesn't get broken by this:
https://bugzilla.kernel.org/show_bug.cgi?id=43163
In any case, regression fixers win over plain bugfixes, so this needs
to go in asap.
v2: The crucial pieces seems to be to clear the force_vdd flag
uncoditionally, too, in edp_panel_off. Looks like this is left behind
by the firmware somehow.
v3: The Apple firmware seems to switch off the panel on it's own, hence
we still need to keep force_vdd on, but properly clear it when switching
the panel off.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=45671
Tested-by: Roberto Romer <sildurin@gmail.com>
Tested-by: Daniel Wagner <wagi@monom.org>
Tested-by: Keith Packard <keithp@keithp.com>
Cc: stable@vger.kernel.org
Cc: Keith Packard <keithp@keithp.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-13 04:17:14 +08:00
|
|
|
intel_dp->want_panel_vdd = false;
|
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
ironlake_wait_panel_off(intel_dp);
|
2010-07-23 04:18:19 +08:00
|
|
|
}
|
|
|
|
|
2012-10-24 04:30:06 +08:00
|
|
|
void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
|
2009-07-24 01:00:32 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-07-24 01:00:32 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-27 05:05:46 +08:00
|
|
|
int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
|
2009-07-24 01:00:32 +08:00
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2009-07-24 01:00:32 +08:00
|
|
|
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
|
|
|
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
2010-10-08 07:01:12 +08:00
|
|
|
/*
|
|
|
|
* If we enable the backlight right away following a panel power
|
|
|
|
* on, we may see slight flicker as the panel syncs with the eDP
|
|
|
|
* link. So delay a bit to make sure the image is solid before
|
|
|
|
* allowing it to appear.
|
|
|
|
*/
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
msleep(intel_dp->backlight_on_delay);
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2009-07-24 01:00:32 +08:00
|
|
|
pp |= EDP_BLC_ENABLE;
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2012-10-21 02:57:42 +08:00
|
|
|
|
|
|
|
intel_panel_enable_backlight(dev, pipe);
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
|
|
|
|
2012-10-24 04:30:06 +08:00
|
|
|
void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
|
2009-07-24 01:00:32 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2009-07-24 01:00:32 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2009-07-24 01:00:32 +08:00
|
|
|
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
|
|
|
|
2012-10-21 02:57:42 +08:00
|
|
|
intel_panel_disable_backlight(dev);
|
|
|
|
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2009-07-24 01:00:32 +08:00
|
|
|
pp &= ~EDP_BLC_ENABLE;
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
|
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
msleep(intel_dp->backlight_off_delay);
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2010-08-14 06:43:26 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 dpa_ctl;
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
assert_pipe_disabled(dev_priv,
|
|
|
|
to_intel_crtc(crtc)->pipe);
|
|
|
|
|
2010-08-14 06:43:26 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
dpa_ctl = I915_READ(DP_A);
|
2012-09-07 04:15:42 +08:00
|
|
|
WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
|
|
|
|
WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
|
|
|
|
|
|
|
|
/* We don't adjust intel_dp->DP while tearing down the link, to
|
|
|
|
* facilitate link retraining (e.g. after hotplug). Hence clear all
|
|
|
|
* enable bits here to ensure that we don't enable too much. */
|
|
|
|
intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
|
|
|
|
intel_dp->DP |= DP_PLL_ENABLE;
|
|
|
|
I915_WRITE(DP_A, intel_dp->DP);
|
2010-10-08 07:01:24 +08:00
|
|
|
POSTING_READ(DP_A);
|
|
|
|
udelay(200);
|
2010-08-14 06:43:26 +08:00
|
|
|
}
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2010-08-14 06:43:26 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 dpa_ctl;
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
assert_pipe_disabled(dev_priv,
|
|
|
|
to_intel_crtc(crtc)->pipe);
|
|
|
|
|
2010-08-14 06:43:26 +08:00
|
|
|
dpa_ctl = I915_READ(DP_A);
|
2012-09-07 04:15:42 +08:00
|
|
|
WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
|
|
|
|
"dp pll off, should be on\n");
|
|
|
|
WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
|
|
|
|
|
|
|
|
/* We can't rely on the value tracked for the DP register in
|
|
|
|
* intel_dp->DP because link_down must not change that (otherwise link
|
|
|
|
* re-training will fail. */
|
2010-10-08 07:01:24 +08:00
|
|
|
dpa_ctl &= ~DP_PLL_ENABLE;
|
2010-08-14 06:43:26 +08:00
|
|
|
I915_WRITE(DP_A, dpa_ctl);
|
2010-09-09 04:07:28 +08:00
|
|
|
POSTING_READ(DP_A);
|
2010-08-14 06:43:26 +08:00
|
|
|
udelay(200);
|
|
|
|
}
|
|
|
|
|
2011-07-08 02:11:03 +08:00
|
|
|
/* If the sink supports it, try to set the power state appropriately */
|
2012-10-16 02:51:41 +08:00
|
|
|
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
|
2011-07-08 02:11:03 +08:00
|
|
|
{
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
/* Should have a valid DPCD by this point */
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (mode != DRM_MODE_DPMS_ON) {
|
|
|
|
ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
|
|
|
|
DP_SET_POWER_D3);
|
|
|
|
if (ret != 1)
|
|
|
|
DRM_DEBUG_DRIVER("failed to write sink power state\n");
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* When turning on, we need to retry for 1ms to give the sink
|
|
|
|
* time to wake up.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
ret = intel_dp_aux_native_write_1(intel_dp,
|
|
|
|
DP_SET_POWER,
|
|
|
|
DP_SET_POWER_D0);
|
|
|
|
if (ret == 1)
|
|
|
|
break;
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-02 19:26:27 +08:00
|
|
|
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-07-02 19:26:27 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2012-07-02 19:26:27 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 tmp = I915_READ(intel_dp->output_reg);
|
|
|
|
|
|
|
|
if (!(tmp & DP_PORT_EN))
|
|
|
|
return false;
|
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
|
2012-07-02 19:26:27 +08:00
|
|
|
*pipe = PORT_TO_PIPE_CPT(tmp);
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
|
2012-07-02 19:26:27 +08:00
|
|
|
*pipe = PORT_TO_PIPE(tmp);
|
|
|
|
} else {
|
|
|
|
u32 trans_sel;
|
|
|
|
u32 trans_dp;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
switch (intel_dp->output_reg) {
|
|
|
|
case PCH_DP_B:
|
|
|
|
trans_sel = TRANS_DP_PORT_SEL_B;
|
|
|
|
break;
|
|
|
|
case PCH_DP_C:
|
|
|
|
trans_sel = TRANS_DP_PORT_SEL_C;
|
|
|
|
break;
|
|
|
|
case PCH_DP_D:
|
|
|
|
trans_sel = TRANS_DP_PORT_SEL_D;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_pipe(i) {
|
|
|
|
trans_dp = I915_READ(TRANS_DP_CTL(i));
|
|
|
|
if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
|
|
|
|
*pipe = i;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-26 16:58:11 +08:00
|
|
|
DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
|
|
|
|
intel_dp->output_reg);
|
|
|
|
}
|
2010-08-14 06:43:26 +08:00
|
|
|
|
2013-04-04 07:15:45 +08:00
|
|
|
return true;
|
2012-07-02 19:26:27 +08:00
|
|
|
}
|
2010-08-14 06:43:26 +08:00
|
|
|
|
2013-05-15 08:08:26 +08:00
|
|
|
static void intel_dp_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
|
|
u32 tmp, flags = 0;
|
|
|
|
|
|
|
|
tmp = I915_READ(intel_dp->output_reg);
|
|
|
|
|
|
|
|
if (tmp & DP_SYNC_HS_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
|
|
|
|
|
|
if (tmp & DP_SYNC_VS_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
|
|
|
|
pipe_config->adjusted_mode.flags |= flags;
|
|
|
|
}
|
|
|
|
|
2012-07-01 19:05:48 +08:00
|
|
|
static void intel_disable_dp(struct intel_encoder *encoder)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-07-01 19:05:48 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-24 00:39:40 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2012-05-20 23:14:50 +08:00
|
|
|
|
|
|
|
/* Make sure the panel is off before trying to change the mode. But also
|
|
|
|
* ensure that we have vdd while we switch off the panel. */
|
|
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
2011-11-02 11:25:21 +08:00
|
|
|
ironlake_edp_backlight_off(intel_dp);
|
2011-07-08 02:11:03 +08:00
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
|
drm/i915: reorder edp disabling to fix ivb MacBook Air
eDP is tons of fun. It turns out that at least the new MacBook Air 5,1
model absolutely doesn't like the new force vdd dance we've introduced
in
commit 6cb49835da0426f69a2931bc2a0a8156344b0e41
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sun May 20 17:14:50 2012 +0200
drm/i915: enable vdd when switching off the eDP panel
But that patch also tried to fix some neat edp sequence issue with the
force_vdd timings. Closer inspection reveals that we've raised
force_vdd only to do the aux channel communication dp_sink_dpms. If we
move the edp_panel_off below that, we don't need any force_vdd for the
disable sequence, which makes the Air happy.
Unfortunately the reporter of the original bug that the above commit
fixed is travelling, so we can't test whether this regresses things.
But my theory is that since we don't check for any power-off ->
force_vdd-on delays in edp_panel_vdd_on, this was the actual
root-cause of this failure. With that force_vdd dance completely
eliminated, I'm hopeful the original bug stays fixed, too.
For reference the old bug, which hopefully doesn't get broken by this:
https://bugzilla.kernel.org/show_bug.cgi?id=43163
In any case, regression fixers win over plain bugfixes, so this needs
to go in asap.
v2: The crucial pieces seems to be to clear the force_vdd flag
uncoditionally, too, in edp_panel_off. Looks like this is left behind
by the firmware somehow.
v3: The Apple firmware seems to switch off the panel on it's own, hence
we still need to keep force_vdd on, but properly clear it when switching
the panel off.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=45671
Tested-by: Roberto Romer <sildurin@gmail.com>
Tested-by: Daniel Wagner <wagi@monom.org>
Tested-by: Keith Packard <keithp@keithp.com>
Cc: stable@vger.kernel.org
Cc: Keith Packard <keithp@keithp.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-13 04:17:14 +08:00
|
|
|
ironlake_edp_panel_off(intel_dp);
|
2012-09-07 04:15:44 +08:00
|
|
|
|
|
|
|
/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
|
2013-05-24 00:39:40 +08:00
|
|
|
if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
|
2012-09-07 04:15:44 +08:00
|
|
|
intel_dp_link_down(intel_dp);
|
2010-08-14 06:43:26 +08:00
|
|
|
}
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
static void intel_post_disable_dp(struct intel_encoder *encoder)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-09-07 04:15:41 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-24 00:39:40 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2013-03-29 00:55:40 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2012-09-07 04:15:41 +08:00
|
|
|
|
2013-05-24 00:39:40 +08:00
|
|
|
if (port == PORT_A || IS_VALLEYVIEW(dev)) {
|
2012-09-07 04:15:44 +08:00
|
|
|
intel_dp_link_down(intel_dp);
|
2013-03-29 00:55:40 +08:00
|
|
|
if (!IS_VALLEYVIEW(dev))
|
|
|
|
ironlake_edp_pll_off(intel_dp);
|
2012-09-07 04:15:44 +08:00
|
|
|
}
|
2012-09-07 04:15:41 +08:00
|
|
|
}
|
|
|
|
|
2012-07-01 19:05:48 +08:00
|
|
|
static void intel_enable_dp(struct intel_encoder *encoder)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-07-01 19:05:48 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t dp_reg = I915_READ(intel_dp->output_reg);
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2012-09-07 04:15:43 +08:00
|
|
|
if (WARN_ON(dp_reg & DP_PORT_EN))
|
|
|
|
return;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_start_link_train(intel_dp);
|
2011-09-29 07:23:51 +08:00
|
|
|
ironlake_edp_panel_on(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
ironlake_edp_panel_vdd_off(intel_dp, true);
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_complete_link_train(intel_dp);
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
ironlake_edp_backlight_on(intel_dp);
|
2013-04-19 05:51:36 +08:00
|
|
|
|
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
struct intel_digital_port *dport =
|
|
|
|
enc_to_dig_port(&encoder->base);
|
|
|
|
int channel = vlv_dport_to_channel(dport);
|
|
|
|
|
|
|
|
vlv_wait_port_ready(dev_priv, channel);
|
|
|
|
}
|
2010-08-14 06:43:26 +08:00
|
|
|
}
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
static void intel_pre_enable_dp(struct intel_encoder *encoder)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-09-07 04:15:41 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
2013-03-29 00:55:40 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2013-04-19 05:51:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
|
2012-09-07 04:15:41 +08:00
|
|
|
ironlake_edp_pll_on(intel_dp);
|
2013-04-19 05:51:36 +08:00
|
|
|
|
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(encoder->base.crtc);
|
|
|
|
int port = vlv_dport_to_channel(dport);
|
|
|
|
int pipe = intel_crtc->pipe;
|
|
|
|
u32 val;
|
|
|
|
|
2013-05-22 20:36:19 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
|
2013-04-19 05:51:36 +08:00
|
|
|
val = 0;
|
|
|
|
if (pipe)
|
|
|
|
val |= (1<<21);
|
|
|
|
else
|
|
|
|
val &= ~(1<<21);
|
|
|
|
val |= 0x001000c4;
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
|
2013-04-19 05:51:36 +08:00
|
|
|
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
|
2013-04-19 05:51:36 +08:00
|
|
|
0x00760018);
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
|
2013-04-19 05:51:36 +08:00
|
|
|
0x00400888);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int port = vlv_dport_to_channel(dport);
|
|
|
|
|
|
|
|
if (!IS_VALLEYVIEW(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Program Tx lane resets to default */
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
|
2013-04-19 05:51:36 +08:00
|
|
|
DPIO_PCS_TX_LANE2_RESET |
|
|
|
|
DPIO_PCS_TX_LANE1_RESET);
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
|
2013-04-19 05:51:36 +08:00
|
|
|
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
|
|
|
|
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
|
|
|
|
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
|
|
|
|
DPIO_PCS_CLK_SOFT_RESET);
|
|
|
|
|
|
|
|
/* Fix up inter-pair skew failure */
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2011-07-08 02:11:02 +08:00
|
|
|
* Native read with retry for link status and receiver capability reads for
|
|
|
|
* cases where the sink may still be asleep.
|
2009-04-08 07:16:42 +08:00
|
|
|
*/
|
|
|
|
static bool
|
2011-07-08 02:11:02 +08:00
|
|
|
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
|
|
|
|
uint8_t *recv, int recv_bytes)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2011-07-08 02:10:57 +08:00
|
|
|
int ret, i;
|
|
|
|
|
2011-07-08 02:11:02 +08:00
|
|
|
/*
|
|
|
|
* Sinks are *supposed* to come up within 1ms from an off state,
|
|
|
|
* but we're also supposed to retry 3 times per the spec.
|
|
|
|
*/
|
2011-07-08 02:10:57 +08:00
|
|
|
for (i = 0; i < 3; i++) {
|
2011-07-08 02:11:02 +08:00
|
|
|
ret = intel_dp_aux_native_read(intel_dp, address, recv,
|
|
|
|
recv_bytes);
|
|
|
|
if (ret == recv_bytes)
|
2011-07-08 02:10:57 +08:00
|
|
|
return true;
|
|
|
|
msleep(1);
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-07-08 02:10:57 +08:00
|
|
|
return false;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fetch AUX CH registers 0x202 - 0x207 which contain
|
|
|
|
* link status information
|
|
|
|
*/
|
|
|
|
static bool
|
2011-11-02 10:45:03 +08:00
|
|
|
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2011-07-08 02:11:02 +08:00
|
|
|
return intel_dp_aux_native_read_retry(intel_dp,
|
|
|
|
DP_LANE0_1_STATUS,
|
2011-11-02 10:45:03 +08:00
|
|
|
link_status,
|
2011-07-08 02:11:02 +08:00
|
|
|
DP_LINK_STATUS_SIZE);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
static char *voltage_names[] = {
|
|
|
|
"0.4V", "0.6V", "0.8V", "1.2V"
|
|
|
|
};
|
|
|
|
static char *pre_emph_names[] = {
|
|
|
|
"0dB", "3.5dB", "6dB", "9.5dB"
|
|
|
|
};
|
|
|
|
static char *link_train_names[] = {
|
|
|
|
"pattern 1", "pattern 2", "idle", "off"
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* These are source-specific values; current Intel hardware supports
|
|
|
|
* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
|
|
|
|
*/
|
|
|
|
|
|
|
|
static uint8_t
|
2011-11-17 08:26:07 +08:00
|
|
|
intel_dp_voltage_max(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2011-11-17 08:26:07 +08:00
|
|
|
|
2013-04-19 05:44:28 +08:00
|
|
|
if (IS_VALLEYVIEW(dev))
|
|
|
|
return DP_TRAIN_VOLTAGE_SWING_1200;
|
2013-05-16 19:40:36 +08:00
|
|
|
else if (IS_GEN7(dev) && port == PORT_A)
|
2011-11-17 08:26:07 +08:00
|
|
|
return DP_TRAIN_VOLTAGE_SWING_800;
|
2013-05-16 19:40:36 +08:00
|
|
|
else if (HAS_PCH_CPT(dev) && port != PORT_A)
|
2011-11-17 08:26:07 +08:00
|
|
|
return DP_TRAIN_VOLTAGE_SWING_1200;
|
|
|
|
else
|
|
|
|
return DP_TRAIN_VOLTAGE_SWING_800;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
|
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2011-11-17 08:26:07 +08:00
|
|
|
|
2013-02-19 06:00:23 +08:00
|
|
|
if (HAS_DDI(dev)) {
|
2012-10-16 02:51:34 +08:00
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_9_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
2013-04-19 05:44:28 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_9_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (IS_GEN7(dev) && port == PORT_A) {
|
2011-11-17 08:26:07 +08:00
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-19 05:44:28 +08:00
|
|
|
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
|
|
unsigned long demph_reg_value, preemph_reg_value,
|
|
|
|
uniqtranscale_reg_value;
|
|
|
|
uint8_t train_set = intel_dp->train_set[0];
|
2013-04-19 23:46:35 +08:00
|
|
|
int port = vlv_dport_to_channel(dport);
|
2013-04-19 05:44:28 +08:00
|
|
|
|
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
preemph_reg_value = 0x0004000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x2B405555;
|
|
|
|
uniqtranscale_reg_value = 0x552AB83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
demph_reg_value = 0x2B404040;
|
|
|
|
uniqtranscale_reg_value = 0x5548B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
demph_reg_value = 0x2B245555;
|
|
|
|
uniqtranscale_reg_value = 0x5560B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
demph_reg_value = 0x2B405555;
|
|
|
|
uniqtranscale_reg_value = 0x5598DA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
preemph_reg_value = 0x0002000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x2B404040;
|
|
|
|
uniqtranscale_reg_value = 0x5552B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
demph_reg_value = 0x2B404848;
|
|
|
|
uniqtranscale_reg_value = 0x5580B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
demph_reg_value = 0x2B404040;
|
|
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
preemph_reg_value = 0x0000000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x2B305555;
|
|
|
|
uniqtranscale_reg_value = 0x5570B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
demph_reg_value = 0x2B2B4040;
|
|
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
preemph_reg_value = 0x0006000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x1B405555;
|
|
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
|
2013-04-19 05:44:28 +08:00
|
|
|
uniqtranscale_reg_value);
|
2013-05-22 20:36:19 +08:00
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
|
2013-04-19 05:44:28 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static void
|
2011-11-02 10:45:03 +08:00
|
|
|
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
|
|
|
uint8_t v = 0;
|
|
|
|
uint8_t p = 0;
|
|
|
|
int lane;
|
2011-11-17 08:26:07 +08:00
|
|
|
uint8_t voltage_max;
|
|
|
|
uint8_t preemph_max;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
for (lane = 0; lane < intel_dp->lane_count; lane++) {
|
2012-10-18 16:15:27 +08:00
|
|
|
uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
|
|
|
|
uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
if (this_v > v)
|
|
|
|
v = this_v;
|
|
|
|
if (this_p > p)
|
|
|
|
p = this_p;
|
|
|
|
}
|
|
|
|
|
2011-11-17 08:26:07 +08:00
|
|
|
voltage_max = intel_dp_voltage_max(intel_dp);
|
2011-11-02 10:54:11 +08:00
|
|
|
if (v >= voltage_max)
|
|
|
|
v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-17 08:26:07 +08:00
|
|
|
preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
|
|
|
|
if (p >= preemph_max)
|
|
|
|
p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
for (lane = 0; lane < 4; lane++)
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp->train_set[lane] = v | p;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
2012-12-07 02:51:50 +08:00
|
|
|
intel_gen4_signal_levels(uint8_t train_set)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2010-11-29 18:09:55 +08:00
|
|
|
uint32_t signal_levels = 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
2009-04-08 07:16:42 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
default:
|
|
|
|
signal_levels |= DP_VOLTAGE_0_4;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
signal_levels |= DP_VOLTAGE_0_6;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
signal_levels |= DP_VOLTAGE_0_8;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
signal_levels |= DP_VOLTAGE_1_2;
|
|
|
|
break;
|
|
|
|
}
|
2010-11-29 18:09:55 +08:00
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
2009-04-08 07:16:42 +08:00
|
|
|
case DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
default:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_0;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_3_5;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_6;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_9_5;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return signal_levels;
|
|
|
|
}
|
|
|
|
|
2010-04-08 09:43:27 +08:00
|
|
|
/* Gen6's DP voltage swing and pre-emphasis control */
|
|
|
|
static uint32_t
|
|
|
|
intel_gen6_edp_signal_levels(uint8_t train_set)
|
|
|
|
{
|
2011-01-06 18:26:08 +08:00
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
default:
|
2011-01-06 18:26:08 +08:00
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
|
|
|
|
"0x%x\n", signal_levels);
|
|
|
|
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-17 08:26:07 +08:00
|
|
|
/* Gen7's DP voltage swing and pre-emphasis control */
|
|
|
|
static uint32_t
|
|
|
|
intel_gen7_edp_signal_levels(uint8_t train_set)
|
|
|
|
{
|
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_400MV_0DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return EDP_LINK_TRAIN_400MV_6DB_IVB;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_600MV_0DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_800MV_0DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
|
|
|
|
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
|
|
|
|
"0x%x\n", signal_levels);
|
|
|
|
return EDP_LINK_TRAIN_500MV_0DB_IVB;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
|
|
|
|
static uint32_t
|
2012-12-07 02:51:50 +08:00
|
|
|
intel_hsw_signal_levels(uint8_t train_set)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-16 02:51:34 +08:00
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return DDI_BUF_EMP_400MV_0DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return DDI_BUF_EMP_400MV_3_5DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return DDI_BUF_EMP_400MV_6DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
return DDI_BUF_EMP_400MV_9_5DB_HSW;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return DDI_BUF_EMP_600MV_0DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return DDI_BUF_EMP_600MV_3_5DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return DDI_BUF_EMP_600MV_6DB_HSW;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return DDI_BUF_EMP_800MV_0DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return DDI_BUF_EMP_800MV_3_5DB_HSW;
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
|
|
|
|
"0x%x\n", signal_levels);
|
|
|
|
return DDI_BUF_EMP_400MV_0DB_HSW;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-07 02:51:50 +08:00
|
|
|
/* Properly updates "DP" with the correct signal levels. */
|
|
|
|
static void
|
|
|
|
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2012-12-07 02:51:50 +08:00
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
uint32_t signal_levels, mask;
|
|
|
|
uint8_t train_set = intel_dp->train_set[0];
|
|
|
|
|
2013-02-19 06:00:23 +08:00
|
|
|
if (HAS_DDI(dev)) {
|
2012-12-07 02:51:50 +08:00
|
|
|
signal_levels = intel_hsw_signal_levels(train_set);
|
|
|
|
mask = DDI_BUF_EMP_MASK;
|
2013-04-19 05:44:28 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
|
|
signal_levels = intel_vlv_signal_levels(intel_dp);
|
|
|
|
mask = 0;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (IS_GEN7(dev) && port == PORT_A) {
|
2012-12-07 02:51:50 +08:00
|
|
|
signal_levels = intel_gen7_edp_signal_levels(train_set);
|
|
|
|
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (IS_GEN6(dev) && port == PORT_A) {
|
2012-12-07 02:51:50 +08:00
|
|
|
signal_levels = intel_gen6_edp_signal_levels(train_set);
|
|
|
|
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
|
|
|
|
} else {
|
|
|
|
signal_levels = intel_gen4_signal_levels(train_set);
|
|
|
|
mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
|
|
|
|
|
|
|
|
*DP = (*DP & ~mask) | signal_levels;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static bool
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_set_link_train(struct intel_dp *intel_dp,
|
2009-04-08 07:16:42 +08:00
|
|
|
uint32_t dp_reg_value,
|
2010-10-03 17:56:11 +08:00
|
|
|
uint8_t dp_train_pat)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:50 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-27 05:05:50 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2009-04-08 07:16:42 +08:00
|
|
|
int ret;
|
|
|
|
|
2013-02-19 06:00:23 +08:00
|
|
|
if (HAS_DDI(dev)) {
|
2013-05-03 17:57:41 +08:00
|
|
|
uint32_t temp = I915_READ(DP_TP_CTL(port));
|
2012-10-16 02:51:34 +08:00
|
|
|
|
|
|
|
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
|
|
|
|
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
|
|
|
|
else
|
|
|
|
temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
|
|
|
|
|
|
|
|
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
|
|
|
|
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
|
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
|
|
|
|
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
|
|
|
|
break;
|
|
|
|
}
|
2012-10-27 05:05:50 +08:00
|
|
|
I915_WRITE(DP_TP_CTL(port), temp);
|
2012-10-16 02:51:34 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
|
2012-07-18 03:55:16 +08:00
|
|
|
dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
|
|
|
|
|
|
|
|
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
|
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
DRM_ERROR("DP training pattern 3 not supported\n");
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
|
|
|
dp_reg_value &= ~DP_LINK_TRAIN_MASK;
|
|
|
|
|
|
|
|
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
|
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_OFF;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_PAT_1;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_PAT_2;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
DRM_ERROR("DP training pattern 3 not supported\n");
|
|
|
|
dp_reg_value |= DP_LINK_TRAIN_PAT_2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, dp_reg_value);
|
|
|
|
POSTING_READ(intel_dp->output_reg);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_aux_native_write_1(intel_dp,
|
2009-04-08 07:16:42 +08:00
|
|
|
DP_TRAINING_PATTERN_SET,
|
|
|
|
dp_train_pat);
|
|
|
|
|
2012-07-18 03:55:16 +08:00
|
|
|
if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
|
|
|
|
DP_TRAINING_PATTERN_DISABLE) {
|
|
|
|
ret = intel_dp_aux_native_write(intel_dp,
|
|
|
|
DP_TRAINING_LANE0_SET,
|
|
|
|
intel_dp->train_set,
|
|
|
|
intel_dp->lane_count);
|
|
|
|
if (ret != intel_dp->lane_count)
|
|
|
|
return false;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-05-03 17:57:41 +08:00
|
|
|
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
if (!HAS_DDI(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
|
|
val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
|
|
|
|
val |= DP_TP_CTL_LINK_TRAIN_IDLE;
|
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On PORT_A we can have only eDP in SST mode. There the only reason
|
|
|
|
* we need to set idle transmission mode is to work around a HW issue
|
|
|
|
* where we enable the pipe while not in idle link-training mode.
|
|
|
|
* In this case there is requirement to wait for a minimum number of
|
|
|
|
* idle patterns to be sent.
|
|
|
|
*/
|
|
|
|
if (port == PORT_A)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
|
|
|
|
1))
|
|
|
|
DRM_ERROR("Timed out waiting for DP idle patterns\n");
|
|
|
|
}
|
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
/* Enable corresponding port and start training pattern 1 */
|
2012-10-16 02:51:41 +08:00
|
|
|
void
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_start_link_train(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
|
2012-10-16 02:51:41 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
int i;
|
|
|
|
uint8_t voltage;
|
|
|
|
bool clock_recovery = false;
|
2011-11-02 11:00:06 +08:00
|
|
|
int voltage_tries, loop_tries;
|
2010-08-04 20:50:23 +08:00
|
|
|
uint32_t DP = intel_dp->DP;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-11-24 01:30:39 +08:00
|
|
|
if (HAS_DDI(dev))
|
2012-10-16 02:51:41 +08:00
|
|
|
intel_ddi_prepare_link_retrain(encoder);
|
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
/* Write the link configuration data */
|
|
|
|
intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
|
|
|
|
intel_dp->link_configuration,
|
|
|
|
DP_LINK_CONFIGURATION_SIZE);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
DP |= DP_PORT_EN;
|
2011-11-17 08:26:07 +08:00
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
memset(intel_dp->train_set, 0, 4);
|
2009-04-08 07:16:42 +08:00
|
|
|
voltage = 0xff;
|
2011-11-02 11:00:06 +08:00
|
|
|
voltage_tries = 0;
|
|
|
|
loop_tries = 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
clock_recovery = false;
|
|
|
|
for (;;) {
|
2010-09-09 03:42:02 +08:00
|
|
|
/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
|
2011-11-02 10:45:03 +08:00
|
|
|
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
2012-12-07 02:51:50 +08:00
|
|
|
|
|
|
|
intel_dp_set_signal_levels(intel_dp, &DP);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-18 16:15:30 +08:00
|
|
|
/* Set training pattern 1 */
|
2012-07-18 03:55:16 +08:00
|
|
|
if (!intel_dp_set_link_train(intel_dp, DP,
|
2011-07-22 05:48:37 +08:00
|
|
|
DP_TRAINING_PATTERN_1 |
|
|
|
|
DP_LINK_SCRAMBLING_DISABLE))
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
|
|
|
|
2012-10-18 16:15:30 +08:00
|
|
|
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
|
2011-11-02 10:45:03 +08:00
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
|
|
|
DRM_ERROR("failed to get link status\n");
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2011-11-02 10:45:03 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-18 16:15:25 +08:00
|
|
|
if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
|
2011-11-02 10:45:03 +08:00
|
|
|
DRM_DEBUG_KMS("clock recovery OK\n");
|
2010-11-29 18:09:55 +08:00
|
|
|
clock_recovery = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check to see if we've tried the max voltage */
|
|
|
|
for (i = 0; i < intel_dp->lane_count; i++)
|
|
|
|
if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2013-03-12 01:40:16 +08:00
|
|
|
if (i == intel_dp->lane_count) {
|
2012-10-16 15:50:25 +08:00
|
|
|
++loop_tries;
|
|
|
|
if (loop_tries == 5) {
|
2011-11-02 11:00:06 +08:00
|
|
|
DRM_DEBUG_KMS("too many full retries, give up\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
memset(intel_dp->train_set, 0, 4);
|
|
|
|
voltage_tries = 0;
|
|
|
|
continue;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
/* Check to see if we've tried the same voltage 5 times */
|
2012-10-16 15:50:25 +08:00
|
|
|
if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
|
2012-09-26 23:48:30 +08:00
|
|
|
++voltage_tries;
|
2012-10-16 15:50:25 +08:00
|
|
|
if (voltage_tries == 5) {
|
|
|
|
DRM_DEBUG_KMS("too many voltage retries, give up\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
voltage_tries = 0;
|
|
|
|
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
/* Compute new intel_dp->train_set as requested by target */
|
2011-11-02 10:45:03 +08:00
|
|
|
intel_get_adjust_train(intel_dp, link_status);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp->DP = DP;
|
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:41 +08:00
|
|
|
void
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_complete_link_train(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
bool channel_eq = false;
|
2011-01-06 06:45:24 +08:00
|
|
|
int tries, cr_tries;
|
2010-09-09 03:42:02 +08:00
|
|
|
uint32_t DP = intel_dp->DP;
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/* channel equalization */
|
|
|
|
tries = 0;
|
2011-01-06 06:45:24 +08:00
|
|
|
cr_tries = 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
channel_eq = false;
|
|
|
|
for (;;) {
|
2011-11-02 10:45:03 +08:00
|
|
|
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2011-01-06 06:45:24 +08:00
|
|
|
if (cr_tries > 5) {
|
|
|
|
DRM_ERROR("failed to train DP, aborting\n");
|
|
|
|
intel_dp_link_down(intel_dp);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2012-12-07 02:51:50 +08:00
|
|
|
intel_dp_set_signal_levels(intel_dp, &DP);
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/* channel eq pattern */
|
2012-07-18 03:55:16 +08:00
|
|
|
if (!intel_dp_set_link_train(intel_dp, DP,
|
2011-07-22 05:48:37 +08:00
|
|
|
DP_TRAINING_PATTERN_2 |
|
|
|
|
DP_LINK_SCRAMBLING_DISABLE))
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
|
|
|
|
2012-10-18 16:15:30 +08:00
|
|
|
drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
|
2011-11-02 10:45:03 +08:00
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status))
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
|
|
|
|
2011-01-06 06:45:24 +08:00
|
|
|
/* Make sure clock is still ok */
|
2012-10-18 16:15:25 +08:00
|
|
|
if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
|
2011-01-06 06:45:24 +08:00
|
|
|
intel_dp_start_link_train(intel_dp);
|
|
|
|
cr_tries++;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2012-10-18 16:15:24 +08:00
|
|
|
if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
|
2010-11-29 18:09:55 +08:00
|
|
|
channel_eq = true;
|
|
|
|
break;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-01-06 06:45:24 +08:00
|
|
|
/* Try 5 times, then try clock recovery if that fails */
|
|
|
|
if (tries > 5) {
|
|
|
|
intel_dp_link_down(intel_dp);
|
|
|
|
intel_dp_start_link_train(intel_dp);
|
|
|
|
tries = 0;
|
|
|
|
cr_tries++;
|
|
|
|
continue;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
/* Compute new intel_dp->train_set as requested by target */
|
2011-11-02 10:45:03 +08:00
|
|
|
intel_get_adjust_train(intel_dp, link_status);
|
2010-11-29 18:09:55 +08:00
|
|
|
++tries;
|
2010-10-08 07:01:22 +08:00
|
|
|
}
|
2010-11-29 18:09:55 +08:00
|
|
|
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_set_idle_link_train(intel_dp);
|
|
|
|
|
|
|
|
intel_dp->DP = DP;
|
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
if (channel_eq)
|
2013-03-20 10:00:34 +08:00
|
|
|
DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
|
2012-10-16 02:51:34 +08:00
|
|
|
|
2013-05-03 17:57:41 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_dp_stop_link_train(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
intel_dp_set_link_train(intel_dp, intel_dp->DP,
|
|
|
|
DP_TRAINING_PATTERN_DISABLE);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_link_down(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2012-10-27 05:05:46 +08:00
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-11-29 22:59:33 +08:00
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(intel_dig_port->base.base.crtc);
|
2010-08-04 20:50:23 +08:00
|
|
|
uint32_t DP = intel_dp->DP;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-16 02:51:41 +08:00
|
|
|
/*
|
|
|
|
* DDI code has a strict mode set sequence and we should try to respect
|
|
|
|
* it, otherwise we might hang the machine in many different ways. So we
|
|
|
|
* really should be disabling the port only on a complete crtc_disable
|
|
|
|
* sequence. This function is just called under two conditions on DDI
|
|
|
|
* code:
|
|
|
|
* - Link train failed while doing crtc_enable, and on this case we
|
|
|
|
* really should respect the mode set sequence and wait for a
|
|
|
|
* crtc_disable.
|
|
|
|
* - Someone turned the monitor off and intel_dp_check_link_status
|
|
|
|
* called us. We don't need to disable the whole port on this case, so
|
|
|
|
* when someone turns the monitor on again,
|
|
|
|
* intel_ddi_prepare_link_retrain will take care of redoing the link
|
|
|
|
* train.
|
|
|
|
*/
|
2012-11-24 01:30:39 +08:00
|
|
|
if (HAS_DDI(dev))
|
2012-10-16 02:51:41 +08:00
|
|
|
return;
|
|
|
|
|
2012-09-07 04:15:43 +08:00
|
|
|
if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
|
2010-12-06 19:20:45 +08:00
|
|
|
return;
|
|
|
|
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
2009-07-24 01:00:32 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
|
2010-04-08 09:43:27 +08:00
|
|
|
DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
|
2010-04-08 09:43:27 +08:00
|
|
|
} else {
|
|
|
|
DP &= ~DP_LINK_TRAIN_MASK;
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
|
2010-04-08 09:43:27 +08:00
|
|
|
}
|
2010-09-12 04:37:48 +08:00
|
|
|
POSTING_READ(intel_dp->output_reg);
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2012-11-29 22:59:33 +08:00
|
|
|
/* We don't really know why we're doing this */
|
|
|
|
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2012-05-30 18:31:56 +08:00
|
|
|
if (HAS_PCH_IBX(dev) &&
|
2010-12-06 19:20:45 +08:00
|
|
|
I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
|
2012-10-27 05:05:46 +08:00
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
2011-04-17 13:38:35 +08:00
|
|
|
|
2010-11-18 09:32:59 +08:00
|
|
|
/* Hardware workaround: leaving our transcoder select
|
|
|
|
* set to transcoder B while it's off will prevent the
|
|
|
|
* corresponding HDMI output on transcoder A.
|
|
|
|
*
|
|
|
|
* Combine this with another hardware workaround:
|
|
|
|
* transcoder select bit can only be cleared while the
|
|
|
|
* port is enabled.
|
|
|
|
*/
|
|
|
|
DP &= ~DP_PIPEB_SELECT;
|
|
|
|
I915_WRITE(intel_dp->output_reg, DP);
|
|
|
|
|
|
|
|
/* Changes to enable or select take place the vblank
|
|
|
|
* after being written.
|
|
|
|
*/
|
2012-11-29 22:59:34 +08:00
|
|
|
if (WARN_ON(crtc == NULL)) {
|
|
|
|
/* We should never try to disable a port without a crtc
|
|
|
|
* attached. For paranoia keep the code around for a
|
|
|
|
* bit. */
|
2011-04-17 13:38:35 +08:00
|
|
|
POSTING_READ(intel_dp->output_reg);
|
|
|
|
msleep(50);
|
|
|
|
} else
|
2012-11-29 22:59:33 +08:00
|
|
|
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
2010-11-18 09:32:59 +08:00
|
|
|
}
|
|
|
|
|
2011-12-09 20:42:21 +08:00
|
|
|
DP &= ~DP_AUDIO_OUTPUT_ENABLE;
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
|
|
|
|
POSTING_READ(intel_dp->output_reg);
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
msleep(intel_dp->panel_power_down_delay);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2011-07-26 11:01:09 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_get_dpcd(struct intel_dp *intel_dp)
|
2011-07-26 10:50:10 +08:00
|
|
|
{
|
2012-12-14 00:09:02 +08:00
|
|
|
char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
|
|
|
|
|
2011-07-26 10:50:10 +08:00
|
|
|
if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
|
2012-09-18 22:58:49 +08:00
|
|
|
sizeof(intel_dp->dpcd)) == 0)
|
|
|
|
return false; /* aux transfer failed */
|
2011-07-26 10:50:10 +08:00
|
|
|
|
2012-12-14 00:09:02 +08:00
|
|
|
hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
|
|
|
|
32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
|
|
|
|
DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
|
|
|
|
|
2012-09-18 22:58:49 +08:00
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
|
|
|
|
return false; /* DPCD not present */
|
|
|
|
|
|
|
|
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
|
|
|
|
DP_DWN_STRM_PORT_PRESENT))
|
|
|
|
return true; /* native DP sink */
|
|
|
|
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
|
|
|
|
return true; /* no per-port downstream info */
|
|
|
|
|
|
|
|
if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
|
|
|
|
intel_dp->downstream_ports,
|
|
|
|
DP_MAX_DOWNSTREAM_PORTS) == 0)
|
|
|
|
return false; /* downstream port status fetch failed */
|
|
|
|
|
|
|
|
return true;
|
2011-07-26 10:50:10 +08:00
|
|
|
}
|
|
|
|
|
2012-05-15 04:05:47 +08:00
|
|
|
static void
|
|
|
|
intel_dp_probe_oui(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
u8 buf[3];
|
|
|
|
|
|
|
|
if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
|
|
|
|
return;
|
|
|
|
|
2012-06-12 19:20:47 +08:00
|
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
|
|
|
|
2012-05-15 04:05:47 +08:00
|
|
|
if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
|
|
|
|
DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
|
|
|
|
buf[0], buf[1], buf[2]);
|
|
|
|
|
|
|
|
if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
|
|
|
|
DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
|
|
|
|
buf[0], buf[1], buf[2]);
|
2012-06-12 19:20:47 +08:00
|
|
|
|
|
|
|
ironlake_edp_panel_vdd_off(intel_dp, false);
|
2012-05-15 04:05:47 +08:00
|
|
|
}
|
|
|
|
|
2011-10-21 06:09:17 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = intel_dp_aux_native_read_retry(intel_dp,
|
|
|
|
DP_DEVICE_SERVICE_IRQ_VECTOR,
|
|
|
|
sink_irq_vector, 1);
|
|
|
|
if (!ret)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
intel_dp_handle_test_request(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
/* NAK by default */
|
2012-10-21 03:13:05 +08:00
|
|
|
intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
|
2011-10-21 06:09:17 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/*
|
|
|
|
* According to DP spec
|
|
|
|
* 5.1.2:
|
|
|
|
* 1. Read DPCD
|
|
|
|
* 2. Configure link according to Receiver Capabilities
|
|
|
|
* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
|
|
|
|
* 4. Check link status on receipt of hot-plug interrupt
|
|
|
|
*/
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
void
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_check_link_status(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
|
2011-10-21 06:09:17 +08:00
|
|
|
u8 sink_irq_vector;
|
2011-11-02 10:45:03 +08:00
|
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
2011-10-21 06:09:17 +08:00
|
|
|
|
2012-10-27 05:05:46 +08:00
|
|
|
if (!intel_encoder->connectors_active)
|
2011-07-26 13:37:51 +08:00
|
|
|
return;
|
2011-07-08 02:10:59 +08:00
|
|
|
|
2012-10-27 05:05:46 +08:00
|
|
|
if (WARN_ON(!intel_encoder->base.crtc))
|
2009-04-08 07:16:42 +08:00
|
|
|
return;
|
|
|
|
|
2011-07-26 10:50:10 +08:00
|
|
|
/* Try to read receiver status if the link appears to be up */
|
2011-11-02 10:45:03 +08:00
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_link_down(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-07-26 10:50:10 +08:00
|
|
|
/* Now read the DPCD to see if it's actually running */
|
2011-07-26 11:01:09 +08:00
|
|
|
if (!intel_dp_get_dpcd(intel_dp)) {
|
2011-07-08 02:10:59 +08:00
|
|
|
intel_dp_link_down(intel_dp);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-10-21 06:09:17 +08:00
|
|
|
/* Try to read the source of the interrupt */
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
|
|
|
|
intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
|
|
|
|
/* Clear interrupt source */
|
|
|
|
intel_dp_aux_native_write_1(intel_dp,
|
|
|
|
DP_DEVICE_SERVICE_IRQ_VECTOR,
|
|
|
|
sink_irq_vector);
|
|
|
|
|
|
|
|
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
|
|
|
|
intel_dp_handle_test_request(intel_dp);
|
|
|
|
if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
|
|
|
|
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
|
|
|
|
}
|
|
|
|
|
2012-10-18 16:15:24 +08:00
|
|
|
if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
|
2011-07-26 10:50:10 +08:00
|
|
|
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
|
2012-10-27 05:05:46 +08:00
|
|
|
drm_get_encoder_name(&intel_encoder->base));
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_start_link_train(intel_dp);
|
|
|
|
intel_dp_complete_link_train(intel_dp);
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
2010-09-09 03:42:02 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2012-09-18 22:58:50 +08:00
|
|
|
/* XXX this is probably wrong for multiple downstream ports */
|
2011-07-13 05:38:04 +08:00
|
|
|
static enum drm_connector_status
|
2011-07-26 11:01:09 +08:00
|
|
|
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
|
2011-07-13 05:38:04 +08:00
|
|
|
{
|
2012-09-18 22:58:50 +08:00
|
|
|
uint8_t *dpcd = intel_dp->dpcd;
|
|
|
|
bool hpd;
|
|
|
|
uint8_t type;
|
|
|
|
|
|
|
|
if (!intel_dp_get_dpcd(intel_dp))
|
|
|
|
return connector_status_disconnected;
|
|
|
|
|
|
|
|
/* if there's no downstream port, we're done */
|
|
|
|
if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
|
2011-07-26 11:01:09 +08:00
|
|
|
return connector_status_connected;
|
2012-09-18 22:58:50 +08:00
|
|
|
|
|
|
|
/* If we're HPD-aware, SINK_COUNT changes dynamically */
|
|
|
|
hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
|
|
|
|
if (hpd) {
|
2012-09-21 04:42:45 +08:00
|
|
|
uint8_t reg;
|
2012-09-18 22:58:50 +08:00
|
|
|
if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
|
2012-09-21 04:42:45 +08:00
|
|
|
®, 1))
|
2012-09-18 22:58:50 +08:00
|
|
|
return connector_status_unknown;
|
2012-09-21 04:42:45 +08:00
|
|
|
return DP_GET_SINK_COUNT(reg) ? connector_status_connected
|
|
|
|
: connector_status_disconnected;
|
2012-09-18 22:58:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* If no HPD, poke DDC gently */
|
|
|
|
if (drm_probe_ddc(&intel_dp->adapter))
|
2011-07-26 11:01:09 +08:00
|
|
|
return connector_status_connected;
|
2012-09-18 22:58:50 +08:00
|
|
|
|
|
|
|
/* Well we tried, say unknown for unreliable port types */
|
|
|
|
type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
|
|
|
|
if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
|
|
|
|
return connector_status_unknown;
|
|
|
|
|
|
|
|
/* Anything else is out of spec, warn and ignore */
|
|
|
|
DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
|
2011-07-26 11:01:09 +08:00
|
|
|
return connector_status_disconnected;
|
2011-07-13 05:38:04 +08:00
|
|
|
}
|
|
|
|
|
2009-07-24 01:00:31 +08:00
|
|
|
static enum drm_connector_status
|
2010-09-19 13:09:06 +08:00
|
|
|
ironlake_dp_detect(struct intel_dp *intel_dp)
|
2009-07-24 01:00:31 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2012-12-14 00:09:01 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2009-07-24 01:00:31 +08:00
|
|
|
enum drm_connector_status status;
|
|
|
|
|
2011-02-12 18:29:38 +08:00
|
|
|
/* Can't disconnect eDP, but you can close the lid... */
|
|
|
|
if (is_edp(intel_dp)) {
|
2012-10-27 05:05:45 +08:00
|
|
|
status = intel_panel_detect(dev);
|
2011-02-12 18:29:38 +08:00
|
|
|
if (status == connector_status_unknown)
|
|
|
|
status = connector_status_connected;
|
|
|
|
return status;
|
|
|
|
}
|
2010-10-08 07:01:12 +08:00
|
|
|
|
2012-12-14 00:09:01 +08:00
|
|
|
if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
|
|
|
|
return connector_status_disconnected;
|
|
|
|
|
2011-07-26 11:01:09 +08:00
|
|
|
return intel_dp_detect_dpcd(intel_dp);
|
2009-07-24 01:00:31 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static enum drm_connector_status
|
2010-09-19 13:09:06 +08:00
|
|
|
g4x_dp_detect(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-01-24 21:29:27 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2012-05-12 01:01:32 +08:00
|
|
|
uint32_t bit;
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2013-03-02 05:14:31 +08:00
|
|
|
/* Can't disconnect eDP, but you can close the lid... */
|
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
enum drm_connector_status status;
|
|
|
|
|
|
|
|
status = intel_panel_detect(dev);
|
|
|
|
if (status == connector_status_unknown)
|
|
|
|
status = connector_status_connected;
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2013-01-24 21:29:27 +08:00
|
|
|
switch (intel_dig_port->port) {
|
|
|
|
case PORT_B:
|
2013-02-07 19:42:32 +08:00
|
|
|
bit = PORTB_HOTPLUG_LIVE_STATUS;
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2013-01-24 21:29:27 +08:00
|
|
|
case PORT_C:
|
2013-02-07 19:42:32 +08:00
|
|
|
bit = PORTC_HOTPLUG_LIVE_STATUS;
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2013-01-24 21:29:27 +08:00
|
|
|
case PORT_D:
|
2013-02-07 19:42:32 +08:00
|
|
|
bit = PORTD_HOTPLUG_LIVE_STATUS;
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return connector_status_unknown;
|
|
|
|
}
|
|
|
|
|
2012-05-12 01:01:32 +08:00
|
|
|
if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
|
2009-04-08 07:16:42 +08:00
|
|
|
return connector_status_disconnected;
|
|
|
|
|
2011-07-26 11:01:09 +08:00
|
|
|
return intel_dp_detect_dpcd(intel_dp);
|
2010-09-19 13:09:06 +08:00
|
|
|
}
|
|
|
|
|
2011-09-29 07:38:44 +08:00
|
|
|
static struct edid *
|
|
|
|
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
|
|
|
|
{
|
2012-10-19 19:51:52 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2012-06-15 03:28:33 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
/* use cached edid if we have one */
|
|
|
|
if (intel_connector->edid) {
|
|
|
|
struct edid *edid;
|
|
|
|
int size;
|
|
|
|
|
|
|
|
/* invalid edid */
|
|
|
|
if (IS_ERR(intel_connector->edid))
|
2012-06-15 03:28:33 +08:00
|
|
|
return NULL;
|
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
|
2013-05-23 05:07:09 +08:00
|
|
|
edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
|
2012-06-15 03:28:33 +08:00
|
|
|
if (!edid)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return edid;
|
|
|
|
}
|
2011-09-29 07:38:44 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
return drm_get_edid(connector, adapter);
|
2011-09-29 07:38:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
|
|
|
|
{
|
2012-10-19 19:51:52 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2011-09-29 07:38:44 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
/* use cached edid if we have one */
|
|
|
|
if (intel_connector->edid) {
|
|
|
|
/* invalid edid */
|
|
|
|
if (IS_ERR(intel_connector->edid))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return intel_connector_update_modes(connector,
|
|
|
|
intel_connector->edid);
|
2012-06-15 03:28:33 +08:00
|
|
|
}
|
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
return intel_ddc_get_modes(connector, adapter);
|
2011-09-29 07:38:44 +08:00
|
|
|
}
|
|
|
|
|
2010-09-19 13:09:06 +08:00
|
|
|
static enum drm_connector_status
|
|
|
|
intel_dp_detect(struct drm_connector *connector, bool force)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2012-10-27 05:05:49 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
2012-10-27 05:05:44 +08:00
|
|
|
struct drm_device *dev = connector->dev;
|
2010-09-19 13:09:06 +08:00
|
|
|
enum drm_connector_status status;
|
|
|
|
struct edid *edid = NULL;
|
|
|
|
|
|
|
|
intel_dp->has_audio = false;
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
status = ironlake_dp_detect(intel_dp);
|
|
|
|
else
|
|
|
|
status = g4x_dp_detect(intel_dp);
|
2011-07-13 05:38:01 +08:00
|
|
|
|
2010-09-19 13:09:06 +08:00
|
|
|
if (status != connector_status_connected)
|
|
|
|
return status;
|
|
|
|
|
2012-05-15 04:05:47 +08:00
|
|
|
intel_dp_probe_oui(intel_dp);
|
|
|
|
|
2012-02-24 00:14:47 +08:00
|
|
|
if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
|
|
|
|
intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
|
2010-09-19 16:29:33 +08:00
|
|
|
} else {
|
2011-09-29 07:38:44 +08:00
|
|
|
edid = intel_dp_get_edid(connector, &intel_dp->adapter);
|
2010-09-19 16:29:33 +08:00
|
|
|
if (edid) {
|
|
|
|
intel_dp->has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
kfree(edid);
|
|
|
|
}
|
2010-09-19 13:09:06 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:49 +08:00
|
|
|
if (intel_encoder->type != INTEL_OUTPUT_EDP)
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
|
2010-09-19 13:09:06 +08:00
|
|
|
return connector_status_connected;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_dp_get_modes(struct drm_connector *connector)
|
|
|
|
{
|
2010-09-09 23:20:55 +08:00
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2012-10-19 19:51:50 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2012-10-27 05:05:44 +08:00
|
|
|
struct drm_device *dev = connector->dev;
|
2009-07-24 01:00:32 +08:00
|
|
|
int ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
/* We should parse the EDID data and find out if it has an audio sink
|
|
|
|
*/
|
|
|
|
|
2011-09-29 07:38:44 +08:00
|
|
|
ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
|
2012-10-19 19:51:48 +08:00
|
|
|
if (ret)
|
2009-07-24 01:00:32 +08:00
|
|
|
return ret;
|
|
|
|
|
2012-10-19 19:51:48 +08:00
|
|
|
/* if eDP has no EDID, fall back to fixed mode */
|
2012-10-19 19:51:50 +08:00
|
|
|
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
|
2012-10-19 19:51:48 +08:00
|
|
|
struct drm_display_mode *mode;
|
2012-10-19 19:51:50 +08:00
|
|
|
mode = drm_mode_duplicate(dev,
|
|
|
|
intel_connector->panel.fixed_mode);
|
2012-10-19 19:51:48 +08:00
|
|
|
if (mode) {
|
2009-07-24 01:00:32 +08:00
|
|
|
drm_mode_probed_add(connector, mode);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_detect_audio(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
|
|
|
struct edid *edid;
|
|
|
|
bool has_audio = false;
|
|
|
|
|
2011-09-29 07:38:44 +08:00
|
|
|
edid = intel_dp_get_edid(connector, &intel_dp->adapter);
|
2011-02-10 02:46:58 +08:00
|
|
|
if (edid) {
|
|
|
|
has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
kfree(edid);
|
|
|
|
}
|
|
|
|
|
|
|
|
return has_audio;
|
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
static int
|
|
|
|
intel_dp_set_property(struct drm_connector *connector,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t val)
|
|
|
|
{
|
2011-02-22 06:23:52 +08:00
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
2012-10-26 17:04:00 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
2010-09-19 16:29:33 +08:00
|
|
|
int ret;
|
|
|
|
|
2012-10-12 09:36:04 +08:00
|
|
|
ret = drm_object_property_set_value(&connector->base, property, val);
|
2010-09-19 16:29:33 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-05-13 05:17:24 +08:00
|
|
|
if (property == dev_priv->force_audio_property) {
|
2011-02-10 02:46:58 +08:00
|
|
|
int i = val;
|
|
|
|
bool has_audio;
|
|
|
|
|
|
|
|
if (i == intel_dp->force_audio)
|
2010-09-19 16:29:33 +08:00
|
|
|
return 0;
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
intel_dp->force_audio = i;
|
2010-09-19 16:29:33 +08:00
|
|
|
|
2012-02-24 00:14:47 +08:00
|
|
|
if (i == HDMI_AUDIO_AUTO)
|
2011-02-10 02:46:58 +08:00
|
|
|
has_audio = intel_dp_detect_audio(connector);
|
|
|
|
else
|
2012-02-24 00:14:47 +08:00
|
|
|
has_audio = (i == HDMI_AUDIO_ON);
|
2011-02-10 02:46:58 +08:00
|
|
|
|
|
|
|
if (has_audio == intel_dp->has_audio)
|
2010-09-19 16:29:33 +08:00
|
|
|
return 0;
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
intel_dp->has_audio = has_audio;
|
2010-09-19 16:29:33 +08:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2011-02-22 06:23:52 +08:00
|
|
|
if (property == dev_priv->broadcast_rgb_property) {
|
2013-04-22 23:07:23 +08:00
|
|
|
bool old_auto = intel_dp->color_range_auto;
|
|
|
|
uint32_t old_range = intel_dp->color_range;
|
|
|
|
|
2013-01-17 22:31:29 +08:00
|
|
|
switch (val) {
|
|
|
|
case INTEL_BROADCAST_RGB_AUTO:
|
|
|
|
intel_dp->color_range_auto = true;
|
|
|
|
break;
|
|
|
|
case INTEL_BROADCAST_RGB_FULL:
|
|
|
|
intel_dp->color_range_auto = false;
|
|
|
|
intel_dp->color_range = 0;
|
|
|
|
break;
|
|
|
|
case INTEL_BROADCAST_RGB_LIMITED:
|
|
|
|
intel_dp->color_range_auto = false;
|
|
|
|
intel_dp->color_range = DP_COLOR_RANGE_16_235;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-04-22 23:07:23 +08:00
|
|
|
|
|
|
|
if (old_auto == intel_dp->color_range_auto &&
|
|
|
|
old_range == intel_dp->color_range)
|
|
|
|
return 0;
|
|
|
|
|
2011-02-22 06:23:52 +08:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2012-10-26 17:04:00 +08:00
|
|
|
if (is_edp(intel_dp) &&
|
|
|
|
property == connector->dev->mode_config.scaling_mode_property) {
|
|
|
|
if (val == DRM_MODE_SCALE_NONE) {
|
|
|
|
DRM_DEBUG_KMS("no scaling not supported\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_connector->panel.fitting_mode == val) {
|
|
|
|
/* the eDP scaling property is not changed */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
intel_connector->panel.fitting_mode = val;
|
|
|
|
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
done:
|
2012-12-20 00:08:43 +08:00
|
|
|
if (intel_encoder->base.crtc)
|
|
|
|
intel_crtc_restore_mode(intel_encoder->base.crtc);
|
2010-09-19 16:29:33 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static void
|
2011-08-17 03:34:10 +08:00
|
|
|
intel_dp_destroy(struct drm_connector *connector)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-12 15:33:05 +08:00
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2012-10-19 19:51:49 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2011-08-12 18:11:33 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
if (!IS_ERR_OR_NULL(intel_connector->edid))
|
|
|
|
kfree(intel_connector->edid);
|
|
|
|
|
2013-04-12 20:18:38 +08:00
|
|
|
if (is_edp(intel_dp))
|
2012-10-19 19:51:49 +08:00
|
|
|
intel_panel_fini(&intel_connector->panel);
|
2011-08-12 18:11:33 +08:00
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
drm_sysfs_connector_remove(connector);
|
|
|
|
drm_connector_cleanup(connector);
|
2010-03-29 16:13:57 +08:00
|
|
|
kfree(connector);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
|
2010-08-21 00:08:28 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
2013-03-25 18:24:10 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2010-08-21 00:08:28 +08:00
|
|
|
|
|
|
|
i2c_del_adapter(&intel_dp->adapter);
|
|
|
|
drm_encoder_cleanup(encoder);
|
2011-09-19 14:09:52 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
|
2013-03-25 18:24:10 +08:00
|
|
|
mutex_lock(&dev->mode_config.mutex);
|
2011-09-19 14:09:52 +08:00
|
|
|
ironlake_panel_vdd_off_sync(intel_dp);
|
2013-03-25 18:24:10 +08:00
|
|
|
mutex_unlock(&dev->mode_config.mutex);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
2012-10-27 05:05:46 +08:00
|
|
|
kfree(intel_dig_port);
|
2010-08-21 00:08:28 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
|
|
|
|
.mode_set = intel_dp_mode_set,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_funcs intel_dp_connector_funcs = {
|
2012-09-07 04:15:41 +08:00
|
|
|
.dpms = intel_connector_dpms,
|
2009-04-08 07:16:42 +08:00
|
|
|
.detect = intel_dp_detect,
|
|
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
2010-09-19 16:29:33 +08:00
|
|
|
.set_property = intel_dp_set_property,
|
2009-04-08 07:16:42 +08:00
|
|
|
.destroy = intel_dp_destroy,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
|
|
|
|
.get_modes = intel_dp_get_modes,
|
|
|
|
.mode_valid = intel_dp_mode_valid,
|
2010-09-09 23:20:55 +08:00
|
|
|
.best_encoder = intel_best_encoder,
|
2009-04-08 07:16:42 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_dp_enc_funcs = {
|
2010-08-21 00:08:28 +08:00
|
|
|
.destroy = intel_dp_encoder_destroy,
|
2009-04-08 07:16:42 +08:00
|
|
|
};
|
|
|
|
|
2010-08-20 20:23:26 +08:00
|
|
|
static void
|
2010-03-26 02:11:14 +08:00
|
|
|
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
|
2009-05-07 02:51:10 +08:00
|
|
|
{
|
2012-10-27 05:05:44 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
2009-05-07 02:51:10 +08:00
|
|
|
|
2011-07-08 02:11:01 +08:00
|
|
|
intel_dp_check_link_status(intel_dp);
|
2009-05-07 02:51:10 +08:00
|
|
|
}
|
2010-01-06 09:49:31 +08:00
|
|
|
|
2010-04-08 09:43:27 +08:00
|
|
|
/* Return which DP Port should be selected for Transcoder DP control */
|
|
|
|
int
|
2011-08-17 03:34:10 +08:00
|
|
|
intel_trans_dp_port_sel(struct drm_crtc *crtc)
|
2010-04-08 09:43:27 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2012-10-27 05:05:44 +08:00
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct intel_dp *intel_dp;
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2012-10-27 05:05:44 +08:00
|
|
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
|
|
|
|
intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2012-10-27 05:05:44 +08:00
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
|
|
|
|
intel_encoder->type == INTEL_OUTPUT_EDP)
|
2010-08-04 20:50:23 +08:00
|
|
|
return intel_dp->output_reg;
|
2010-04-08 09:43:27 +08:00
|
|
|
}
|
2010-08-04 20:50:23 +08:00
|
|
|
|
2010-04-08 09:43:27 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2010-06-12 14:32:21 +08:00
|
|
|
/* check the VBT to see whether the eDP is on DP-D port */
|
2010-07-17 02:46:29 +08:00
|
|
|
bool intel_dpd_is_edp(struct drm_device *dev)
|
2010-06-12 14:32:21 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct child_device_config *p_child;
|
|
|
|
int i;
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
if (!dev_priv->vbt.child_dev_num)
|
2010-06-12 14:32:21 +08:00
|
|
|
return false;
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
|
|
|
|
p_child = dev_priv->vbt.child_dev + i;
|
2010-06-12 14:32:21 +08:00
|
|
|
|
|
|
|
if (p_child->dvo_port == PORT_IDPD &&
|
|
|
|
p_child->device_type == DEVICE_TYPE_eDP)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
static void
|
|
|
|
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
|
|
|
|
{
|
2012-10-26 17:04:00 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
|
2011-05-13 05:17:24 +08:00
|
|
|
intel_attach_force_audio_property(connector);
|
2011-02-22 06:23:52 +08:00
|
|
|
intel_attach_broadcast_rgb_property(connector);
|
2013-01-17 22:31:29 +08:00
|
|
|
intel_dp->color_range_auto = true;
|
2012-10-26 17:04:00 +08:00
|
|
|
|
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
drm_mode_create_scaling_mode_property(connector->dev);
|
2012-10-12 09:36:04 +08:00
|
|
|
drm_object_attach_property(
|
|
|
|
&connector->base,
|
2012-10-26 17:04:00 +08:00
|
|
|
connector->dev->mode_config.scaling_mode_property,
|
2012-10-26 17:04:01 +08:00
|
|
|
DRM_MODE_SCALE_ASPECT);
|
|
|
|
intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
|
2012-10-26 17:04:00 +08:00
|
|
|
}
|
2010-09-19 16:29:33 +08:00
|
|
|
}
|
|
|
|
|
2012-10-21 02:57:45 +08:00
|
|
|
static void
|
|
|
|
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
|
2013-01-16 16:53:40 +08:00
|
|
|
struct intel_dp *intel_dp,
|
|
|
|
struct edp_power_seq *out)
|
2012-10-21 02:57:45 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct edp_power_seq cur, vbt, spec, final;
|
|
|
|
u32 pp_on, pp_off, pp_div, pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
pp_control_reg = PCH_PP_CONTROL;
|
|
|
|
pp_on_reg = PCH_PP_ON_DELAYS;
|
|
|
|
pp_off_reg = PCH_PP_OFF_DELAYS;
|
|
|
|
pp_div_reg = PCH_PP_DIVISOR;
|
|
|
|
} else {
|
|
|
|
pp_control_reg = PIPEA_PP_CONTROL;
|
|
|
|
pp_on_reg = PIPEA_PP_ON_DELAYS;
|
|
|
|
pp_off_reg = PIPEA_PP_OFF_DELAYS;
|
|
|
|
pp_div_reg = PIPEA_PP_DIVISOR;
|
|
|
|
}
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
/* Workaround: Need to write PP_CONTROL with the unlock key as
|
|
|
|
* the very first thing. */
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
|
|
|
I915_WRITE(pp_control_reg, pp);
|
2012-10-21 02:57:45 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_on = I915_READ(pp_on_reg);
|
|
|
|
pp_off = I915_READ(pp_off_reg);
|
|
|
|
pp_div = I915_READ(pp_div_reg);
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
/* Pull timing values out of registers */
|
|
|
|
cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
|
|
|
|
PANEL_POWER_UP_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
|
|
|
|
PANEL_LIGHT_ON_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
|
|
|
|
PANEL_LIGHT_OFF_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
|
|
|
|
PANEL_POWER_DOWN_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
|
|
|
|
PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
|
|
|
|
cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
vbt = dev_priv->vbt.edp_pps;
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
|
|
|
|
* our hw here, which are all in 100usec. */
|
|
|
|
spec.t1_t3 = 210 * 10;
|
|
|
|
spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
|
|
|
|
spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
|
|
|
|
spec.t10 = 500 * 10;
|
|
|
|
/* This one is special and actually in units of 100ms, but zero
|
|
|
|
* based in the hw (so we need to add 100 ms). But the sw vbt
|
|
|
|
* table multiplies it with 1000 to make it in units of 100usec,
|
|
|
|
* too. */
|
|
|
|
spec.t11_t12 = (510 + 100) * 10;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
|
|
|
|
vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
|
|
|
|
|
|
|
|
/* Use the max of the register settings and vbt. If both are
|
|
|
|
* unset, fall back to the spec limits. */
|
|
|
|
#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
|
|
|
|
spec.field : \
|
|
|
|
max(cur.field, vbt.field))
|
|
|
|
assign_final(t1_t3);
|
|
|
|
assign_final(t8);
|
|
|
|
assign_final(t9);
|
|
|
|
assign_final(t10);
|
|
|
|
assign_final(t11_t12);
|
|
|
|
#undef assign_final
|
|
|
|
|
|
|
|
#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
|
|
|
|
intel_dp->panel_power_up_delay = get_delay(t1_t3);
|
|
|
|
intel_dp->backlight_on_delay = get_delay(t8);
|
|
|
|
intel_dp->backlight_off_delay = get_delay(t9);
|
|
|
|
intel_dp->panel_power_down_delay = get_delay(t10);
|
|
|
|
intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
|
|
|
|
#undef get_delay
|
|
|
|
|
2013-01-16 16:53:40 +08:00
|
|
|
DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
|
|
|
|
intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
|
|
|
|
intel_dp->panel_power_cycle_delay);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
|
|
|
|
intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
|
|
|
|
|
|
|
|
if (out)
|
|
|
|
*out = final;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
|
|
|
|
struct intel_dp *intel_dp,
|
|
|
|
struct edp_power_seq *seq)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_on, pp_off, pp_div, port_sel = 0;
|
|
|
|
int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
|
|
|
|
int pp_on_reg, pp_off_reg, pp_div_reg;
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
pp_on_reg = PCH_PP_ON_DELAYS;
|
|
|
|
pp_off_reg = PCH_PP_OFF_DELAYS;
|
|
|
|
pp_div_reg = PCH_PP_DIVISOR;
|
|
|
|
} else {
|
|
|
|
pp_on_reg = PIPEA_PP_ON_DELAYS;
|
|
|
|
pp_off_reg = PIPEA_PP_OFF_DELAYS;
|
|
|
|
pp_div_reg = PIPEA_PP_DIVISOR;
|
|
|
|
}
|
|
|
|
|
2012-10-21 02:57:45 +08:00
|
|
|
/* And finally store the new values in the power sequencer. */
|
2013-01-16 16:53:40 +08:00
|
|
|
pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
|
|
|
|
(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
|
|
|
|
pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
|
|
|
|
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
|
2012-10-21 02:57:45 +08:00
|
|
|
/* Compute the divisor for the pp clock, simply match the Bspec
|
|
|
|
* formula. */
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
|
2013-01-16 16:53:40 +08:00
|
|
|
pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
|
2012-10-21 02:57:45 +08:00
|
|
|
<< PANEL_POWER_CYCLE_DELAY_SHIFT);
|
|
|
|
|
|
|
|
/* Haswell doesn't have any port selection bits for the panel
|
|
|
|
* power sequencer any more. */
|
2013-05-16 19:40:36 +08:00
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
port_sel = I915_READ(pp_on_reg) & 0xc0000000;
|
|
|
|
} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
|
|
|
|
if (dp_to_dig_port(intel_dp)->port == PORT_A)
|
2013-03-29 00:55:41 +08:00
|
|
|
port_sel = PANEL_POWER_PORT_DP_A;
|
2012-10-21 02:57:45 +08:00
|
|
|
else
|
2013-03-29 00:55:41 +08:00
|
|
|
port_sel = PANEL_POWER_PORT_DP_D;
|
2012-10-21 02:57:45 +08:00
|
|
|
}
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_on |= port_sel;
|
|
|
|
|
|
|
|
I915_WRITE(pp_on_reg, pp_on);
|
|
|
|
I915_WRITE(pp_off_reg, pp_off);
|
|
|
|
I915_WRITE(pp_div_reg, pp_div);
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
|
2013-03-29 00:55:41 +08:00
|
|
|
I915_READ(pp_on_reg),
|
|
|
|
I915_READ(pp_off_reg),
|
|
|
|
I915_READ(pp_div_reg));
|
2010-09-19 16:29:33 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
void
|
2012-10-27 05:05:48 +08:00
|
|
|
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:48 +08:00
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-19 19:51:48 +08:00
|
|
|
struct drm_display_mode *fixed_mode = NULL;
|
2013-01-16 16:53:40 +08:00
|
|
|
struct edp_power_seq power_seq = { 0 };
|
2012-10-27 05:05:50 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2009-07-24 01:00:31 +08:00
|
|
|
const char *name = NULL;
|
2010-07-17 02:46:28 +08:00
|
|
|
int type;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-09-07 04:15:42 +08:00
|
|
|
/* Preserve the current hw state. */
|
|
|
|
intel_dp->DP = I915_READ(intel_dp->output_reg);
|
2012-10-19 19:51:50 +08:00
|
|
|
intel_dp->attached_connector = intel_connector;
|
2011-02-12 18:33:12 +08:00
|
|
|
|
2013-05-08 18:14:05 +08:00
|
|
|
type = DRM_MODE_CONNECTOR_DisplayPort;
|
2012-09-27 21:43:07 +08:00
|
|
|
/*
|
|
|
|
* FIXME : We need to initialize built-in panels before external panels.
|
|
|
|
* For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
|
|
|
|
*/
|
2013-05-08 18:14:05 +08:00
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
2012-09-27 21:43:07 +08:00
|
|
|
type = DRM_MODE_CONNECTOR_eDP;
|
2013-05-08 18:14:05 +08:00
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
if (IS_VALLEYVIEW(dev))
|
|
|
|
type = DRM_MODE_CONNECTOR_eDP;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
|
|
|
|
type = DRM_MODE_CONNECTOR_eDP;
|
|
|
|
break;
|
|
|
|
default: /* silence GCC warning */
|
|
|
|
break;
|
2010-07-17 02:46:28 +08:00
|
|
|
}
|
|
|
|
|
2013-05-08 18:14:05 +08:00
|
|
|
/*
|
|
|
|
* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
|
|
|
|
* for DP the encoder type can be set by the caller to
|
|
|
|
* INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
|
|
|
|
*/
|
|
|
|
if (type == DRM_MODE_CONNECTOR_eDP)
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_EDP;
|
|
|
|
|
2013-05-08 18:14:08 +08:00
|
|
|
DRM_DEBUG_KMS("Adding %s connector on port %c\n",
|
|
|
|
type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
|
|
|
|
port_name(port));
|
|
|
|
|
2010-07-17 02:46:28 +08:00
|
|
|
drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
|
2009-04-08 07:16:42 +08:00
|
|
|
drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
|
|
|
|
|
|
|
|
connector->interlace_allowed = true;
|
|
|
|
connector->doublescan_allowed = 0;
|
|
|
|
|
2012-10-27 05:05:48 +08:00
|
|
|
INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
|
|
|
|
ironlake_panel_vdd_work);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-09-09 23:20:55 +08:00
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
2009-04-08 07:16:42 +08:00
|
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
|
2012-11-24 01:30:39 +08:00
|
|
|
if (HAS_DDI(dev))
|
2012-10-27 05:05:51 +08:00
|
|
|
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
|
|
|
|
else
|
|
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
|
|
|
|
2013-02-19 06:00:25 +08:00
|
|
|
intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
|
|
|
|
if (HAS_DDI(dev)) {
|
|
|
|
switch (intel_dig_port->port) {
|
|
|
|
case PORT_A:
|
|
|
|
intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
|
|
|
|
break;
|
|
|
|
case PORT_B:
|
|
|
|
intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
2012-07-01 19:05:48 +08:00
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/* Set up the DDC bus. */
|
2012-07-18 04:53:45 +08:00
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_A;
|
2012-07-18 04:53:45 +08:00
|
|
|
name = "DPDDC-A";
|
|
|
|
break;
|
|
|
|
case PORT_B:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_B;
|
2012-07-18 04:53:45 +08:00
|
|
|
name = "DPDDC-B";
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_C;
|
2012-07-18 04:53:45 +08:00
|
|
|
name = "DPDDC-C";
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_D;
|
2012-07-18 04:53:45 +08:00
|
|
|
name = "DPDDC-D";
|
|
|
|
break;
|
|
|
|
default:
|
2013-03-07 23:30:28 +08:00
|
|
|
BUG();
|
2009-07-24 01:00:31 +08:00
|
|
|
}
|
|
|
|
|
2012-10-21 02:57:45 +08:00
|
|
|
if (is_edp(intel_dp))
|
2013-01-16 16:53:40 +08:00
|
|
|
intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
|
2012-08-30 09:06:18 +08:00
|
|
|
|
|
|
|
intel_dp_i2c_init(intel_dp, intel_connector, name);
|
|
|
|
|
2012-10-21 02:57:45 +08:00
|
|
|
/* Cache DPCD and EDID for edp. */
|
2012-08-30 09:06:18 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
bool ret;
|
2012-10-19 19:51:48 +08:00
|
|
|
struct drm_display_mode *scan;
|
2012-08-30 09:06:18 +08:00
|
|
|
struct edid *edid;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
|
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
2011-07-26 11:01:56 +08:00
|
|
|
ret = intel_dp_get_dpcd(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
ironlake_edp_panel_vdd_off(intel_dp, false);
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2011-07-26 11:01:56 +08:00
|
|
|
if (ret) {
|
2011-07-08 02:10:58 +08:00
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
|
|
|
|
dev_priv->no_aux_handshake =
|
|
|
|
intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
|
2010-10-08 07:01:21 +08:00
|
|
|
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
|
|
|
|
} else {
|
2011-02-12 18:33:12 +08:00
|
|
|
/* if this fails, presume the device is a ghost */
|
2011-03-18 17:06:49 +08:00
|
|
|
DRM_INFO("failed to retrieve link info, disabling eDP\n");
|
2012-10-27 05:05:44 +08:00
|
|
|
intel_dp_encoder_destroy(&intel_encoder->base);
|
|
|
|
intel_dp_destroy(connector);
|
2011-02-12 18:33:12 +08:00
|
|
|
return;
|
2010-10-08 07:01:21 +08:00
|
|
|
}
|
|
|
|
|
2013-01-16 16:53:40 +08:00
|
|
|
/* We now know it's not a ghost, init power sequence regs. */
|
|
|
|
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
|
|
|
|
&power_seq);
|
|
|
|
|
2012-06-15 03:28:33 +08:00
|
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
|
|
|
edid = drm_get_edid(connector, &intel_dp->adapter);
|
|
|
|
if (edid) {
|
2012-10-19 19:51:52 +08:00
|
|
|
if (drm_add_edid_modes(connector, edid)) {
|
|
|
|
drm_mode_connector_update_edid_property(connector, edid);
|
|
|
|
drm_edid_to_eld(connector, edid);
|
|
|
|
} else {
|
|
|
|
kfree(edid);
|
|
|
|
edid = ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
edid = ERR_PTR(-ENOENT);
|
2012-06-15 03:28:33 +08:00
|
|
|
}
|
2012-10-19 19:51:52 +08:00
|
|
|
intel_connector->edid = edid;
|
2012-10-19 19:51:48 +08:00
|
|
|
|
|
|
|
/* prefer fixed mode from EDID if available */
|
|
|
|
list_for_each_entry(scan, &connector->probed_modes, head) {
|
|
|
|
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
|
|
|
|
fixed_mode = drm_mode_duplicate(dev, scan);
|
|
|
|
break;
|
|
|
|
}
|
2012-06-15 03:28:33 +08:00
|
|
|
}
|
2012-10-19 19:51:48 +08:00
|
|
|
|
|
|
|
/* fallback to VBT if available for eDP */
|
2013-05-10 07:03:18 +08:00
|
|
|
if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
|
|
|
|
fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
|
2012-10-19 19:51:48 +08:00
|
|
|
if (fixed_mode)
|
|
|
|
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
|
|
}
|
|
|
|
|
2012-06-15 03:28:33 +08:00
|
|
|
ironlake_edp_panel_vdd_off(intel_dp, false);
|
|
|
|
}
|
2011-09-29 07:31:53 +08:00
|
|
|
|
2010-10-08 07:01:07 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
2012-10-19 19:51:50 +08:00
|
|
|
intel_panel_init(&intel_connector->panel, fixed_mode);
|
2012-10-19 19:51:46 +08:00
|
|
|
intel_panel_setup_backlight(connector);
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
intel_dp_add_properties(intel_dp, connector);
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
|
|
* generated on the port when a cable is not attached.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev) && !IS_GM45(dev)) {
|
|
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
|
|
}
|
|
|
|
}
|
2012-10-27 05:05:48 +08:00
|
|
|
|
|
|
|
void
|
|
|
|
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
|
|
|
|
intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
|
|
|
|
if (!intel_dig_port)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
|
|
|
|
if (!intel_connector) {
|
|
|
|
kfree(intel_dig_port);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
encoder = &intel_encoder->base;
|
|
|
|
|
|
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS);
|
2012-10-27 05:05:52 +08:00
|
|
|
drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
|
2012-10-27 05:05:48 +08:00
|
|
|
|
2013-03-27 07:44:55 +08:00
|
|
|
intel_encoder->compute_config = intel_dp_compute_config;
|
2012-10-27 05:05:52 +08:00
|
|
|
intel_encoder->enable = intel_enable_dp;
|
|
|
|
intel_encoder->pre_enable = intel_pre_enable_dp;
|
|
|
|
intel_encoder->disable = intel_disable_dp;
|
|
|
|
intel_encoder->post_disable = intel_post_disable_dp;
|
|
|
|
intel_encoder->get_hw_state = intel_dp_get_hw_state;
|
2013-05-15 08:08:26 +08:00
|
|
|
intel_encoder->get_config = intel_dp_get_config;
|
2013-04-19 05:51:36 +08:00
|
|
|
if (IS_VALLEYVIEW(dev))
|
|
|
|
intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
|
2012-10-27 05:05:48 +08:00
|
|
|
|
2012-10-27 05:05:50 +08:00
|
|
|
intel_dig_port->port = port;
|
2012-10-27 05:05:48 +08:00
|
|
|
intel_dig_port->dp.output_reg = output_reg;
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
|
2012-10-27 05:05:48 +08:00
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
|
|
intel_encoder->cloneable = false;
|
|
|
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intel_encoder->hot_plug = intel_dp_hot_plug;
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intel_dp_init_connector(intel_dig_port, intel_connector);
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}
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