43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright: (C) 2002 Rory Bolt
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*/
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#ifndef __IOP32X_IRQS_H
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#define __IOP32X_IRQS_H
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/*
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* IOP80321 chipset interrupts
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*/
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#define IRQ_IOP32X_DMA0_EOT 0
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#define IRQ_IOP32X_DMA0_EOC 1
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#define IRQ_IOP32X_DMA1_EOT 2
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#define IRQ_IOP32X_DMA1_EOC 3
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#define IRQ_IOP32X_AA_EOT 6
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#define IRQ_IOP32X_AA_EOC 7
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#define IRQ_IOP32X_CORE_PMON 8
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#define IRQ_IOP32X_TIMER0 9
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#define IRQ_IOP32X_TIMER1 10
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#define IRQ_IOP32X_I2C_0 11
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#define IRQ_IOP32X_I2C_1 12
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#define IRQ_IOP32X_MESSAGING 13
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#define IRQ_IOP32X_ATU_BIST 14
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#define IRQ_IOP32X_PERFMON 15
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#define IRQ_IOP32X_CORE_PMU 16
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#define IRQ_IOP32X_BIU_ERR 17
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#define IRQ_IOP32X_ATU_ERR 18
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#define IRQ_IOP32X_MCU_ERR 19
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#define IRQ_IOP32X_DMA0_ERR 20
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#define IRQ_IOP32X_DMA1_ERR 21
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#define IRQ_IOP32X_AA_ERR 23
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#define IRQ_IOP32X_MSG_ERR 24
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#define IRQ_IOP32X_SSP 25
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#define IRQ_IOP32X_XINT0 27
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#define IRQ_IOP32X_XINT1 28
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#define IRQ_IOP32X_XINT2 29
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#define IRQ_IOP32X_XINT3 30
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#define IRQ_IOP32X_HPI 31
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#endif
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