2020-03-04 15:27:26 +08:00
|
|
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
|
|
# Copyright 2019 Unisoc Inc.
|
|
|
|
%YAML 1.2
|
|
|
|
---
|
|
|
|
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
|
|
|
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|
|
|
|
|
|
|
title: SC9863A Clock Control Unit Device Tree Bindings
|
|
|
|
|
|
|
|
maintainers:
|
|
|
|
- Orson Zhai <orsonzhai@gmail.com>
|
|
|
|
- Baolin Wang <baolin.wang7@gmail.com>
|
|
|
|
- Chunyan Zhang <zhang.lyra@gmail.com>
|
|
|
|
|
|
|
|
properties:
|
|
|
|
"#clock-cells":
|
|
|
|
const: 1
|
|
|
|
|
2020-04-21 10:24:47 +08:00
|
|
|
compatible:
|
2020-03-04 15:27:26 +08:00
|
|
|
enum:
|
|
|
|
- sprd,sc9863a-ap-clk
|
|
|
|
- sprd,sc9863a-aon-clk
|
|
|
|
- sprd,sc9863a-apahb-gate
|
|
|
|
- sprd,sc9863a-pmu-gate
|
|
|
|
- sprd,sc9863a-aonapb-gate
|
|
|
|
- sprd,sc9863a-pll
|
|
|
|
- sprd,sc9863a-mpll
|
|
|
|
- sprd,sc9863a-rpll
|
|
|
|
- sprd,sc9863a-dpll
|
|
|
|
- sprd,sc9863a-mm-gate
|
2020-05-27 13:36:36 +08:00
|
|
|
- sprd,sc9863a-mm-clk
|
2020-03-04 15:27:26 +08:00
|
|
|
- sprd,sc9863a-apapb-gate
|
|
|
|
|
|
|
|
clocks:
|
|
|
|
minItems: 1
|
|
|
|
maxItems: 4
|
|
|
|
description: |
|
|
|
|
The input parent clock(s) phandle for this clock, only list fixed
|
|
|
|
clocks which are declared in devicetree.
|
|
|
|
|
|
|
|
clock-names:
|
|
|
|
minItems: 1
|
|
|
|
items:
|
|
|
|
- const: ext-26m
|
|
|
|
- const: ext-32k
|
|
|
|
- const: ext-4m
|
|
|
|
- const: rco-100m
|
|
|
|
|
|
|
|
reg:
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
required:
|
|
|
|
- compatible
|
|
|
|
- '#clock-cells'
|
|
|
|
|
|
|
|
if:
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
enum:
|
|
|
|
- sprd,sc9863a-ap-clk
|
|
|
|
- sprd,sc9863a-aon-clk
|
|
|
|
then:
|
|
|
|
required:
|
|
|
|
- reg
|
|
|
|
|
|
|
|
else:
|
|
|
|
description: |
|
|
|
|
Other SC9863a clock nodes should be the child of a syscon node in
|
|
|
|
which compatible string shoule be:
|
|
|
|
"sprd,sc9863a-glbregs", "syscon", "simple-mfd"
|
|
|
|
|
|
|
|
The 'reg' property for the clock node is also required if there is a sub
|
|
|
|
range of registers for the clocks.
|
|
|
|
|
2020-10-03 07:41:43 +08:00
|
|
|
additionalProperties: false
|
|
|
|
|
2020-03-04 15:27:26 +08:00
|
|
|
examples:
|
|
|
|
- |
|
|
|
|
ap_clk: clock-controller@21500000 {
|
|
|
|
compatible = "sprd,sc9863a-ap-clk";
|
2020-05-13 04:45:43 +08:00
|
|
|
reg = <0x21500000 0x1000>;
|
2020-03-04 15:27:26 +08:00
|
|
|
clocks = <&ext_26m>, <&ext_32k>;
|
|
|
|
clock-names = "ext-26m", "ext-32k";
|
|
|
|
#clock-cells = <1>;
|
|
|
|
};
|
|
|
|
|
|
|
|
- |
|
2020-05-13 04:45:43 +08:00
|
|
|
syscon@20e00000 {
|
|
|
|
compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
|
|
|
|
reg = <0x20e00000 0x4000>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0x20e00000 0x4000>;
|
|
|
|
|
|
|
|
apahb_gate: apahb-gate@0 {
|
|
|
|
compatible = "sprd,sc9863a-apahb-gate";
|
|
|
|
reg = <0x0 0x1020>;
|
|
|
|
#clock-cells = <1>;
|
2020-03-04 15:27:26 +08:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
...
|