OpenCloudOS-Kernel/sound/firewire/fireface/ff-protocol-latter.c

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// SPDX-License-Identifier: GPL-2.0
// ff-protocol-latter - a part of driver for RME Fireface series
//
// Copyright (c) 2019 Takashi Sakamoto
//
// Licensed under the terms of the GNU General Public License, version 2.
#include <linux/delay.h>
#include "ff.h"
#define LATTER_STF 0xffff00000004
#define LATTER_ISOC_CHANNELS 0xffff00000008
#define LATTER_ISOC_START 0xffff0000000c
#define LATTER_FETCH_MODE 0xffff00000010
#define LATTER_SYNC_STATUS 0x0000801c0000
static int parse_clock_bits(u32 data, unsigned int *rate,
enum snd_ff_clock_src *src)
{
static const struct {
unsigned int rate;
u32 flag;
} *rate_entry, rate_entries[] = {
{ 32000, 0x00000000, },
{ 44100, 0x01000000, },
{ 48000, 0x02000000, },
{ 64000, 0x04000000, },
{ 88200, 0x05000000, },
{ 96000, 0x06000000, },
{ 128000, 0x08000000, },
{ 176400, 0x09000000, },
{ 192000, 0x0a000000, },
};
static const struct {
enum snd_ff_clock_src src;
u32 flag;
} *clk_entry, clk_entries[] = {
{ SND_FF_CLOCK_SRC_SPDIF, 0x00000200, },
{ SND_FF_CLOCK_SRC_ADAT1, 0x00000400, },
{ SND_FF_CLOCK_SRC_WORD, 0x00000600, },
{ SND_FF_CLOCK_SRC_INTERNAL, 0x00000e00, },
};
int i;
for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
rate_entry = rate_entries + i;
if ((data & 0x0f000000) == rate_entry->flag) {
*rate = rate_entry->rate;
break;
}
}
if (i == ARRAY_SIZE(rate_entries))
return -EIO;
for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
clk_entry = clk_entries + i;
if ((data & 0x000e00) == clk_entry->flag) {
*src = clk_entry->src;
break;
}
}
if (i == ARRAY_SIZE(clk_entries))
return -EIO;
return 0;
}
static int latter_get_clock(struct snd_ff *ff, unsigned int *rate,
enum snd_ff_clock_src *src)
{
__le32 reg;
u32 data;
int err;
err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
LATTER_SYNC_STATUS, &reg, sizeof(reg), 0);
if (err < 0)
return err;
data = le32_to_cpu(reg);
return parse_clock_bits(data, rate, src);
}
static int latter_switch_fetching_mode(struct snd_ff *ff, bool enable)
{
u32 data;
__le32 reg;
if (enable)
data = 0x00000000;
else
data = 0xffffffff;
reg = cpu_to_le32(data);
return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
LATTER_FETCH_MODE, &reg, sizeof(reg), 0);
}
static int keep_resources(struct snd_ff *ff, unsigned int rate)
{
enum snd_ff_stream_mode mode;
int i;
int err;
// Check whether the given value is supported or not.
for (i = 0; i < CIP_SFC_COUNT; i++) {
if (amdtp_rate_table[i] == rate)
break;
}
if (i >= CIP_SFC_COUNT)
return -EINVAL;
err = snd_ff_stream_get_multiplier_mode(i, &mode);
if (err < 0)
return err;
/* Keep resources for in-stream. */
ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
err = fw_iso_resources_allocate(&ff->tx_resources,
amdtp_stream_get_max_payload(&ff->tx_stream),
fw_parent_device(ff->unit)->max_speed);
if (err < 0)
return err;
/* Keep resources for out-stream. */
ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
err = fw_iso_resources_allocate(&ff->rx_resources,
amdtp_stream_get_max_payload(&ff->rx_stream),
fw_parent_device(ff->unit)->max_speed);
if (err < 0)
fw_iso_resources_free(&ff->tx_resources);
return err;
}
static int latter_begin_session(struct snd_ff *ff, unsigned int rate)
{
static const struct {
unsigned int stf;
unsigned int code;
unsigned int flag;
} *entry, rate_table[] = {
{ 32000, 0x00, 0x92, },
{ 44100, 0x02, 0x92, },
{ 48000, 0x04, 0x92, },
{ 64000, 0x08, 0x8e, },
{ 88200, 0x0a, 0x8e, },
{ 96000, 0x0c, 0x8e, },
{ 128000, 0x10, 0x8c, },
{ 176400, 0x12, 0x8c, },
{ 192000, 0x14, 0x8c, },
};
u32 data;
__le32 reg;
unsigned int count;
int i;
int err;
for (i = 0; i < ARRAY_SIZE(rate_table); ++i) {
entry = rate_table + i;
if (entry->stf == rate)
break;
}
if (i == ARRAY_SIZE(rate_table))
return -EINVAL;
reg = cpu_to_le32(entry->code);
err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
LATTER_STF, &reg, sizeof(reg), 0);
if (err < 0)
return err;
// Confirm to shift transmission clock.
count = 0;
while (count++ < 10) {
unsigned int curr_rate;
enum snd_ff_clock_src src;
err = latter_get_clock(ff, &curr_rate, &src);
if (err < 0)
return err;
if (curr_rate == rate)
break;
}
if (count == 10)
return -ETIMEDOUT;
err = keep_resources(ff, rate);
if (err < 0)
return err;
data = (ff->tx_resources.channel << 8) | ff->rx_resources.channel;
reg = cpu_to_le32(data);
err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
LATTER_ISOC_CHANNELS, &reg, sizeof(reg), 0);
if (err < 0)
return err;
// Always use the maximum number of data channels in data block of
// packet.
reg = cpu_to_le32(entry->flag);
return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
LATTER_ISOC_START, &reg, sizeof(reg), 0);
}
static void latter_finish_session(struct snd_ff *ff)
{
__le32 reg;
reg = cpu_to_le32(0x00000000);
snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
LATTER_ISOC_START, &reg, sizeof(reg), 0);
}
static void latter_dump_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
{
static const struct {
char *const label;
u32 locked_mask;
u32 synced_mask;
} *clk_entry, clk_entries[] = {
{ "S/PDIF", 0x00000001, 0x00000010, },
{ "ADAT", 0x00000002, 0x00000020, },
{ "WDClk", 0x00000004, 0x00000040, },
};
__le32 reg;
u32 data;
unsigned int rate;
enum snd_ff_clock_src src;
const char *label;
int i;
int err;
err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
LATTER_SYNC_STATUS, &reg, sizeof(reg), 0);
if (err < 0)
return;
data = le32_to_cpu(reg);
snd_iprintf(buffer, "External source detection:\n");
for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
clk_entry = clk_entries + i;
snd_iprintf(buffer, "%s: ", clk_entry->label);
if (data & clk_entry->locked_mask) {
if (data & clk_entry->synced_mask)
snd_iprintf(buffer, "sync\n");
else
snd_iprintf(buffer, "lock\n");
} else {
snd_iprintf(buffer, "none\n");
}
}
err = parse_clock_bits(data, &rate, &src);
if (err < 0)
return;
label = snd_ff_proc_get_clk_label(src);
if (!label)
return;
snd_iprintf(buffer, "Referred clock: %s %d\n", label, rate);
}
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 21:17:02 +08:00
// NOTE: transactions are transferred within 0x00-0x7f in allocated range of
// address. This seems to be for check of discontinuity in receiver side.
static void latter_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
__le32 *buf, size_t length)
{
u32 data = le32_to_cpu(*buf);
unsigned int index = (data & 0x000000f0) >> 4;
u8 byte[3];
struct snd_rawmidi_substream *substream;
unsigned int len;
if (index > ff->spec->midi_in_ports)
return;
switch (data & 0x0000000f) {
case 0x00000008:
case 0x00000009:
case 0x0000000a:
case 0x0000000b:
case 0x0000000e:
len = 3;
break;
case 0x0000000c:
case 0x0000000d:
len = 2;
break;
default:
len = data & 0x00000003;
if (len == 0)
len = 3;
break;
}
byte[0] = (data & 0x0000ff00) >> 8;
byte[1] = (data & 0x00ff0000) >> 16;
byte[2] = (data & 0xff000000) >> 24;
substream = READ_ONCE(ff->tx_midi_substreams[index]);
if (substream)
snd_rawmidi_receive(substream, byte, len);
}
const struct snd_ff_protocol snd_ff_protocol_latter = {
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 21:17:02 +08:00
.handle_midi_msg = latter_handle_midi_msg,
.get_clock = latter_get_clock,
.switch_fetching_mode = latter_switch_fetching_mode,
.begin_session = latter_begin_session,
.finish_session = latter_finish_session,
.dump_status = latter_dump_status,
};