2005-04-17 06:20:36 +08:00
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/*
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* PCI Express Hot Plug Controller Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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2005-08-17 06:16:10 +08:00
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* Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
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2005-04-17 06:20:36 +08:00
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*
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*/
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#ifndef _PCIEHP_H
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#define _PCIEHP_H
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#include <linux/types.h>
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#include <linux/pci.h>
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2006-10-14 11:05:19 +08:00
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#include <linux/pci_hotplug.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/delay.h>
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2006-01-08 17:02:05 +08:00
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#include <linux/sched.h> /* signal_pending() */
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2005-04-17 06:20:36 +08:00
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#include <linux/pcieport_if.h>
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2006-01-13 23:02:15 +08:00
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#include <linux/mutex.h>
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2005-04-17 06:20:36 +08:00
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#define MY_NAME "pciehp"
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extern int pciehp_poll_mode;
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extern int pciehp_poll_time;
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extern int pciehp_debug;
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2005-11-01 08:20:12 +08:00
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extern int pciehp_force;
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2007-03-07 07:02:26 +08:00
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extern struct workqueue_struct *pciehp_wq;
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2005-04-17 06:20:36 +08:00
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2006-12-22 09:01:07 +08:00
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#define dbg(format, arg...) \
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2009-02-06 17:23:36 +08:00
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do { \
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if (pciehp_debug) \
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printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \
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} while (0)
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2006-12-22 09:01:07 +08:00
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#define err(format, arg...) \
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printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
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#define info(format, arg...) \
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printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
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#define warn(format, arg...) \
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printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
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2005-04-17 06:20:36 +08:00
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2008-09-05 11:11:26 +08:00
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#define ctrl_dbg(ctrl, format, arg...) \
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do { \
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if (pciehp_debug) \
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2009-02-06 17:23:36 +08:00
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dev_printk(KERN_DEBUG, &ctrl->pcie->device, \
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2008-09-05 11:11:26 +08:00
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format, ## arg); \
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} while (0)
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#define ctrl_err(ctrl, format, arg...) \
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dev_err(&ctrl->pcie->device, format, ## arg)
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#define ctrl_info(ctrl, format, arg...) \
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dev_info(&ctrl->pcie->device, format, ## arg)
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#define ctrl_warn(ctrl, format, arg...) \
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dev_warn(&ctrl->pcie->device, format, ## arg)
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2006-12-22 09:01:02 +08:00
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#define SLOT_NAME_SIZE 10
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2005-04-17 06:20:36 +08:00
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struct slot {
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u8 state;
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struct controller *ctrl;
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struct hotplug_slot *hotplug_slot;
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2007-03-07 07:02:26 +08:00
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struct delayed_work work; /* work for button event */
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struct mutex lock;
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2005-04-17 06:20:36 +08:00
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};
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struct event_info {
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u32 event_type;
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2007-03-07 07:02:26 +08:00
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struct slot *p_slot;
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struct work_struct work;
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2005-04-17 06:20:36 +08:00
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};
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struct controller {
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2006-09-23 01:17:29 +08:00
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struct mutex ctrl_lock; /* controller lock */
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2008-08-22 16:16:48 +08:00
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struct pcie_device *pcie; /* PCI Express port service */
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2009-09-15 16:24:46 +08:00
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struct slot *slot;
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2005-04-17 06:20:36 +08:00
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wait_queue_head_t queue; /* sleep & wake process */
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2008-04-26 05:39:06 +08:00
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u32 slot_cap;
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2005-05-07 08:19:09 +08:00
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u8 cap_base;
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2006-12-22 09:01:04 +08:00
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struct timer_list poll_timer;
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2009-02-03 14:06:18 +08:00
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unsigned int cmd_busy:1;
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pciehp: fix slow probing
Fix the "pciehp probing slow" problem reported from Jan C. Nordholz in
http://bugzilla.kernel.org/show_bug.cgi?id=10751.
The command completed bit in Slot Status register applies only to
commands issued to control the attention indicator, power indicator,
power controller, or electromechanical interlock. However, writes to
other parts of the Slot Control register would end up writing to the
control fields. Hence, any write to Slot Control register is
considered as a command. However, if the controller doesn't support
any of attention indicator, power indicator, power controller and
electromechanical interlock, command completed bit would not set in
writing to Slot Control register. In this case, we should not wait for
command completed bit set, otherwise all commands would be considered
not completed in timeout seconds (1 sec.).
The cause of the problem is pciehp driver didn't take this situation
into account. This patch changes pciehp to take it into account. This
patch also add the check for "No Command Completed Support" bit in
Slot Capability register. If it is set, we should not wait for command
completed bit set as well.
This problem seems to be revealed by the commit
c27fb883dffe11aa4cb35ecea1fa1832ba45d4da that fixed the bug that
pciehp did not wait for command completed properly (pciehp just
ignored the command completion event).
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27 18:04:30 +08:00
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unsigned int no_cmd_complete:1;
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2008-10-22 13:31:44 +08:00
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unsigned int link_active_reporting:1;
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2009-01-29 11:31:18 +08:00
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unsigned int notification_enabled:1;
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2009-02-03 14:06:16 +08:00
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unsigned int power_fault_detected;
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2005-04-17 06:20:36 +08:00
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};
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#define INT_BUTTON_IGNORE 0
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#define INT_PRESENCE_ON 1
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#define INT_PRESENCE_OFF 2
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#define INT_SWITCH_CLOSE 3
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#define INT_SWITCH_OPEN 4
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#define INT_POWER_FAULT 5
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#define INT_POWER_FAULT_CLEAR 6
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#define INT_BUTTON_PRESS 7
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#define INT_BUTTON_RELEASE 8
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#define INT_BUTTON_CANCEL 9
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#define STATIC_STATE 0
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#define BLINKINGON_STATE 1
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#define BLINKINGOFF_STATE 2
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#define POWERON_STATE 3
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#define POWEROFF_STATE 4
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2009-09-15 16:34:05 +08:00
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#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
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#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
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#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
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#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
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#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
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#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
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#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
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#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
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2009-09-15 16:28:53 +08:00
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#define PSN(ctrl) ((ctrl)->slot_cap >> 19)
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2005-04-17 06:20:36 +08:00
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2007-03-07 07:02:26 +08:00
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extern int pciehp_sysfs_enable_slot(struct slot *slot);
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extern int pciehp_sysfs_disable_slot(struct slot *slot);
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2008-05-27 18:03:16 +08:00
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extern u8 pciehp_handle_attention_button(struct slot *p_slot);
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2009-09-15 16:30:48 +08:00
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extern u8 pciehp_handle_switch_change(struct slot *p_slot);
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2008-05-27 18:03:16 +08:00
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extern u8 pciehp_handle_presence_change(struct slot *p_slot);
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extern u8 pciehp_handle_power_fault(struct slot *p_slot);
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2006-12-22 09:01:07 +08:00
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extern int pciehp_configure_device(struct slot *p_slot);
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extern int pciehp_unconfigure_device(struct slot *p_slot);
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2007-03-22 02:45:31 +08:00
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extern void pciehp_queue_pushbutton_work(struct work_struct *work);
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2008-06-20 11:07:08 +08:00
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struct controller *pcie_init(struct pcie_device *dev);
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2009-01-29 11:31:18 +08:00
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int pcie_init_notification(struct controller *ctrl);
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2007-11-29 07:11:28 +08:00
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int pciehp_enable_slot(struct slot *p_slot);
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2007-11-29 07:12:00 +08:00
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int pciehp_disable_slot(struct slot *p_slot);
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2008-06-20 11:07:08 +08:00
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int pcie_enable_notification(struct controller *ctrl);
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2009-09-15 16:30:48 +08:00
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int pciehp_power_on_slot(struct slot *slot);
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int pciehp_power_off_slot(struct slot *slot);
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int pciehp_get_power_status(struct slot *slot, u8 *status);
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int pciehp_get_attention_status(struct slot *slot, u8 *status);
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int pciehp_set_attention_status(struct slot *slot, u8 status);
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int pciehp_get_latch_status(struct slot *slot, u8 *status);
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int pciehp_get_adapter_status(struct slot *slot, u8 *status);
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int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *speed);
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int pciehp_get_max_link_width(struct slot *slot, enum pcie_link_width *val);
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int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *speed);
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int pciehp_get_cur_link_width(struct slot *slot, enum pcie_link_width *val);
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int pciehp_query_power_fault(struct slot *slot);
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void pciehp_green_led_on(struct slot *slot);
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void pciehp_green_led_off(struct slot *slot);
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void pciehp_green_led_blink(struct slot *slot);
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int pciehp_check_link_status(struct controller *ctrl);
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void pciehp_release_ctrl(struct controller *ctrl);
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2005-04-17 06:20:36 +08:00
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2008-10-21 07:41:38 +08:00
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static inline const char *slot_name(struct slot *slot)
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{
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return hotplug_slot_name(slot->hotplug_slot);
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}
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2006-03-04 02:16:05 +08:00
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#ifdef CONFIG_ACPI
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2006-08-08 21:44:26 +08:00
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#include <acpi/acpi.h>
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#include <acpi/acpi_bus.h>
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#include <linux/pci-acpi.h>
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2008-12-17 11:07:38 +08:00
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extern void __init pciehp_acpi_slot_detection_init(void);
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extern int pciehp_acpi_slot_detection_check(struct pci_dev *dev);
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static inline void pciehp_firmware_init(void)
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{
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pciehp_acpi_slot_detection_init();
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}
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2008-05-28 14:01:03 +08:00
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static inline int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev)
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{
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2008-12-17 11:07:38 +08:00
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int retval;
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2008-05-28 14:01:03 +08:00
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u32 flags = (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |
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OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
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2008-12-17 11:07:38 +08:00
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retval = acpi_get_hp_hw_control_from_firmware(dev, flags);
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if (retval)
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return retval;
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return pciehp_acpi_slot_detection_check(dev);
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2008-05-28 14:01:03 +08:00
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}
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2006-03-04 02:16:05 +08:00
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#else
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2008-12-17 11:07:38 +08:00
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#define pciehp_firmware_init() do {} while (0)
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2006-03-04 02:16:05 +08:00
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#define pciehp_get_hp_hw_control_from_firmware(dev) 0
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#endif /* CONFIG_ACPI */
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2005-04-17 06:20:36 +08:00
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#endif /* _PCIEHP_H */
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