2015-07-18 00:33:44 +08:00
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i synthesize instructions events
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2020-05-30 20:24:41 +08:00
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b synthesize branches events (branch misses for Arm SPE)
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2015-07-18 00:33:44 +08:00
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c synthesize branches events (calls only)
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r synthesize branches events (returns only)
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x synthesize transactions events
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2017-05-26 16:17:24 +08:00
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w synthesize ptwrite events
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2021-02-06 01:53:50 +08:00
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p synthesize power events (incl. PSB events for Intel PT)
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2019-08-06 16:46:03 +08:00
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o synthesize other events recorded due to the use
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of aux-output (refer to perf record)
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2015-07-18 00:33:44 +08:00
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e synthesize error events
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d create a debug log
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2020-05-30 20:24:41 +08:00
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f synthesize first level cache events
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m synthesize last level cache events
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2020-11-06 17:48:50 +08:00
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M synthesize memory events
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2020-05-30 20:24:41 +08:00
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t synthesize TLB events
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a synthesize remote access events
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2015-07-18 00:33:44 +08:00
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g synthesize a call chain (use with i or x)
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2020-04-01 18:16:05 +08:00
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G synthesize a call chain on existing event records
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2015-09-25 21:15:39 +08:00
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l synthesize last branch entries (use with i or x)
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2020-04-29 23:07:46 +08:00
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L synthesize last branch entries on existing event records
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2016-03-29 01:45:38 +08:00
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s skip initial number of events
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2020-07-10 23:11:02 +08:00
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q quicker (less detailed) decoding
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2021-04-30 15:02:58 +08:00
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Z prefer to ignore timestamps (so-called "timeless" decoding)
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2015-07-18 00:33:44 +08:00
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2018-09-21 02:05:37 +08:00
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The default is all events i.e. the same as --itrace=ibxwpe,
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except for perf script where it is --itrace=ce
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2015-07-18 00:33:44 +08:00
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2018-09-21 02:05:37 +08:00
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In addition, the period (default 100000, except for perf script where it is 1)
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for instructions events can be specified in units of:
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2015-07-18 00:33:44 +08:00
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i instructions
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t ticks
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ms milliseconds
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us microseconds
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ns nanoseconds (default)
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Also the call chain size (default 16, max. 1024) for instructions or
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transactions events can be specified.
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2015-09-25 21:15:39 +08:00
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Also the number of last branch entries (default 64, max. 1024) for
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instructions or transactions events can be specified.
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2016-03-29 01:45:38 +08:00
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2020-04-29 23:07:50 +08:00
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Similar to options g and l, size may also be specified for options G and L.
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On x86, note that G and L work poorly when data has been recorded with
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large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
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2017-05-26 16:17:24 +08:00
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It is also possible to skip events generated (instructions, branches, transactions,
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2017-05-26 16:17:25 +08:00
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ptwrite, power) at the beginning. This is useful to ignore initialization code.
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2016-03-29 01:45:38 +08:00
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--itrace=i0nss1000000
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skips the first million instructions.
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2020-07-10 23:10:57 +08:00
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The 'e' option may be followed by flags which affect what errors will or
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will not be reported. Each flag must be preceded by either '+' or '-'.
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The flags are:
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o overflow
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l trace data lost
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2020-07-10 23:10:59 +08:00
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If supported, the 'd' option may be followed by flags which affect what
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debug messages will or will not be logged. Each flag must be preceded
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by either '+' or '-'. The flags are:
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a all perf events
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2020-07-10 23:11:02 +08:00
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If supported, the 'q' option may be repeated to increase the effect.
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