2019-07-25 01:16:09 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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2020-06-25 01:07:49 +08:00
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* Ingenic SoCs TCU IRQ driver
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2019-07-25 01:16:09 +08:00
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* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
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2020-06-25 01:07:49 +08:00
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* Copyright (C) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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2019-07-25 01:16:09 +08:00
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/ingenic-tcu.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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2020-06-25 01:07:49 +08:00
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#include <linux/overflow.h>
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2019-07-25 01:16:09 +08:00
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sched_clock.h>
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#include <dt-bindings/clock/ingenic,tcu.h>
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2020-06-25 01:07:49 +08:00
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static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd);
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2019-07-25 01:16:09 +08:00
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struct ingenic_soc_info {
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unsigned int num_channels;
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};
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu_timer {
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unsigned int cpu;
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unsigned int channel;
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struct clock_event_device cevt;
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struct clk *clk;
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char name[8];
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};
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2019-07-25 01:16:09 +08:00
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struct ingenic_tcu {
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struct regmap *map;
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2020-06-25 01:07:49 +08:00
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struct device_node *np;
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struct clk *cs_clk;
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unsigned int cs_channel;
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2019-07-25 01:16:09 +08:00
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struct clocksource cs;
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unsigned long pwm_channels_mask;
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu_timer timers[];
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2019-07-25 01:16:09 +08:00
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};
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static struct ingenic_tcu *ingenic_tcu;
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static u64 notrace ingenic_tcu_timer_read(void)
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{
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struct ingenic_tcu *tcu = ingenic_tcu;
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unsigned int count;
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regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);
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return count;
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}
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static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
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{
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return ingenic_tcu_timer_read();
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}
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2020-06-25 01:07:49 +08:00
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static inline struct ingenic_tcu *
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to_ingenic_tcu(struct ingenic_tcu_timer *timer)
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{
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return container_of(timer, struct ingenic_tcu, timers[timer->cpu]);
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}
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static inline struct ingenic_tcu_timer *
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to_ingenic_tcu_timer(struct clock_event_device *evt)
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2019-07-25 01:16:09 +08:00
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{
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2020-06-25 01:07:49 +08:00
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return container_of(evt, struct ingenic_tcu_timer, cevt);
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2019-07-25 01:16:09 +08:00
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}
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static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
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{
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
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struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
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2019-07-25 01:16:09 +08:00
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2020-06-25 01:07:49 +08:00
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regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
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2019-07-25 01:16:09 +08:00
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return 0;
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}
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static int ingenic_tcu_cevt_set_next(unsigned long next,
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struct clock_event_device *evt)
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{
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
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struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
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2019-07-25 01:16:09 +08:00
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if (next > 0xffff)
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return -EINVAL;
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2020-06-25 01:07:49 +08:00
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regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next);
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regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0);
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regmap_write(tcu->map, TCU_REG_TESR, BIT(timer->channel));
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2019-07-25 01:16:09 +08:00
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return 0;
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}
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2020-06-25 01:07:49 +08:00
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static void ingenic_per_cpu_event_handler(void *info)
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{
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struct clock_event_device *cevt = (struct clock_event_device *) info;
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cevt->event_handler(cevt);
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}
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2019-07-25 01:16:09 +08:00
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static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
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{
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu_timer *timer = dev_id;
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struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
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call_single_data_t *csd;
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2019-07-25 01:16:09 +08:00
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2020-06-25 01:07:49 +08:00
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regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
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2019-07-25 01:16:09 +08:00
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2020-06-25 01:07:49 +08:00
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if (timer->cevt.event_handler) {
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csd = &per_cpu(ingenic_cevt_csd, timer->cpu);
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csd->info = (void *) &timer->cevt;
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csd->func = ingenic_per_cpu_event_handler;
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smp_call_function_single_async(timer->cpu, csd);
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}
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2019-07-25 01:16:09 +08:00
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return IRQ_HANDLED;
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}
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static struct clk * __init ingenic_tcu_get_clock(struct device_node *np, int id)
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{
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struct of_phandle_args args;
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args.np = np;
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args.args_count = 1;
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args.args[0] = id;
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return of_clk_get_from_provider(&args);
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}
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2020-06-25 01:07:49 +08:00
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static int ingenic_tcu_setup_cevt(unsigned int cpu)
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2019-07-25 01:16:09 +08:00
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{
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu *tcu = ingenic_tcu;
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struct ingenic_tcu_timer *timer = &tcu->timers[cpu];
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unsigned int timer_virq;
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2019-07-25 01:16:09 +08:00
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struct irq_domain *domain;
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unsigned long rate;
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int err;
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2020-06-25 01:07:49 +08:00
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timer->clk = ingenic_tcu_get_clock(tcu->np, timer->channel);
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if (IS_ERR(timer->clk))
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return PTR_ERR(timer->clk);
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2019-07-25 01:16:09 +08:00
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2020-06-25 01:07:49 +08:00
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err = clk_prepare_enable(timer->clk);
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2019-07-25 01:16:09 +08:00
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if (err)
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goto err_clk_put;
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2020-06-25 01:07:49 +08:00
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rate = clk_get_rate(timer->clk);
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2019-07-25 01:16:09 +08:00
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if (!rate) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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2020-06-25 01:07:49 +08:00
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domain = irq_find_host(tcu->np);
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2019-07-25 01:16:09 +08:00
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if (!domain) {
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err = -ENODEV;
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goto err_clk_disable;
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}
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2020-06-25 01:07:49 +08:00
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timer_virq = irq_create_mapping(domain, timer->channel);
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2019-07-25 01:16:09 +08:00
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if (!timer_virq) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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2020-06-25 01:07:49 +08:00
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snprintf(timer->name, sizeof(timer->name), "TCU%u", timer->channel);
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2019-07-25 01:16:09 +08:00
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err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
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2020-06-25 01:07:49 +08:00
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timer->name, timer);
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2019-07-25 01:16:09 +08:00
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if (err)
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goto err_irq_dispose_mapping;
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2020-06-25 01:07:49 +08:00
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timer->cpu = smp_processor_id();
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timer->cevt.cpumask = cpumask_of(smp_processor_id());
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timer->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
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timer->cevt.name = timer->name;
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timer->cevt.rating = 200;
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timer->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
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timer->cevt.set_next_event = ingenic_tcu_cevt_set_next;
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2019-07-25 01:16:09 +08:00
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2020-06-25 01:07:49 +08:00
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clockevents_config_and_register(&timer->cevt, rate, 10, 0xffff);
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2019-07-25 01:16:09 +08:00
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return 0;
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err_irq_dispose_mapping:
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irq_dispose_mapping(timer_virq);
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err_clk_disable:
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2020-06-25 01:07:49 +08:00
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clk_disable_unprepare(timer->clk);
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2019-07-25 01:16:09 +08:00
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err_clk_put:
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2020-06-25 01:07:49 +08:00
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clk_put(timer->clk);
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2019-07-25 01:16:09 +08:00
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return err;
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}
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static int __init ingenic_tcu_clocksource_init(struct device_node *np,
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struct ingenic_tcu *tcu)
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{
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unsigned int channel = tcu->cs_channel;
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struct clocksource *cs = &tcu->cs;
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unsigned long rate;
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int err;
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tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
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if (IS_ERR(tcu->cs_clk))
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return PTR_ERR(tcu->cs_clk);
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err = clk_prepare_enable(tcu->cs_clk);
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if (err)
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goto err_clk_put;
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rate = clk_get_rate(tcu->cs_clk);
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if (!rate) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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/* Reset channel */
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regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
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0xffff & ~TCU_TCSR_RESERVED_BITS, 0);
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/* Reset counter */
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regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
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regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
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/* Enable channel */
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regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
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cs->name = "ingenic-timer";
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cs->rating = 200;
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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cs->mask = CLOCKSOURCE_MASK(16);
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cs->read = ingenic_tcu_timer_cs_read;
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err = clocksource_register_hz(cs, rate);
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if (err)
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goto err_clk_disable;
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return 0;
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err_clk_disable:
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clk_disable_unprepare(tcu->cs_clk);
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err_clk_put:
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clk_put(tcu->cs_clk);
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return err;
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}
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static const struct ingenic_soc_info jz4740_soc_info = {
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.num_channels = 8,
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};
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static const struct ingenic_soc_info jz4725b_soc_info = {
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.num_channels = 6,
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};
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static const struct of_device_id ingenic_tcu_of_match[] = {
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{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
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{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
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{ .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
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2020-02-19 16:29:33 +08:00
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{ .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, },
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2019-07-25 01:16:09 +08:00
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{ /* sentinel */ }
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};
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static int __init ingenic_tcu_init(struct device_node *np)
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{
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const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
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const struct ingenic_soc_info *soc_info = id->data;
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2020-06-25 01:07:49 +08:00
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struct ingenic_tcu_timer *timer;
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2019-07-25 01:16:09 +08:00
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struct ingenic_tcu *tcu;
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struct regmap *map;
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2020-06-25 01:07:49 +08:00
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unsigned int cpu;
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int ret, last_bit = -1;
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2019-07-25 01:16:09 +08:00
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long rate;
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of_node_clear_flag(np, OF_POPULATED);
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map = device_node_to_regmap(np);
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if (IS_ERR(map))
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return PTR_ERR(map);
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|
2020-06-25 01:07:49 +08:00
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tcu = kzalloc(struct_size(tcu, timers, num_possible_cpus()),
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GFP_KERNEL);
|
2019-07-25 01:16:09 +08:00
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if (!tcu)
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return -ENOMEM;
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2020-06-25 01:07:49 +08:00
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/*
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* Enable all TCU channels for PWM use by default except channels 0/1,
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* and channel 2 if target CPU is JZ4780/X2000 and SMP is selected.
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*/
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tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1,
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num_possible_cpus() + 1);
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2019-07-25 01:16:09 +08:00
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of_property_read_u32(np, "ingenic,pwm-channels-mask",
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(u32 *)&tcu->pwm_channels_mask);
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2020-06-25 01:07:49 +08:00
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/* Verify that we have at least num_possible_cpus() + 1 free channels */
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if (hweight8(tcu->pwm_channels_mask) >
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soc_info->num_channels - num_possible_cpus() + 1) {
|
2019-07-25 01:16:09 +08:00
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pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
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tcu->pwm_channels_mask);
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ret = -EINVAL;
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goto err_free_ingenic_tcu;
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}
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tcu->map = map;
|
2020-06-25 01:07:49 +08:00
|
|
|
tcu->np = np;
|
2019-07-25 01:16:09 +08:00
|
|
|
ingenic_tcu = tcu;
|
|
|
|
|
2020-06-25 01:07:49 +08:00
|
|
|
for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
|
|
|
|
timer = &tcu->timers[cpu];
|
|
|
|
|
|
|
|
timer->cpu = cpu;
|
|
|
|
timer->channel = find_next_zero_bit(&tcu->pwm_channels_mask,
|
|
|
|
soc_info->num_channels,
|
|
|
|
last_bit + 1);
|
|
|
|
last_bit = timer->channel;
|
|
|
|
}
|
|
|
|
|
2019-07-25 01:16:09 +08:00
|
|
|
tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
|
|
|
|
soc_info->num_channels,
|
2020-06-25 01:07:49 +08:00
|
|
|
last_bit + 1);
|
2019-07-25 01:16:09 +08:00
|
|
|
|
|
|
|
ret = ingenic_tcu_clocksource_init(np, tcu);
|
|
|
|
if (ret) {
|
|
|
|
pr_crit("%s: Unable to init clocksource: %d\n", __func__, ret);
|
|
|
|
goto err_free_ingenic_tcu;
|
|
|
|
}
|
|
|
|
|
2020-06-25 01:07:49 +08:00
|
|
|
/* Setup clock events on each CPU core */
|
|
|
|
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online",
|
|
|
|
ingenic_tcu_setup_cevt, NULL);
|
|
|
|
if (ret < 0) {
|
|
|
|
pr_crit("%s: Unable to start CPU timers: %d\n", __func__, ret);
|
2019-07-25 01:16:09 +08:00
|
|
|
goto err_tcu_clocksource_cleanup;
|
2020-06-25 01:07:49 +08:00
|
|
|
}
|
2019-07-25 01:16:09 +08:00
|
|
|
|
|
|
|
/* Register the sched_clock at the end as there's no way to undo it */
|
|
|
|
rate = clk_get_rate(tcu->cs_clk);
|
|
|
|
sched_clock_register(ingenic_tcu_timer_read, 16, rate);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_tcu_clocksource_cleanup:
|
|
|
|
clocksource_unregister(&tcu->cs);
|
|
|
|
clk_disable_unprepare(tcu->cs_clk);
|
|
|
|
clk_put(tcu->cs_clk);
|
|
|
|
err_free_ingenic_tcu:
|
|
|
|
kfree(tcu);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
TIMER_OF_DECLARE(jz4740_tcu_intc, "ingenic,jz4740-tcu", ingenic_tcu_init);
|
|
|
|
TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
|
|
|
|
TIMER_OF_DECLARE(jz4770_tcu_intc, "ingenic,jz4770-tcu", ingenic_tcu_init);
|
2020-02-19 16:29:33 +08:00
|
|
|
TIMER_OF_DECLARE(x1000_tcu_intc, "ingenic,x1000-tcu", ingenic_tcu_init);
|
2019-07-25 01:16:09 +08:00
|
|
|
|
|
|
|
static int __init ingenic_tcu_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
platform_set_drvdata(pdev, ingenic_tcu);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __maybe_unused ingenic_tcu_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ingenic_tcu *tcu = dev_get_drvdata(dev);
|
2020-06-25 01:07:49 +08:00
|
|
|
unsigned int cpu;
|
2019-07-25 01:16:09 +08:00
|
|
|
|
|
|
|
clk_disable(tcu->cs_clk);
|
2020-06-25 01:07:49 +08:00
|
|
|
|
|
|
|
for (cpu = 0; cpu < num_online_cpus(); cpu++)
|
|
|
|
clk_disable(tcu->timers[cpu].clk);
|
|
|
|
|
2019-07-25 01:16:09 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __maybe_unused ingenic_tcu_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ingenic_tcu *tcu = dev_get_drvdata(dev);
|
2020-06-25 01:07:49 +08:00
|
|
|
unsigned int cpu;
|
2019-07-25 01:16:09 +08:00
|
|
|
int ret;
|
|
|
|
|
2020-06-25 01:07:49 +08:00
|
|
|
for (cpu = 0; cpu < num_online_cpus(); cpu++) {
|
|
|
|
ret = clk_enable(tcu->timers[cpu].clk);
|
|
|
|
if (ret)
|
|
|
|
goto err_timer_clk_disable;
|
|
|
|
}
|
2019-07-25 01:16:09 +08:00
|
|
|
|
|
|
|
ret = clk_enable(tcu->cs_clk);
|
2020-06-25 01:07:49 +08:00
|
|
|
if (ret)
|
|
|
|
goto err_timer_clk_disable;
|
2019-07-25 01:16:09 +08:00
|
|
|
|
|
|
|
return 0;
|
2020-06-25 01:07:49 +08:00
|
|
|
|
|
|
|
err_timer_clk_disable:
|
|
|
|
for (; cpu > 0; cpu--)
|
|
|
|
clk_disable(tcu->timers[cpu - 1].clk);
|
|
|
|
return ret;
|
2019-07-25 01:16:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops __maybe_unused ingenic_tcu_pm_ops = {
|
|
|
|
/* _noirq: We want the TCU clocks to be gated last / ungated first */
|
|
|
|
.suspend_noirq = ingenic_tcu_suspend,
|
|
|
|
.resume_noirq = ingenic_tcu_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver ingenic_tcu_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "ingenic-tcu-timer",
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
.pm = &ingenic_tcu_pm_ops,
|
|
|
|
#endif
|
|
|
|
.of_match_table = ingenic_tcu_of_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);
|