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OpenCloudOS-Kernel/arch/arm/mach-sunxi/sunxi.c

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ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
/*
* Device Tree support for Allwinner A1X SoCs
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
ARM: sunxi: Register the A31 reset IP in init_time The A31 has a reset IP that maintains a few other IPs in reset by default. Among these IPs are the UARTs, and most notably the timers. We thus need to register the reset driver before initializing the timers so that the reset timer can use the reset framework. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-10-05 20:53:48 +08:00
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
ARM: sunxi: Reintroduce the restart code for A10/A20 SoCs This partly reverts commits 553600502b84 (ARM: sunxi: Remove reset code from the platform) and 5e669ec583e2 (ARM: sunxi: Remove init_machine callback) for the sun4i, sun5i and sun7i families. This is needed because the watchdog counterpart of these commits was dropped, and didn't make it into 3.16. In order to still be able to reboot the board, we need to reintroduce that code. Of course, the long term view is still to get rid of that code in mach-sunxi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-06-29 21:48:53 +08:00
#include <linux/init.h>
ARM: sunxi: Register cpufreq-dt for sun[45678]i On sun[45678]i, we have one cluster of identical cores sharing a clock, which is ideal for using cpufreq-dt. Register a platform device for cpufreq-dt. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-06 10:35:11 +08:00
#include <linux/platform_device.h>
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
#include <asm/mach/arch.h>
ARM: sunxi: Rework the restart code The Allwinner sun6i (A31) has a slightly different watchdog, that doesn't allow to use the already existing restart code. Rework a bit the restart code to allow to plug in more easily different restart handlers depending on the device tree. In the past, we were also meaning sunxi as a generic name covering all Allwinner SoCs. This won't be true anymore with the A31 (sun6i) that differs pretty much from sun4i and sun5i, and we will end up having sunxi, for sun4i and sun5i, and sun6i, which is neither consistent nor convenient. So, while we're at it, also change sunxi to sun4i. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-12 03:21:11 +08:00
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
static const char * const sunxi_board_dt_compat[] = {
sunxi: Change the machine compatible string. Commit 68136b10 ("ARM: sunxi: Change device tree naming scheme for sunxi") changed the naming scheme and the compatible strings used in the device trees related to the sunXi platform, but forgot to change the compatible string in the DT machine definition. This prevents the kernel from booting on these boards. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-12-18 22:17:12 +08:00
"allwinner,sun4i-a10",
ARM: sunxi: Add Allwinner A10s machine compatible The A10s is a SoC member of the Allwinner sun5i family. It is basically an A13 with an EMAC and an HDMI controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-06-09 15:40:05 +08:00
"allwinner,sun5i-a10s",
sunxi: Change the machine compatible string. Commit 68136b10 ("ARM: sunxi: Change device tree naming scheme for sunxi") changed the naming scheme and the compatible strings used in the device trees related to the sunXi platform, but forgot to change the compatible string in the DT machine definition. This prevents the kernel from booting on these boards. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-12-18 22:17:12 +08:00
"allwinner,sun5i-a13",
ARM: sunxi: Add R8 support The R8 is a new Allwinner SoC based on the A13. While both are very similar, there's still a few differences. Introduce a new compatible to deal with them. In order to have a consistent naming, instead of mentioning the Allwinner A series as the machine name, switch to sun4i/sun5i like what is done for the other families. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-10 01:38:04 +08:00
"allwinner,sun5i-r8",
ARM: sunxi: Support the Nextthing GR8 The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family. It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S), but some controllers missing too (Ethernet, less I2C, less UARTs). Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-09-08 18:26:08 +08:00
"nextthing,gr8",
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
NULL,
};
ARM: sunxi: Add R8 support The R8 is a new Allwinner SoC based on the A13. While both are very similar, there's still a few differences. Introduce a new compatible to deal with them. In order to have a consistent naming, instead of mentioning the Allwinner A series as the machine name, switch to sun4i/sun5i like what is done for the other families. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-10 01:38:04 +08:00
DT_MACHINE_START(SUNXI_DT, "Allwinner sun4i/sun5i Families")
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
.dt_compat = sunxi_board_dt_compat,
MACHINE_END
ARM: sunxi: Split out the DT machines for sun6i and sun7i The A20 and A31 SMP code have a different way of bringing up a new core. This will prevent us from using the same set of smp_operations for the two SoCs family. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-11 20:35:08 +08:00
static const char * const sun6i_board_dt_compat[] = {
"allwinner,sun6i-a31",
ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi So far the A31s is 100% compatible with the A31, still lets do the same as what we've done for the A13 / A10s and give it its own compatible string, in case we need to differentiate later. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [Maxime: Removed unusude CPU_OF_DECLARE_METHOD] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-18 01:18:14 +08:00
"allwinner,sun6i-a31s",
ARM: sunxi: Split out the DT machines for sun6i and sun7i The A20 and A31 SMP code have a different way of bringing up a new core. This will prevent us from using the same set of smp_operations for the two SoCs family. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-11 20:35:08 +08:00
NULL,
};
ARM: sunxi: Register the A31 reset IP in init_time The A31 has a reset IP that maintains a few other IPs in reset by default. Among these IPs are the UARTs, and most notably the timers. We thus need to register the reset driver before initializing the timers so that the reset timer can use the reset framework. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-10-05 20:53:48 +08:00
extern void __init sun6i_reset_init(void);
static void __init sun6i_timer_init(void)
{
of_clk_init(NULL);
ARM: sunxi: allow building without reset controller The sunxi reset controller code is only used with sun6i (a31). After the platform has been split up into per-soc options, it's now possible to build it without the reset controller code, so the base platform init must not call into the reset driver if that is turned off at compile time. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-05-26 23:14:57 +08:00
if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
sun6i_reset_init();
clocksource/drivers: Rename clocksource_probe to timer_probe The function name is now renamed to 'timer_probe' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-05-26 23:40:46 +08:00
timer_probe();
ARM: sunxi: Register the A31 reset IP in init_time The A31 has a reset IP that maintains a few other IPs in reset by default. Among these IPs are the UARTs, and most notably the timers. We thus need to register the reset driver before initializing the timers so that the reset timer can use the reset framework. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-10-05 20:53:48 +08:00
}
ARM: sunxi: Split out the DT machines for sun6i and sun7i The A20 and A31 SMP code have a different way of bringing up a new core. This will prevent us from using the same set of smp_operations for the two SoCs family. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-11 20:35:08 +08:00
DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
ARM: sunxi: Register the A31 reset IP in init_time The A31 has a reset IP that maintains a few other IPs in reset by default. Among these IPs are the UARTs, and most notably the timers. We thus need to register the reset driver before initializing the timers so that the reset timer can use the reset framework. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-10-05 20:53:48 +08:00
.init_time = sun6i_timer_init,
ARM: sunxi: Split out the DT machines for sun6i and sun7i The A20 and A31 SMP code have a different way of bringing up a new core. This will prevent us from using the same set of smp_operations for the two SoCs family. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-11 20:35:08 +08:00
.dt_compat = sun6i_board_dt_compat,
MACHINE_END
static const char * const sun7i_board_dt_compat[] = {
"allwinner,sun7i-a20",
NULL,
};
DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
.dt_compat = sun7i_board_dt_compat,
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
MACHINE_END
ARM: sunxi: Introduce Allwinner A23 support The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of the IPs found in previous SoCs, notably the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-06-20 22:52:50 +08:00
static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
ARM: sunxi: Add Machine support for A33 Add machine support for the Allwinner A33 quad core cortex-a7 based SoC, which is similar to the A23 SoC. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-05-30 22:55:01 +08:00
"allwinner,sun8i-a33",
ARM: sunxi: Introduce Allwinner for A83T support Allwinner A83T is octa-core cortex-a7 based SoC. It's clock control unit and prcm, pinmux are different from previous sun8i series. Its processor cores are arragned in two clusters 4 cores each, similar to A80. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> [maxime: Removed the clock protection code] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-06 21:11:52 +08:00
"allwinner,sun8i-a83t",
ARM: sunxi: add support for H2+ SoC Allwinner H2+ is a quad-core Cortex-A7 SoC. It is very like H3, that they share the same SoC ID (0x1680), and H3 memory maps as well as drivers works well on the SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-12-02 23:05:12 +08:00
"allwinner,sun8i-h2-plus",
ARM: sunxi: Introduce Allwinner H3 support The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar to other sun8i family SoCs like the A23. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-05-16 00:38:55 +08:00
"allwinner,sun8i-h3",
ARM: sunxi: add support for R40 SoC Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-22 13:23:22 +08:00
"allwinner,sun8i-r40",
arm: sunxi: add support for V3s SoC Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB integrated DRAM, and several peripherals. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-20 01:54:44 +08:00
"allwinner,sun8i-v3s",
ARM: sunxi: Introduce Allwinner A23 support The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of the IPs found in previous SoCs, notably the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-06-20 22:52:50 +08:00
NULL,
};
ARM: sunxi: Introduce Allwinner H3 support The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar to other sun8i family SoCs like the A23. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-05-16 00:38:55 +08:00
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.init_time = sun6i_timer_init,
ARM: sunxi: Introduce Allwinner A23 support The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of the IPs found in previous SoCs, notably the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-06-20 22:52:50 +08:00
.dt_compat = sun8i_board_dt_compat,
MACHINE_END
ARM: sunxi: Introduce Allwinner A80 support The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC. While it's processor cores and interconnecting bus are new, it re-uses many peripherals found in earlier Allwinner SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-08 21:02:52 +08:00
static const char * const sun9i_board_dt_compat[] = {
"allwinner,sun9i-a80",
NULL,
};
DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
.dt_compat = sun9i_board_dt_compat,
MACHINE_END