2017-12-15 02:03:03 +08:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2016-2017 Hisilicon Limited. */
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#ifndef __HCLGE_MBX_H
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#define __HCLGE_MBX_H
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#include <linux/init.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#define HCLGE_MBX_VF_MSG_DATA_NUM 16
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enum HCLGE_MBX_OPCODE {
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HCLGE_MBX_RESET = 0x01, /* (VF -> PF) assert reset */
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2018-03-22 22:28:59 +08:00
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HCLGE_MBX_ASSERTING_RESET, /* (PF -> VF) PF is asserting reset*/
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2017-12-15 02:03:03 +08:00
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HCLGE_MBX_SET_UNICAST, /* (VF -> PF) set UC addr */
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HCLGE_MBX_SET_MULTICAST, /* (VF -> PF) set MC addr */
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HCLGE_MBX_SET_VLAN, /* (VF -> PF) set VLAN */
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HCLGE_MBX_MAP_RING_TO_VECTOR, /* (VF -> PF) map ring-to-vector */
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HCLGE_MBX_UNMAP_RING_TO_VECTOR, /* (VF -> PF) unamp ring-to-vector */
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HCLGE_MBX_SET_PROMISC_MODE, /* (VF -> PF) set promiscuous mode */
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HCLGE_MBX_SET_MACVLAN, /* (VF -> PF) set unicast filter */
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HCLGE_MBX_API_NEGOTIATE, /* (VF -> PF) negotiate API version */
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HCLGE_MBX_GET_QINFO, /* (VF -> PF) get queue config */
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2019-02-23 17:22:15 +08:00
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HCLGE_MBX_GET_QDEPTH, /* (VF -> PF) get queue depth */
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2017-12-15 02:03:03 +08:00
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HCLGE_MBX_GET_TCINFO, /* (VF -> PF) get TC config */
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HCLGE_MBX_GET_RETA, /* (VF -> PF) get RETA */
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HCLGE_MBX_GET_RSS_KEY, /* (VF -> PF) get RSS key */
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HCLGE_MBX_GET_MAC_ADDR, /* (VF -> PF) get MAC addr */
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HCLGE_MBX_PF_VF_RESP, /* (PF -> VF) generate respone to VF */
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HCLGE_MBX_GET_BDNUM, /* (VF -> PF) get BD num */
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HCLGE_MBX_GET_BUFSIZE, /* (VF -> PF) get buffer size */
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HCLGE_MBX_GET_STREAMID, /* (VF -> PF) get stream id */
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HCLGE_MBX_SET_AESTART, /* (VF -> PF) start ae */
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HCLGE_MBX_SET_TSOSTATS, /* (VF -> PF) get tso stats */
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HCLGE_MBX_LINK_STAT_CHANGE, /* (PF -> VF) link status has changed */
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HCLGE_MBX_GET_BASE_CONFIG, /* (VF -> PF) get config */
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HCLGE_MBX_BIND_FUNC_QUEUE, /* (VF -> PF) bind function and queue */
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HCLGE_MBX_GET_LINK_STATUS, /* (VF -> PF) get link status */
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HCLGE_MBX_QUEUE_RESET, /* (VF -> PF) reset queue */
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2018-11-18 11:19:12 +08:00
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HCLGE_MBX_KEEP_ALIVE, /* (VF -> PF) send keep alive cmd */
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HCLGE_MBX_SET_ALIVE, /* (VF -> PF) set alive state */
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2018-11-18 11:19:13 +08:00
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HCLGE_MBX_SET_MTU, /* (VF -> PF) set mtu */
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2018-12-15 23:31:57 +08:00
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HCLGE_MBX_GET_QID_IN_PF, /* (VF -> PF) get queue id in pf */
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2019-02-02 22:39:33 +08:00
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HCLGE_MBX_LINK_STAT_MODE, /* (PF -> VF) link mode has changed */
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HCLGE_MBX_GET_LINK_MODE, /* (VF -> PF) get the link mode of pf */
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2019-07-21 21:08:31 +08:00
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HCLGE_MBX_PUSH_VLAN_INFO, /* (PF -> VF) push port base vlan */
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2019-04-04 16:17:50 +08:00
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HCLGE_MBX_GET_MEDIA_TYPE, /* (VF -> PF) get media type */
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2019-10-08 09:20:06 +08:00
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HCLGE_MBX_PUSH_PROMISC_INFO, /* (PF -> VF) push vf promisc info */
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2019-02-20 10:32:48 +08:00
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2019-10-31 19:23:22 +08:00
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HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */
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2019-08-01 11:55:34 +08:00
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HCLGE_MBX_PUSH_LINK_STATUS, /* (M7 -> PF) get port link status */
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2019-08-01 11:55:35 +08:00
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HCLGE_MBX_NCSI_ERROR, /* (M7 -> PF) receive a NCSI error */
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2017-12-15 02:03:03 +08:00
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};
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/* below are per-VF mac-vlan subcodes */
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enum hclge_mbx_mac_vlan_subcode {
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HCLGE_MBX_MAC_VLAN_UC_MODIFY = 0, /* modify UC mac addr */
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HCLGE_MBX_MAC_VLAN_UC_ADD, /* add a new UC mac addr */
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HCLGE_MBX_MAC_VLAN_UC_REMOVE, /* remove a new UC mac addr */
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HCLGE_MBX_MAC_VLAN_MC_MODIFY, /* modify MC mac addr */
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HCLGE_MBX_MAC_VLAN_MC_ADD, /* add new MC mac addr */
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HCLGE_MBX_MAC_VLAN_MC_REMOVE, /* remove MC mac addr */
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};
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/* below are per-VF vlan cfg subcodes */
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enum hclge_mbx_vlan_cfg_subcode {
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HCLGE_MBX_VLAN_FILTER = 0, /* set vlan filter */
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HCLGE_MBX_VLAN_TX_OFF_CFG, /* set tx side vlan offload */
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HCLGE_MBX_VLAN_RX_OFF_CFG, /* set rx side vlan offload */
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2019-04-14 09:47:38 +08:00
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HCLGE_MBX_PORT_BASE_VLAN_CFG, /* set port based vlan configuration */
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HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, /* get port based vlan state */
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2017-12-15 02:03:03 +08:00
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};
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#define HCLGE_MBX_MAX_MSG_SIZE 16
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2019-10-31 19:23:23 +08:00
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#define HCLGE_MBX_MAX_RESP_DATA_SIZE 8U
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2018-03-10 11:29:29 +08:00
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#define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM 3
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#define HCLGE_MBX_RING_NODE_VARIABLE_NUM 3
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2017-12-15 02:03:03 +08:00
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struct hclgevf_mbx_resp_status {
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struct mutex mbx_mutex; /* protects against contending sync cmd resp */
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u32 origin_mbx_msg;
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bool received_resp;
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int resp_status;
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u8 additional_info[HCLGE_MBX_MAX_RESP_DATA_SIZE];
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};
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struct hclge_mbx_vf_to_pf_cmd {
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u8 rsv;
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u8 mbx_src_vfid; /* Auto filled by IMP */
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2019-04-25 20:42:50 +08:00
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u8 mbx_need_resp;
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u8 rsv1[1];
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2017-12-15 02:03:03 +08:00
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u8 msg_len;
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u8 rsv2[3];
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u8 msg[HCLGE_MBX_MAX_MSG_SIZE];
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};
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2019-04-25 20:42:50 +08:00
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#define HCLGE_MBX_NEED_RESP_BIT BIT(0)
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2017-12-15 02:03:03 +08:00
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struct hclge_mbx_pf_to_vf_cmd {
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u8 dest_vfid;
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u8 rsv[3];
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u8 msg_len;
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u8 rsv1[3];
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u16 msg[8];
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};
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2018-11-09 22:07:48 +08:00
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struct hclge_vf_rst_cmd {
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u8 dest_vfid;
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u8 vf_rst;
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u8 rsv[22];
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};
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2018-03-22 22:28:58 +08:00
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/* used by VF to store the received Async responses from PF */
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struct hclgevf_mbx_arq_ring {
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#define HCLGE_MBX_MAX_ARQ_MSG_SIZE 8
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#define HCLGE_MBX_MAX_ARQ_MSG_NUM 1024
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struct hclgevf_dev *hdev;
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u32 head;
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u32 tail;
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2019-04-25 20:42:49 +08:00
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atomic_t count;
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2018-03-22 22:28:58 +08:00
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u16 msg_q[HCLGE_MBX_MAX_ARQ_MSG_NUM][HCLGE_MBX_MAX_ARQ_MSG_SIZE];
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};
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2017-12-15 02:03:03 +08:00
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#define hclge_mbx_ring_ptr_move_crq(crq) \
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(crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)
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2018-03-22 22:28:58 +08:00
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#define hclge_mbx_tail_ptr_move_arq(arq) \
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(arq.tail = (arq.tail + 1) % HCLGE_MBX_MAX_ARQ_MSG_SIZE)
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#define hclge_mbx_head_ptr_move_arq(arq) \
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(arq.head = (arq.head + 1) % HCLGE_MBX_MAX_ARQ_MSG_SIZE)
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2017-12-15 02:03:03 +08:00
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#endif
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