2009-02-24 08:33:56 +08:00
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/*
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* Performance counter support for POWER5 (not POWER5++) processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 18:02:48 +08:00
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#include <linux/perf_event.h>
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2009-06-17 19:52:09 +08:00
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#include <linux/string.h>
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2009-02-24 08:33:56 +08:00
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#include <asm/reg.h>
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2009-06-17 19:52:09 +08:00
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#include <asm/cputable.h>
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2009-02-24 08:33:56 +08:00
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/*
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* Bits in event code for POWER5 (not POWER5++)
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*/
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#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0xf
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#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
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#define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
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#define PM_UNIT_MSK 0xf
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#define PM_BYTE_SH 12 /* Byte number of event bus to use */
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#define PM_BYTE_MSK 7
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#define PM_GRS_SH 8 /* Storage subsystem mux select */
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#define PM_GRS_MSK 7
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#define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
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#define PM_PMCSEL_MSK 0x7f
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/* Values in PM_UNIT field */
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#define PM_FPU 0
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#define PM_ISU0 1
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#define PM_IFU 2
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#define PM_ISU1 3
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#define PM_IDU 4
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#define PM_ISU0_ALT 6
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#define PM_GRS 7
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#define PM_LSU0 8
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#define PM_LSU1 0xc
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#define PM_LASTUNIT 0xc
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/*
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* Bits in MMCR1 for POWER5
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*/
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#define MMCR1_TTM0SEL_SH 62
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#define MMCR1_TTM1SEL_SH 60
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#define MMCR1_TTM2SEL_SH 58
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#define MMCR1_TTM3SEL_SH 56
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#define MMCR1_TTMSEL_MSK 3
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#define MMCR1_TD_CP_DBG0SEL_SH 54
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#define MMCR1_TD_CP_DBG1SEL_SH 52
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#define MMCR1_TD_CP_DBG2SEL_SH 50
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#define MMCR1_TD_CP_DBG3SEL_SH 48
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#define MMCR1_GRS_L2SEL_SH 46
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#define MMCR1_GRS_L2SEL_MSK 3
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#define MMCR1_GRS_L3SEL_SH 44
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#define MMCR1_GRS_L3SEL_MSK 3
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#define MMCR1_GRS_MCSEL_SH 41
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#define MMCR1_GRS_MCSEL_MSK 7
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#define MMCR1_GRS_FABSEL_SH 39
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#define MMCR1_GRS_FABSEL_MSK 3
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#define MMCR1_PMC1_ADDER_SEL_SH 35
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#define MMCR1_PMC2_ADDER_SEL_SH 34
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#define MMCR1_PMC3_ADDER_SEL_SH 33
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#define MMCR1_PMC4_ADDER_SEL_SH 32
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#define MMCR1_PMC1SEL_SH 25
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#define MMCR1_PMC2SEL_SH 17
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#define MMCR1_PMC3SEL_SH 9
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#define MMCR1_PMC4SEL_SH 1
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#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
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#define MMCR1_PMCSEL_MSK 0x7f
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/*
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* Layout of constraint bits:
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* 6666555555555544444444443333333333222222222211111111110000000000
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* 3210987654321098765432109876543210987654321098765432109876543210
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* <><>[ ><><>< ><> [ >[ >[ >< >< >< >< ><><><><><><>
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* T0T1 NC G0G1G2 G3 UC PS1PS2 B0 B1 B2 B3 P6P5P4P3P2P1
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*
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* T0 - TTM0 constraint
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* 54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
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*
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* T1 - TTM1 constraint
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* 52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
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*
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* NC - number of counters
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* 51: NC error 0x0008_0000_0000_0000
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* 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
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*
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* G0..G3 - GRS mux constraints
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* 46-47: GRS_L2SEL value
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* 44-45: GRS_L3SEL value
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* 41-44: GRS_MCSEL value
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* 39-40: GRS_FABSEL value
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* Note that these match up with their bit positions in MMCR1
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*
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* UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
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* 37: UC3 error 0x20_0000_0000
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* 36: FPU|IFU|ISU1 events needed 0x10_0000_0000
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* 35: ISU0 events needed 0x08_0000_0000
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* 34: IDU|GRS events needed 0x04_0000_0000
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*
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* PS1
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* 33: PS1 error 0x2_0000_0000
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* 31-32: count of events needing PMC1/2 0x1_8000_0000
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*
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* PS2
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* 30: PS2 error 0x4000_0000
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* 28-29: count of events needing PMC3/4 0x3000_0000
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*
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* B0
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* 24-27: Byte 0 event source 0x0f00_0000
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* Encoding as for the event code
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*
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* B1, B2, B3
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* 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
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*
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* P1..P6
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* 0-11: Count of events needing PMC1..PMC6
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*/
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static const int grsel_shift[8] = {
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MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
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MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
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MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
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};
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/* Masks and values for using events from the various units */
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2009-06-17 19:51:13 +08:00
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static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
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[PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul },
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[PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul },
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[PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul },
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[PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul },
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[PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul },
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[PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul },
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2009-02-24 08:33:56 +08:00
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};
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2009-06-17 19:51:13 +08:00
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static int power5_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp)
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2009-02-24 08:33:56 +08:00
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{
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int pmc, byte, unit, sh;
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int bit, fmask;
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2009-06-17 19:51:13 +08:00
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unsigned long mask = 0, value = 0;
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2009-02-24 08:33:56 +08:00
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int grp = -1;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 6)
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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if (pmc <= 4)
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grp = (pmc - 1) >> 1;
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else if (event != 0x500009 && event != 0x600005)
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return -1;
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}
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if (event & PM_BUSEVENT_MSK) {
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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if (unit > PM_LASTUNIT)
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return -1;
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if (unit == PM_ISU0_ALT)
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unit = PM_ISU0;
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mask |= unit_cons[unit][0];
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value |= unit_cons[unit][1];
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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if (byte >= 4) {
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if (unit != PM_LSU1)
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return -1;
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/* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
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++unit;
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byte &= 3;
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}
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if (unit == PM_GRS) {
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bit = event & 7;
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fmask = (bit == 6)? 7: 3;
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sh = grsel_shift[bit];
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2009-06-17 19:51:13 +08:00
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mask |= (unsigned long)fmask << sh;
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value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
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<< sh;
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2009-02-24 08:33:56 +08:00
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}
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/*
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* Bus events on bytes 0 and 2 can be counted
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* on PMC1/2; bytes 1 and 3 on PMC3/4.
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*/
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if (!pmc)
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grp = byte & 1;
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/* Set byte lane select field */
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2009-06-17 19:51:13 +08:00
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mask |= 0xfUL << (24 - 4 * byte);
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value |= (unsigned long)unit << (24 - 4 * byte);
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2009-02-24 08:33:56 +08:00
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}
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if (grp == 0) {
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/* increment PMC1/2 field */
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2009-06-17 19:51:13 +08:00
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mask |= 0x200000000ul;
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value |= 0x080000000ul;
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2009-02-24 08:33:56 +08:00
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} else if (grp == 1) {
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/* increment PMC3/4 field */
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2009-06-17 19:51:13 +08:00
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mask |= 0x40000000ul;
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value |= 0x10000000ul;
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2009-02-24 08:33:56 +08:00
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}
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if (pmc < 5) {
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/* need a counter from PMC1-4 set */
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2009-06-17 19:51:13 +08:00
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mask |= 0x8000000000000ul;
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value |= 0x1000000000000ul;
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2009-02-24 08:33:56 +08:00
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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#define MAX_ALT 3 /* at most 3 alternatives for any event */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
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{ 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
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{ 0x100005, 0x600005 }, /* PM_RUN_CYC */
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{ 0x100009, 0x200009, 0x500009 }, /* PM_INST_CMPL */
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{ 0x300009, 0x400009 }, /* PM_INST_DISP */
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};
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/*
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* Scan the alternatives table for a match and return the
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* index into the alternatives table if found, else -1.
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*/
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2009-05-14 11:29:14 +08:00
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static int find_alternative(u64 event)
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2009-02-24 08:33:56 +08:00
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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break;
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for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
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if (event == event_alternatives[i][j])
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return i;
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}
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return -1;
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}
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static const unsigned char bytedecode_alternatives[4][4] = {
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/* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
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/* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
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/* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
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/* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
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};
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/*
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* Some direct events for decodes of event bus byte 3 have alternative
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* PMCSEL values on other counters. This returns the alternative
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* event code for those that do, or -1 otherwise.
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*/
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2009-06-03 17:38:58 +08:00
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static s64 find_alternative_bdecode(u64 event)
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2009-02-24 08:33:56 +08:00
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{
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int pmc, altpmc, pp, j;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc == 0 || pmc > 4)
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return -1;
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altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */
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pp = event & PM_PMCSEL_MSK;
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for (j = 0; j < 4; ++j) {
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if (bytedecode_alternatives[pmc - 1][j] == pp) {
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return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
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(altpmc << PM_PMC_SH) |
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|
|
bytedecode_alternatives[altpmc - 1][j];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2009-05-14 11:29:14 +08:00
|
|
|
static int power5_get_alternatives(u64 event, unsigned int flags, u64 alt[])
|
2009-02-24 08:33:56 +08:00
|
|
|
{
|
2009-05-14 11:29:14 +08:00
|
|
|
int i, j, nalt = 1;
|
2009-06-03 17:38:58 +08:00
|
|
|
s64 ae;
|
2009-02-24 08:33:56 +08:00
|
|
|
|
|
|
|
alt[0] = event;
|
|
|
|
nalt = 1;
|
|
|
|
i = find_alternative(event);
|
|
|
|
if (i >= 0) {
|
|
|
|
for (j = 0; j < MAX_ALT; ++j) {
|
|
|
|
ae = event_alternatives[i][j];
|
|
|
|
if (ae && ae != event)
|
|
|
|
alt[nalt++] = ae;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ae = find_alternative_bdecode(event);
|
|
|
|
if (ae > 0)
|
|
|
|
alt[nalt++] = ae;
|
|
|
|
}
|
|
|
|
return nalt;
|
|
|
|
}
|
|
|
|
|
2009-04-08 18:30:18 +08:00
|
|
|
/*
|
|
|
|
* Map of which direct events on which PMCs are marked instruction events.
|
|
|
|
* Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
|
|
|
|
* Bit 0 is set if it is marked for all PMCs.
|
|
|
|
* The 0x80 bit indicates a byte decode PMCSEL value.
|
|
|
|
*/
|
|
|
|
static unsigned char direct_event_is_marked[0x28] = {
|
|
|
|
0, /* 00 */
|
|
|
|
0x1f, /* 01 PM_IOPS_CMPL */
|
|
|
|
0x2, /* 02 PM_MRK_GRP_DISP */
|
|
|
|
0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
|
|
|
|
0, /* 04 */
|
|
|
|
0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
|
|
|
|
0x80, /* 06 */
|
|
|
|
0x80, /* 07 */
|
|
|
|
0, 0, 0,/* 08 - 0a */
|
|
|
|
0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
|
|
|
|
0, /* 0c */
|
|
|
|
0x80, /* 0d */
|
|
|
|
0x80, /* 0e */
|
|
|
|
0, /* 0f */
|
|
|
|
0, /* 10 */
|
|
|
|
0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
|
|
|
|
0, /* 12 */
|
|
|
|
0x10, /* 13 PM_MRK_GRP_CMPL */
|
|
|
|
0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
|
|
|
|
0x2, /* 15 PM_MRK_GRP_ISSUED */
|
|
|
|
0x80, /* 16 */
|
|
|
|
0x80, /* 17 */
|
|
|
|
0, 0, 0, 0, 0,
|
|
|
|
0x80, /* 1d */
|
|
|
|
0x80, /* 1e */
|
|
|
|
0, /* 1f */
|
|
|
|
0x80, /* 20 */
|
|
|
|
0x80, /* 21 */
|
|
|
|
0x80, /* 22 */
|
|
|
|
0x80, /* 23 */
|
|
|
|
0x80, /* 24 */
|
|
|
|
0x80, /* 25 */
|
|
|
|
0x80, /* 26 */
|
|
|
|
0x80, /* 27 */
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Returns 1 if event counts things relating to marked instructions
|
|
|
|
* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
|
|
|
|
*/
|
2009-05-14 11:29:14 +08:00
|
|
|
static int power5_marked_instr_event(u64 event)
|
2009-04-08 18:30:18 +08:00
|
|
|
{
|
|
|
|
int pmc, psel;
|
|
|
|
int bit, byte, unit;
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
|
|
|
|
psel = event & PM_PMCSEL_MSK;
|
|
|
|
if (pmc >= 5)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
bit = -1;
|
|
|
|
if (psel < sizeof(direct_event_is_marked)) {
|
|
|
|
if (direct_event_is_marked[psel] & (1 << pmc))
|
|
|
|
return 1;
|
|
|
|
if (direct_event_is_marked[psel] & 0x80)
|
|
|
|
bit = 4;
|
|
|
|
else if (psel == 0x08)
|
|
|
|
bit = pmc - 1;
|
|
|
|
else if (psel == 0x10)
|
|
|
|
bit = 4 - pmc;
|
|
|
|
else if (psel == 0x1b && (pmc == 1 || pmc == 3))
|
|
|
|
bit = 4;
|
|
|
|
} else if ((psel & 0x58) == 0x40)
|
|
|
|
bit = psel & 7;
|
|
|
|
|
|
|
|
if (!(event & PM_BUSEVENT_MSK))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
|
|
|
|
unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
|
|
|
|
if (unit == PM_LSU0) {
|
|
|
|
/* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
|
|
|
|
mask = 0x5dff00;
|
|
|
|
} else if (unit == PM_LSU1 && byte >= 4) {
|
|
|
|
byte -= 4;
|
|
|
|
/* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */
|
|
|
|
mask = 0x5f00c0aa;
|
|
|
|
} else
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return (mask >> (byte * 8 + bit)) & 1;
|
|
|
|
}
|
|
|
|
|
2009-05-14 11:29:14 +08:00
|
|
|
static int power5_compute_mmcr(u64 event[], int n_ev,
|
2009-06-17 19:51:13 +08:00
|
|
|
unsigned int hwc[], unsigned long mmcr[])
|
2009-02-24 08:33:56 +08:00
|
|
|
{
|
2009-06-17 19:51:13 +08:00
|
|
|
unsigned long mmcr1 = 0;
|
2009-10-28 02:31:29 +08:00
|
|
|
unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
|
2009-02-24 08:33:56 +08:00
|
|
|
unsigned int pmc, unit, byte, psel;
|
|
|
|
unsigned int ttm, grp;
|
|
|
|
int i, isbus, bit, grsel;
|
|
|
|
unsigned int pmc_inuse = 0;
|
|
|
|
unsigned int pmc_grp_use[2];
|
|
|
|
unsigned char busbyte[4];
|
|
|
|
unsigned char unituse[16];
|
|
|
|
int ttmuse;
|
|
|
|
|
|
|
|
if (n_ev > 6)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* First pass to count resource use */
|
|
|
|
pmc_grp_use[0] = pmc_grp_use[1] = 0;
|
|
|
|
memset(busbyte, 0, sizeof(busbyte));
|
|
|
|
memset(unituse, 0, sizeof(unituse));
|
|
|
|
for (i = 0; i < n_ev; ++i) {
|
|
|
|
pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
|
|
|
|
if (pmc) {
|
|
|
|
if (pmc > 6)
|
|
|
|
return -1;
|
|
|
|
if (pmc_inuse & (1 << (pmc - 1)))
|
|
|
|
return -1;
|
|
|
|
pmc_inuse |= 1 << (pmc - 1);
|
|
|
|
/* count 1/2 vs 3/4 use */
|
|
|
|
if (pmc <= 4)
|
|
|
|
++pmc_grp_use[(pmc - 1) >> 1];
|
|
|
|
}
|
|
|
|
if (event[i] & PM_BUSEVENT_MSK) {
|
|
|
|
unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
|
|
|
|
byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
|
|
|
|
if (unit > PM_LASTUNIT)
|
|
|
|
return -1;
|
|
|
|
if (unit == PM_ISU0_ALT)
|
|
|
|
unit = PM_ISU0;
|
|
|
|
if (byte >= 4) {
|
|
|
|
if (unit != PM_LSU1)
|
|
|
|
return -1;
|
|
|
|
++unit;
|
|
|
|
byte &= 3;
|
|
|
|
}
|
|
|
|
if (!pmc)
|
|
|
|
++pmc_grp_use[byte & 1];
|
|
|
|
if (busbyte[byte] && busbyte[byte] != unit)
|
|
|
|
return -1;
|
|
|
|
busbyte[byte] = unit;
|
|
|
|
unituse[unit] = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assign resources and set multiplexer selects.
|
|
|
|
*
|
|
|
|
* PM_ISU0 can go either on TTM0 or TTM1, but that's the only
|
|
|
|
* choice we have to deal with.
|
|
|
|
*/
|
|
|
|
if (unituse[PM_ISU0] &
|
|
|
|
(unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
|
|
|
|
unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */
|
|
|
|
unituse[PM_ISU0] = 0;
|
|
|
|
}
|
|
|
|
/* Set TTM[01]SEL fields. */
|
|
|
|
ttmuse = 0;
|
|
|
|
for (i = PM_FPU; i <= PM_ISU1; ++i) {
|
|
|
|
if (!unituse[i])
|
|
|
|
continue;
|
|
|
|
if (ttmuse++)
|
|
|
|
return -1;
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
|
2009-02-24 08:33:56 +08:00
|
|
|
}
|
|
|
|
ttmuse = 0;
|
|
|
|
for (; i <= PM_GRS; ++i) {
|
|
|
|
if (!unituse[i])
|
|
|
|
continue;
|
|
|
|
if (ttmuse++)
|
|
|
|
return -1;
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
|
2009-02-24 08:33:56 +08:00
|
|
|
}
|
|
|
|
if (ttmuse > 1)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
|
|
|
|
for (byte = 0; byte < 4; ++byte) {
|
|
|
|
unit = busbyte[byte];
|
|
|
|
if (!unit)
|
|
|
|
continue;
|
|
|
|
if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
|
|
|
|
/* get ISU0 through TTM1 rather than TTM0 */
|
|
|
|
unit = PM_ISU0_ALT;
|
|
|
|
} else if (unit == PM_LSU1 + 1) {
|
|
|
|
/* select lower word of LSU1 for this byte */
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
|
2009-02-24 08:33:56 +08:00
|
|
|
}
|
|
|
|
ttm = unit >> 2;
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= (unsigned long)ttm
|
|
|
|
<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
|
2009-02-24 08:33:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
|
|
|
|
for (i = 0; i < n_ev; ++i) {
|
|
|
|
pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
|
|
|
|
unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
|
|
|
|
byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
|
|
|
|
psel = event[i] & PM_PMCSEL_MSK;
|
|
|
|
isbus = event[i] & PM_BUSEVENT_MSK;
|
|
|
|
if (!pmc) {
|
|
|
|
/* Bus event or any-PMC direct event */
|
|
|
|
for (pmc = 0; pmc < 4; ++pmc) {
|
|
|
|
if (pmc_inuse & (1 << pmc))
|
|
|
|
continue;
|
|
|
|
grp = (pmc >> 1) & 1;
|
|
|
|
if (isbus) {
|
|
|
|
if (grp == (byte & 1))
|
|
|
|
break;
|
|
|
|
} else if (pmc_grp_use[grp] < 2) {
|
|
|
|
++pmc_grp_use[grp];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pmc_inuse |= 1 << pmc;
|
|
|
|
} else if (pmc <= 4) {
|
|
|
|
/* Direct event */
|
|
|
|
--pmc;
|
|
|
|
if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
|
|
|
|
/* add events on higher-numbered bus */
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
|
2009-02-24 08:33:56 +08:00
|
|
|
} else {
|
|
|
|
/* Instructions or run cycles on PMC5/6 */
|
|
|
|
--pmc;
|
|
|
|
}
|
|
|
|
if (isbus && unit == PM_GRS) {
|
|
|
|
bit = psel & 7;
|
|
|
|
grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
|
2009-02-24 08:33:56 +08:00
|
|
|
}
|
2009-04-08 18:30:18 +08:00
|
|
|
if (power5_marked_instr_event(event[i]))
|
|
|
|
mmcra |= MMCRA_SAMPLE_ENABLE;
|
2009-02-24 08:33:56 +08:00
|
|
|
if (pmc <= 3)
|
|
|
|
mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
|
|
|
|
hwc[i] = pmc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return MMCRx values */
|
|
|
|
mmcr[0] = 0;
|
|
|
|
if (pmc_inuse & 1)
|
|
|
|
mmcr[0] = MMCR0_PMC1CE;
|
|
|
|
if (pmc_inuse & 0x3e)
|
|
|
|
mmcr[0] |= MMCR0_PMCjCE;
|
|
|
|
mmcr[1] = mmcr1;
|
2009-04-08 18:30:18 +08:00
|
|
|
mmcr[2] = mmcra;
|
2009-02-24 08:33:56 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-17 19:51:13 +08:00
|
|
|
static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
2009-02-24 08:33:56 +08:00
|
|
|
{
|
|
|
|
if (pmc <= 3)
|
|
|
|
mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int power5_generic_events[] = {
|
2009-06-11 20:06:28 +08:00
|
|
|
[PERF_COUNT_HW_CPU_CYCLES] = 0xf,
|
|
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = 0x100009,
|
|
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = 0x4c1090, /* LD_REF_L1 */
|
|
|
|
[PERF_COUNT_HW_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */
|
|
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */
|
|
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
|
2009-02-24 08:33:56 +08:00
|
|
|
};
|
|
|
|
|
2009-06-11 12:55:42 +08:00
|
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Table of generalized cache-related events.
|
|
|
|
* 0 means not supported, -1 means nonsensical, other values
|
|
|
|
* are event codes.
|
|
|
|
*/
|
|
|
|
static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
|
|
|
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
[C(OP_READ)] = { 0x4c1090, 0x3c1088 },
|
|
|
|
[C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },
|
|
|
|
[C(OP_PREFETCH)] = { 0xc70e7, 0 },
|
|
|
|
},
|
|
|
|
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
[C(OP_READ)] = { 0, 0 },
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
[C(OP_PREFETCH)] = { 0, 0 },
|
|
|
|
},
|
2009-06-11 20:19:11 +08:00
|
|
|
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
2009-06-11 12:55:42 +08:00
|
|
|
[C(OP_READ)] = { 0, 0x3c309b },
|
|
|
|
[C(OP_WRITE)] = { 0, 0 },
|
|
|
|
[C(OP_PREFETCH)] = { 0xc50c3, 0 },
|
|
|
|
},
|
|
|
|
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
[C(OP_READ)] = { 0x2c4090, 0x800c4 },
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
},
|
|
|
|
[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
[C(OP_READ)] = { 0, 0x800c0 },
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
},
|
|
|
|
[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
[C(OP_READ)] = { 0x230e4, 0x230e5 },
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
},
|
2011-04-23 05:37:06 +08:00
|
|
|
[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
[C(OP_READ)] = { -1, -1 },
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
},
|
2009-06-11 12:55:42 +08:00
|
|
|
};
|
|
|
|
|
2009-06-17 19:52:09 +08:00
|
|
|
static struct power_pmu power5_pmu = {
|
|
|
|
.name = "POWER5",
|
2009-06-17 19:51:13 +08:00
|
|
|
.n_counter = 6,
|
|
|
|
.max_alternatives = MAX_ALT,
|
|
|
|
.add_fields = 0x7000090000555ul,
|
|
|
|
.test_adder = 0x3000490000000ul,
|
|
|
|
.compute_mmcr = power5_compute_mmcr,
|
|
|
|
.get_constraint = power5_get_constraint,
|
|
|
|
.get_alternatives = power5_get_alternatives,
|
|
|
|
.disable_pmc = power5_disable_pmc,
|
|
|
|
.n_generic = ARRAY_SIZE(power5_generic_events),
|
|
|
|
.generic_events = power5_generic_events,
|
|
|
|
.cache_events = &power5_cache_events,
|
2013-04-26 03:28:23 +08:00
|
|
|
.flags = PPMU_HAS_SSLOT,
|
2009-02-24 08:33:56 +08:00
|
|
|
};
|
2009-06-17 19:52:09 +08:00
|
|
|
|
2011-06-29 12:54:00 +08:00
|
|
|
static int __init init_power5_pmu(void)
|
2009-06-17 19:52:09 +08:00
|
|
|
{
|
2009-08-06 19:16:44 +08:00
|
|
|
if (!cur_cpu_spec->oprofile_cpu_type ||
|
|
|
|
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5"))
|
2009-06-17 19:52:09 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return register_power_pmu(&power5_pmu);
|
|
|
|
}
|
|
|
|
|
2010-11-26 01:38:29 +08:00
|
|
|
early_initcall(init_power5_pmu);
|