2019-05-29 22:17:52 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2011-02-03 00:20:16 +08:00
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/*
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* Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
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* for Intel part #(s):
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* - AF82MP20 PCH
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*
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* Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_SCU_WATCHDOG_H
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#define __INTEL_SCU_WATCHDOG_H
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#define WDT_VER "0.3"
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/* minimum time between interrupts */
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#define MIN_TIME_CYCLE 1
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/* Time from warning to reboot is 2 seconds */
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#define DEFAULT_SOFT_TO_HARD_MARGIN 2
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#define MAX_TIME 170
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#define DEFAULT_TIME 5
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#define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
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/* Ajustment to clock tick frequency to make timing come out right */
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#define FREQ_ADJUSTMENT 8
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struct intel_scu_watchdog_dev {
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ulong driver_open;
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ulong driver_closed;
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u32 timer_started;
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u32 timer_set;
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u32 threshold;
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u32 soft_threshold;
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u32 __iomem *timer_load_count_addr;
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u32 __iomem *timer_current_value_addr;
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u32 __iomem *timer_control_addr;
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u32 __iomem *timer_clear_interrupt_addr;
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u32 __iomem *timer_interrupt_status_addr;
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struct sfi_timer_table_entry *timer_tbl_ptr;
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struct notifier_block intel_scu_notifier;
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struct miscdevice miscdev;
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};
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extern int sfi_mtimer_num;
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/* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
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#endif /* __INTEL_SCU_WATCHDOG_H */
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