2019-05-27 14:55:01 +08:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2005-10-10 12:19:43 +08:00
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#ifndef _ASM_POWERPC_PROCESSOR_H
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#define _ASM_POWERPC_PROCESSOR_H
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2005-04-17 06:20:36 +08:00
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/*
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2005-10-10 12:19:43 +08:00
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* Copyright (C) 2001 PPC 64 Team, IBM Corp
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2005-04-17 06:20:36 +08:00
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*/
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2005-10-10 12:19:43 +08:00
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#include <asm/reg.h>
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2005-04-17 06:20:36 +08:00
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2008-06-25 12:07:18 +08:00
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#ifdef CONFIG_VSX
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#define TS_FPRWIDTH 2
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2013-09-23 10:04:37 +08:00
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#ifdef __BIG_ENDIAN__
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#define TS_FPROFFSET 0
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#define TS_VSRLOWOFFSET 1
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#else
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#define TS_FPROFFSET 1
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#define TS_VSRLOWOFFSET 0
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#endif
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2008-06-25 12:07:18 +08:00
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#else
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2008-06-26 15:07:48 +08:00
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#define TS_FPRWIDTH 1
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2013-09-23 10:04:37 +08:00
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#define TS_FPROFFSET 0
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2008-06-25 12:07:18 +08:00
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#endif
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2008-06-26 15:07:48 +08:00
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2012-12-07 05:49:56 +08:00
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#ifdef CONFIG_PPC64
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/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
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#define PPR_PRIORITY 3
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#ifdef __ASSEMBLY__
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2018-10-12 21:15:16 +08:00
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#define DEFAULT_PPR (PPR_PRIORITY << 50)
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2012-12-07 05:49:56 +08:00
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#else
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2018-10-12 21:15:16 +08:00
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#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
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2012-12-07 05:49:56 +08:00
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_PPC64 */
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2005-10-10 12:19:43 +08:00
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#ifndef __ASSEMBLY__
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2018-07-06 00:25:09 +08:00
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#include <linux/types.h>
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2019-01-17 20:27:28 +08:00
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#include <linux/thread_info.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/ptrace.h>
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2012-12-20 22:06:44 +08:00
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#include <asm/hw_breakpoint.h>
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2005-04-17 06:20:36 +08:00
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2005-11-10 10:37:51 +08:00
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/* We do _not_ want to define new machine types at all, those must die
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* in favor of using the device-tree
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* -- BenH.
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2005-04-17 06:20:36 +08:00
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*/
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2013-03-27 08:47:03 +08:00
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/* PREP sub-platform types. Unused */
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2005-04-17 06:20:36 +08:00
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#define _PREP_Motorola 0x01 /* motorola prep */
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#define _PREP_Firm 0x02 /* firmworks prep */
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#define _PREP_IBM 0x00 /* ibm prep */
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#define _PREP_Bull 0x03 /* bull prep */
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2005-11-10 10:37:51 +08:00
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/* CHRP sub-platform types. These are arbitrary */
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2005-04-17 06:20:36 +08:00
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#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
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#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
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#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
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2006-07-04 12:16:28 +08:00
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#define _CHRP_briq 0x07 /* TotalImpact's briQ */
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2005-04-17 06:20:36 +08:00
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2006-03-28 20:15:54 +08:00
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#if defined(__KERNEL__) && defined(CONFIG_PPC32)
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extern int _chrp_type;
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2005-11-10 10:37:51 +08:00
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2006-03-28 20:15:54 +08:00
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#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
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2005-10-10 12:19:43 +08:00
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/* Macros for adjusting thread priority (hardware multi-threading) */
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#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
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#define HMT_low() asm volatile("or 1,1,1 # low priority")
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#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
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#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
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#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
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#define HMT_high() asm volatile("or 3,3,3 # high priority")
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC64
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2019-01-31 18:08:48 +08:00
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#include <asm/task_size_64.h>
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2017-03-30 19:05:21 +08:00
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#else
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2019-01-31 18:08:48 +08:00
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#include <asm/task_size_32.h>
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2017-03-30 19:05:21 +08:00
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#endif
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2019-01-31 18:08:48 +08:00
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struct task_struct;
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void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
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void release_thread(struct task_struct *);
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2008-02-08 20:19:26 +08:00
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2005-04-17 06:20:36 +08:00
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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2013-09-10 18:20:42 +08:00
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#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
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2016-09-23 14:18:25 +08:00
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#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
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2013-09-10 18:20:42 +08:00
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/* FP and VSX 0-31 register set */
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struct thread_fp_state {
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u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
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u64 fpscr; /* Floating point status */
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};
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/* Complete AltiVec register set including VSCR */
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struct thread_vr_state {
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vector128 vr[32] __attribute__((aligned(16)));
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vector128 vscr __attribute__((aligned(16)));
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};
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2008-06-26 15:07:48 +08:00
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2013-07-04 14:15:46 +08:00
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struct debug_reg {
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2010-02-08 19:53:26 +08:00
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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/*
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* The following help to manage the use of Debug Control Registers
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* om the BookE platforms.
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*/
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2013-05-22 12:20:58 +08:00
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uint32_t dbcr0;
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uint32_t dbcr1;
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2010-02-08 19:53:26 +08:00
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#ifdef CONFIG_BOOKE
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2013-05-22 12:20:58 +08:00
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uint32_t dbcr2;
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2010-02-08 19:53:26 +08:00
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#endif
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/*
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* The stored value of the DBSR register will be the value at the
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* last debug interrupt. This register can only be read from the
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* user (will never be written to) and has value while helping to
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* describe the reason for the last debug trap. Torez
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*/
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2013-05-22 12:20:58 +08:00
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uint32_t dbsr;
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2010-02-08 19:53:26 +08:00
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/*
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* The following will contain addresses used by debug applications
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* to help trace and trap on particular address locations.
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* The bits in the Debug Control Registers above help define which
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* of the following registers will contain valid data and/or addresses.
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*/
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unsigned long iac1;
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unsigned long iac2;
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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unsigned long iac3;
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unsigned long iac4;
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#endif
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unsigned long dac1;
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unsigned long dac2;
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
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unsigned long dvc1;
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unsigned long dvc2;
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#endif
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2005-04-17 06:20:36 +08:00
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#endif
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2013-07-04 14:15:46 +08:00
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};
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struct thread_struct {
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unsigned long ksp; /* Kernel stack pointer */
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2013-06-26 13:42:22 +08:00
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2013-07-04 14:15:46 +08:00
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#ifdef CONFIG_PPC64
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unsigned long ksp_vsid;
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#endif
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struct pt_regs *regs; /* Pointer to saved register state */
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2018-05-14 21:03:15 +08:00
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mm_segment_t addr_limit; /* for get_fs() validation */
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2013-07-04 14:15:46 +08:00
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#ifdef CONFIG_BOOKE
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/* BookE base exception scratch space; align on cacheline */
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unsigned long normsave[8] ____cacheline_aligned;
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#endif
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#ifdef CONFIG_PPC32
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void *pgdir; /* root of page-table tree */
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unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
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2019-02-21 18:37:54 +08:00
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#ifdef CONFIG_PPC_RTAS
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unsigned long rtas_sp; /* stack pointer for when in RTAS */
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#endif
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2019-03-11 16:30:38 +08:00
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#endif
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#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
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unsigned long kuap; /* opened segments for user access */
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2013-07-04 14:15:46 +08:00
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#endif
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2013-06-26 13:42:22 +08:00
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/* Debug Registers */
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2013-07-04 14:15:46 +08:00
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struct debug_reg debug;
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2013-09-10 18:20:42 +08:00
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struct thread_fp_state fp_state;
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2013-09-10 18:21:10 +08:00
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struct thread_fp_state *fp_save_area;
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2005-10-10 12:19:43 +08:00
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int fpexc_mode; /* floating-point exception mode */
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2006-06-07 14:15:39 +08:00
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unsigned int align_ctl; /* alignment handling control */
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2010-06-15 14:05:19 +08:00
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct perf_event *ptrace_bps[HBP_NUM];
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/*
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* Helps identify source of single-step exception and subsequent
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* hw-breakpoint enablement
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*/
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struct perf_event *last_hit_ubp;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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2012-12-20 22:06:44 +08:00
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struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
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2012-08-24 05:27:09 +08:00
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unsigned long trap_nr; /* last trap # on this thread */
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powerpc/64s/hash: Add a SLB preload cache
When switching processes, currently all user SLBEs are cleared, and a
few (exec_base, pc, and stack) are preloaded. In trivial testing with
small apps, this tends to miss the heap and low 256MB segments, and it
will also miss commonly accessed segments on large memory workloads.
Add a simple round-robin preload cache that just inserts the last SLB
miss into the head of the cache and preloads those at context switch
time. Every 256 context switches, the oldest entry is removed from the
cache to shrink the cache and require fewer slbmte if they are unused.
Much more could go into this, including into the SLB entry reclaim
side to track some LRU information etc, which would require a study of
large memory workloads. But this is a simple thing we can do now that
is an obvious win for common workloads.
With the full series, process switching speed on the context_switch
benchmark on POWER9/hash (with kernel speculation security masures
disabled) increases from 140K/s to 178K/s (27%).
POWER8 does not change much (within 1%), it's unclear why it does not
see a big gain like POWER9.
Booting to busybox init with 256MB segments has SLB misses go down
from 945 to 69, and with 1T segments 900 to 21. These could almost all
be eliminated by preloading a bit more carefully with ELF binary
loading.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-09-14 23:30:56 +08:00
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u8 load_slb; /* Ages out SLB preload cache entries */
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2016-02-29 14:53:47 +08:00
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u8 load_fp;
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2005-04-17 06:20:36 +08:00
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#ifdef CONFIG_ALTIVEC
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2016-02-29 14:53:47 +08:00
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u8 load_vec;
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2013-09-10 18:20:42 +08:00
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struct thread_vr_state vr_state;
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2013-09-10 18:21:10 +08:00
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struct thread_vr_state *vr_save_area;
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2005-04-17 06:20:36 +08:00
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unsigned long vrsave;
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int used_vr; /* set if process has used altivec */
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#endif /* CONFIG_ALTIVEC */
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2008-06-25 12:07:18 +08:00
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#ifdef CONFIG_VSX
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/* VSR status */
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2016-03-25 01:12:21 +08:00
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int used_vsr; /* set if process has used VSX */
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2008-06-25 12:07:18 +08:00
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#endif /* CONFIG_VSX */
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2005-04-17 06:20:36 +08:00
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#ifdef CONFIG_SPE
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unsigned long evr[32]; /* upper 32-bits of SPE regs */
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u64 acc; /* Accumulator */
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unsigned long spefscr; /* SPE & eFP status */
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powerpc: fix exception clearing in e500 SPE float emulation
The e500 SPE floating-point emulation code clears existing exceptions
(__FPU_FPSCR &= ~FP_EX_MASK;) before ORing in the exceptions from the
emulated operation. However, these exception bits are the "sticky",
cumulative exception bits, and should only be cleared by the user
program setting SPEFSCR, not implicitly by any floating-point
instruction (whether executed purely by the hardware or emulated).
The spurious clearing of these bits shows up as missing exceptions in
glibc testing.
Fixing this, however, is not as simple as just not clearing the bits,
because while the bits may be from previous floating-point operations
(in which case they should not be cleared), the processor can also set
the sticky bits itself before the interrupt for an exception occurs,
and this can happen in cases when IEEE 754 semantics are that the
sticky bit should not be set. Specifically, the "invalid" sticky bit
is set in various cases with non-finite operands, where IEEE 754
semantics do not involve raising such an exception, and the
"underflow" sticky bit is set in cases of exact underflow, whereas
IEEE 754 semantics are that this flag is set only for inexact
underflow. Thus, for correct emulation the kernel needs to know the
setting of these two sticky bits before the instruction being
emulated.
When a floating-point operation raises an exception, the kernel can
note the state of the sticky bits immediately afterwards. Some
<fenv.h> functions that affect the state of these bits, such as
fesetenv and feholdexcept, need to use prctl with PR_GET_FPEXC and
PR_SET_FPEXC anyway, and so it is natural to record the state of those
bits during that call into the kernel and so avoid any need for a
separate call into the kernel to inform it of a change to those bits.
Thus, the interface I chose to use (in this patch and the glibc port)
is that one of those prctl calls must be made after any userspace
change to those sticky bits, other than through a floating-point
operation that traps into the kernel anyway. feclearexcept and
fesetexceptflag duly make those calls, which would not be required
were it not for this issue.
The previous EGLIBC port, and the uClibc code copied from it, is
fundamentally broken as regards any use of prctl for floating-point
exceptions because it didn't use the PR_FP_EXC_SW_ENABLE bit in its
prctl calls (and did various worse things, such as passing a pointer
when prctl expected an integer). If you avoid anything where prctl is
used, the clearing of sticky bits still means it will never give
anything approximating correct exception semantics with existing
kernels. I don't believe the patch makes things any worse for
existing code that doesn't try to inform the kernel of changes to
sticky bits - such code may get incorrect exceptions in some cases,
but it would have done so anyway in other cases.
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-12-11 07:07:45 +08:00
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unsigned long spefscr_last; /* SPEFSCR value on last prctl
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call or trap return */
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2005-04-17 06:20:36 +08:00
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int used_spe; /* set if process has used spe */
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#endif /* CONFIG_SPE */
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2013-02-14 00:21:31 +08:00
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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2016-09-14 16:02:16 +08:00
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u8 load_tm;
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2013-02-14 00:21:31 +08:00
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u64 tm_tfhar; /* Transaction fail handler addr */
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u64 tm_texasr; /* Transaction exception & summary */
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u64 tm_tfiar; /* Transaction fail instr address reg */
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struct pt_regs ckpt_regs; /* Checkpointed registers */
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2013-08-09 15:29:31 +08:00
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unsigned long tm_tar;
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unsigned long tm_ppr;
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unsigned long tm_dscr;
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2013-02-14 00:21:31 +08:00
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/*
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2016-09-23 14:18:24 +08:00
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* Checkpointed FP and VSX 0-31 register set.
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2013-02-14 00:21:31 +08:00
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*
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* When a transaction is active/signalled/scheduled etc., *regs is the
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* most recent set of/speculated GPRs with ckpt_regs being the older
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* checkpointed regs to which we roll back if transaction aborts.
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*
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2016-09-23 14:18:24 +08:00
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* These are analogous to how ckpt_regs and pt_regs work
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2013-02-14 00:21:31 +08:00
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*/
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2016-09-23 14:18:25 +08:00
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struct thread_fp_state ckfp_state; /* Checkpointed FP state */
|
|
|
|
|
struct thread_vr_state ckvr_state; /* Checkpointed VR state */
|
|
|
|
|
unsigned long ckvrsave; /* Checkpointed VRSAVE */
|
2013-02-14 00:21:31 +08:00
|
|
|
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
|
2018-01-19 09:50:31 +08:00
|
|
|
#ifdef CONFIG_PPC_MEM_KEYS
|
|
|
|
|
unsigned long amr;
|
|
|
|
|
unsigned long iamr;
|
|
|
|
|
unsigned long uamor;
|
|
|
|
|
#endif
|
2010-04-16 06:11:51 +08:00
|
|
|
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
|
|
|
|
|
void* kvm_shadow_vcpu; /* KVM internal data */
|
|
|
|
|
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
|
2011-12-20 23:34:43 +08:00
|
|
|
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
|
|
|
|
|
struct kvm_vcpu *kvm_vcpu;
|
|
|
|
|
#endif
|
2011-03-02 23:18:48 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
unsigned long dscr;
|
2015-10-29 08:43:55 +08:00
|
|
|
unsigned long fscr;
|
2015-05-21 14:43:04 +08:00
|
|
|
/*
|
|
|
|
|
* This member element dscr_inherit indicates that the process
|
|
|
|
|
* has explicitly attempted and changed the DSCR register value
|
|
|
|
|
* for itself. Hence kernel wont use the default CPU DSCR value
|
|
|
|
|
* contained in the PACA structure anymore during process context
|
|
|
|
|
* switch. Once this variable is set, this behaviour will also be
|
|
|
|
|
* inherited to all the children of this process from that point
|
|
|
|
|
* onwards.
|
|
|
|
|
*/
|
2011-03-02 23:18:48 +08:00
|
|
|
int dscr_inherit;
|
2017-11-08 10:23:53 +08:00
|
|
|
unsigned long tidr;
|
2011-03-02 23:18:48 +08:00
|
|
|
#endif
|
2013-02-07 23:46:58 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
unsigned long tar;
|
2013-05-01 04:17:04 +08:00
|
|
|
unsigned long ebbrr;
|
|
|
|
|
unsigned long ebbhr;
|
|
|
|
|
unsigned long bescr;
|
2013-05-22 00:31:12 +08:00
|
|
|
unsigned long siar;
|
|
|
|
|
unsigned long sdar;
|
|
|
|
|
unsigned long sier;
|
|
|
|
|
unsigned long mmcr2;
|
2013-06-28 16:15:16 +08:00
|
|
|
unsigned mmcr0;
|
2017-11-08 10:23:54 +08:00
|
|
|
|
2013-06-28 16:15:16 +08:00
|
|
|
unsigned used_ebb;
|
2017-11-08 10:23:54 +08:00
|
|
|
unsigned int used_vas;
|
2013-02-07 23:46:58 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define ARCH_MIN_TASKALIGN 16
|
|
|
|
|
|
|
|
|
|
#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
|
2019-01-31 18:09:00 +08:00
|
|
|
#define INIT_SP_LIMIT ((unsigned long)&init_stack)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-10-28 11:50:21 +08:00
|
|
|
#ifdef CONFIG_SPE
|
powerpc: fix exception clearing in e500 SPE float emulation
The e500 SPE floating-point emulation code clears existing exceptions
(__FPU_FPSCR &= ~FP_EX_MASK;) before ORing in the exceptions from the
emulated operation. However, these exception bits are the "sticky",
cumulative exception bits, and should only be cleared by the user
program setting SPEFSCR, not implicitly by any floating-point
instruction (whether executed purely by the hardware or emulated).
The spurious clearing of these bits shows up as missing exceptions in
glibc testing.
Fixing this, however, is not as simple as just not clearing the bits,
because while the bits may be from previous floating-point operations
(in which case they should not be cleared), the processor can also set
the sticky bits itself before the interrupt for an exception occurs,
and this can happen in cases when IEEE 754 semantics are that the
sticky bit should not be set. Specifically, the "invalid" sticky bit
is set in various cases with non-finite operands, where IEEE 754
semantics do not involve raising such an exception, and the
"underflow" sticky bit is set in cases of exact underflow, whereas
IEEE 754 semantics are that this flag is set only for inexact
underflow. Thus, for correct emulation the kernel needs to know the
setting of these two sticky bits before the instruction being
emulated.
When a floating-point operation raises an exception, the kernel can
note the state of the sticky bits immediately afterwards. Some
<fenv.h> functions that affect the state of these bits, such as
fesetenv and feholdexcept, need to use prctl with PR_GET_FPEXC and
PR_SET_FPEXC anyway, and so it is natural to record the state of those
bits during that call into the kernel and so avoid any need for a
separate call into the kernel to inform it of a change to those bits.
Thus, the interface I chose to use (in this patch and the glibc port)
is that one of those prctl calls must be made after any userspace
change to those sticky bits, other than through a floating-point
operation that traps into the kernel anyway. feclearexcept and
fesetexceptflag duly make those calls, which would not be required
were it not for this issue.
The previous EGLIBC port, and the uClibc code copied from it, is
fundamentally broken as regards any use of prctl for floating-point
exceptions because it didn't use the PR_FP_EXC_SW_ENABLE bit in its
prctl calls (and did various worse things, such as passing a pointer
when prctl expected an integer). If you avoid anything where prctl is
used, the clearing of sticky bits still means it will never give
anything approximating correct exception semantics with existing
kernels. I don't believe the patch makes things any worse for
existing code that doesn't try to inform the kernel of changes to
sticky bits - such code may get incorrect exceptions in some cases,
but it would have done so anyway in other cases.
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-12-11 07:07:45 +08:00
|
|
|
#define SPEFSCR_INIT \
|
|
|
|
|
.spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
|
|
|
|
|
.spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
|
2008-10-28 11:50:21 +08:00
|
|
|
#else
|
|
|
|
|
#define SPEFSCR_INIT
|
|
|
|
|
#endif
|
2005-10-10 12:19:43 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC32
|
2005-04-17 06:20:36 +08:00
|
|
|
#define INIT_THREAD { \
|
|
|
|
|
.ksp = INIT_SP, \
|
2008-04-28 14:21:22 +08:00
|
|
|
.ksp_limit = INIT_SP_LIMIT, \
|
2018-05-14 21:03:15 +08:00
|
|
|
.addr_limit = KERNEL_DS, \
|
2005-04-17 06:20:36 +08:00
|
|
|
.pgdir = swapper_pg_dir, \
|
|
|
|
|
.fpexc_mode = MSR_FE0 | MSR_FE1, \
|
2008-10-28 11:50:21 +08:00
|
|
|
SPEFSCR_INIT \
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2005-10-10 12:19:43 +08:00
|
|
|
#else
|
|
|
|
|
#define INIT_THREAD { \
|
|
|
|
|
.ksp = INIT_SP, \
|
|
|
|
|
.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
|
2018-05-14 21:03:15 +08:00
|
|
|
.addr_limit = KERNEL_DS, \
|
[POWERPC] disable floating point exceptions for init
Floating point exceptions should not be enabled by default,
as this setting impacts the performance on some CPUs, in
particular the Cell BE. Since the bits are inherited from
parent processes, the place to change the default is the
thread struct used for init.
glibc sets this up correctly per thread in its fesetenv
function, so user space should not be impacted by this
setting. None of the other common libc implementations
(uClibc, dietlibc, newlib, klibc) has support for fp
exceptions, so they are unlikely to be hit by this either.
There is a small risk that somebody wrote their own
application that manually sets the fpscr bits instead
of calling fesetenv, without changing the MSR bits as well.
Those programs will break with this change.
It probably makes sense to change glibc in the future
to be more clever about FE bits, so that when running
on a CPU where this is expensive, it disables exceptions
ASAP, while it keeps them enabled on CPUs where running
with exceptions on is cheaper than changing the state
often.
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-20 08:30:33 +08:00
|
|
|
.fpexc_mode = 0, \
|
2016-06-09 10:31:08 +08:00
|
|
|
.fscr = FSCR_TAR | FSCR_EBB \
|
2005-10-10 12:19:43 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-07-07 22:22:27 +08:00
|
|
|
#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long get_wchan(struct task_struct *p);
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
|
|
|
|
|
#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* Get/set floating-point exception mode */
|
2005-10-10 12:19:43 +08:00
|
|
|
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
|
|
|
|
|
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
|
|
|
|
|
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
|
|
|
|
|
|
2006-06-07 14:14:40 +08:00
|
|
|
#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
|
|
|
|
|
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
|
|
|
|
|
|
|
|
|
|
extern int get_endian(struct task_struct *tsk, unsigned long adr);
|
|
|
|
|
extern int set_endian(struct task_struct *tsk, unsigned int val);
|
|
|
|
|
|
2006-06-07 14:15:39 +08:00
|
|
|
#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
|
|
|
|
|
#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
|
|
|
|
|
|
|
|
|
|
extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
|
|
|
|
|
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
|
|
|
|
|
|
2013-09-10 18:21:10 +08:00
|
|
|
extern void load_fp_state(struct thread_fp_state *fp);
|
|
|
|
|
extern void store_fp_state(struct thread_fp_state *fp);
|
|
|
|
|
extern void load_vr_state(struct thread_vr_state *vr);
|
|
|
|
|
extern void store_vr_state(struct thread_vr_state *vr);
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline unsigned int __unpack_fe01(unsigned long msr_bits)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline unsigned long __pack_fe01(unsigned int fpmode)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
|
2017-06-06 21:08:31 +08:00
|
|
|
|
|
|
|
|
#define spin_begin() HMT_low()
|
|
|
|
|
|
|
|
|
|
#define spin_cpu_relax() barrier()
|
|
|
|
|
|
|
|
|
|
#define spin_end() HMT_medium()
|
|
|
|
|
|
|
|
|
|
#define spin_until_cond(cond) \
|
|
|
|
|
do { \
|
|
|
|
|
if (unlikely(!(cond))) { \
|
|
|
|
|
spin_begin(); \
|
|
|
|
|
do { \
|
|
|
|
|
spin_cpu_relax(); \
|
|
|
|
|
} while (!(cond)); \
|
|
|
|
|
spin_end(); \
|
|
|
|
|
} \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#else
|
2005-04-17 06:20:36 +08:00
|
|
|
#define cpu_relax() barrier()
|
2005-10-10 12:19:43 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-03-27 08:46:18 +08:00
|
|
|
/* Check that a certain kernel stack pointer is valid in task_struct p */
|
|
|
|
|
int validate_sp(unsigned long sp, struct task_struct *p,
|
|
|
|
|
unsigned long nbytes);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* Prefetch macros.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCH_HAS_PREFETCH
|
|
|
|
|
#define ARCH_HAS_PREFETCHW
|
|
|
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline void prefetch(const void *x)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-10-10 12:19:43 +08:00
|
|
|
if (unlikely(!x))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline void prefetchw(const void *x)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-10-10 12:19:43 +08:00
|
|
|
if (unlikely(!x))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define spin_lock_prefetch(x) prefetchw(x)
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#define HAVE_ARCH_PICK_MMAP_LAYOUT
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2009-03-25 14:23:59 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2013-05-27 02:09:41 +08:00
|
|
|
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
|
2009-03-25 14:23:59 +08:00
|
|
|
{
|
|
|
|
|
if (is_32)
|
2013-05-27 02:09:41 +08:00
|
|
|
return sp & 0x0ffffffffUL;
|
2009-03-25 14:23:59 +08:00
|
|
|
return sp;
|
|
|
|
|
}
|
|
|
|
|
#else
|
2013-05-27 02:09:41 +08:00
|
|
|
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
|
2009-03-25 14:23:59 +08:00
|
|
|
{
|
2013-05-27 02:09:41 +08:00
|
|
|
return sp;
|
2009-03-25 14:23:59 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
powerpc/64s: Reimplement book3s idle code in C
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack and reloading GPRs then
returning to C after waking from idle.
The complex logic dealing with threads and subcores, locking, SPRs,
HMIs, timebase resync, etc., is all done in C which makes it more
maintainable.
This is not a strict translation to C code, there are some
significant differences:
- Idle wakeup no longer uses the ->cpu_restore call to reinit SPRs,
but saves and restores them itself.
- The optimisation where EC=ESL=0 idle modes did not have to save GPRs
or change MSR is restored, because it's now simple to do. ESL=1
sleeps that do not lose GPRs can use this optimization too.
- KVM secondary entry and cede is now more of a call/return style
rather than branchy. nap_state_lost is not required because KVM
always returns via NVGPR restoring path.
- KVM secondary wakeup from offline sequence is moved entirely into
the offline wakeup, which avoids a hwsync in the normal idle wakeup
path.
Performance measured with context switch ping-pong on different
threads or cores, is possibly improved a small amount, 1-3% depending
on stop state and core vs thread test for shallow states. Deep states
it's in the noise compared with other latencies.
KVM improvements:
- Idle sleepers now always return to caller rather than branch out
to KVM first.
- This allows optimisations like very fast return to caller when no
state has been lost.
- KVM no longer requires nap_state_lost because it controls NVGPR
save/restore itself on the way in and out.
- The heavy idle wakeup KVM request check can be moved out of the
normal host idle code and into the not-performance-critical offline
code.
- KVM nap code now returns from where it is called, which makes the
flow a bit easier to follow.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Squash the KVM changes in]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-12 22:30:52 +08:00
|
|
|
/* asm stubs */
|
|
|
|
|
extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
|
|
|
|
|
extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
|
|
|
|
|
extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
|
|
|
|
|
|
2011-11-30 10:47:03 +08:00
|
|
|
extern unsigned long cpuidle_disable;
|
2011-11-30 10:46:31 +08:00
|
|
|
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
|
|
|
|
|
|
2012-03-29 01:30:02 +08:00
|
|
|
extern int powersave_nap; /* set if nap mode can be used in idle loop */
|
powerpc/64s: Reimplement book3s idle code in C
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack and reloading GPRs then
returning to C after waking from idle.
The complex logic dealing with threads and subcores, locking, SPRs,
HMIs, timebase resync, etc., is all done in C which makes it more
maintainable.
This is not a strict translation to C code, there are some
significant differences:
- Idle wakeup no longer uses the ->cpu_restore call to reinit SPRs,
but saves and restores them itself.
- The optimisation where EC=ESL=0 idle modes did not have to save GPRs
or change MSR is restored, because it's now simple to do. ESL=1
sleeps that do not lose GPRs can use this optimization too.
- KVM secondary entry and cede is now more of a call/return style
rather than branchy. nap_state_lost is not required because KVM
always returns via NVGPR restoring path.
- KVM secondary wakeup from offline sequence is moved entirely into
the offline wakeup, which avoids a hwsync in the normal idle wakeup
path.
Performance measured with context switch ping-pong on different
threads or cores, is possibly improved a small amount, 1-3% depending
on stop state and core vs thread test for shallow states. Deep states
it's in the noise compared with other latencies.
KVM improvements:
- Idle sleepers now always return to caller rather than branch out
to KVM first.
- This allows optimisations like very fast return to caller when no
state has been lost.
- KVM no longer requires nap_state_lost because it controls NVGPR
save/restore itself on the way in and out.
- The heavy idle wakeup KVM request check can be moved out of the
normal host idle code and into the not-performance-critical offline
code.
- KVM nap code now returns from where it is called, which makes the
flow a bit easier to follow.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Squash the KVM changes in]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-12 22:30:52 +08:00
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2017-06-13 21:05:45 +08:00
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extern void power7_idle_type(unsigned long type);
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extern void power9_idle_type(unsigned long stop_psscr_val,
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unsigned long stop_psscr_mask);
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2016-07-08 14:20:49 +08:00
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2012-03-29 01:30:02 +08:00
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extern void flush_instruction_cache(void);
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extern void hard_reset_now(void);
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extern void poweroff_now(void);
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extern int fix_alignment(struct pt_regs *);
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extern void cvt_fd(float *from, double *to);
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extern void cvt_df(double *from, float *to);
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extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
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#ifdef CONFIG_PPC64
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/*
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* We handle most unaligned accesses in hardware. On the other hand
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* unaligned DMA can be very expensive on some ppc64 IO chips (it does
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* powers of 2 writes until it reaches sufficient alignment).
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*
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* Based on this we disable the IP header alignment in network drivers.
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*/
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#define NET_IP_ALIGN 0
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#endif
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2005-04-17 06:20:36 +08:00
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#endif /* __KERNEL__ */
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2005-10-10 12:19:43 +08:00
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PROCESSOR_H */
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