2005-04-17 06:20:36 +08:00
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/*
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* SNI specific definitions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997, 1998 by Ralf Baechle
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*/
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#ifndef __ASM_SNI_H
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#define __ASM_SNI_H
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#define SNI_PORT_BASE 0xb4000000
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/*
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* ASIC PCI registers for little endian configuration.
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*/
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#define PCIMT_UCONF 0xbfff0000
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#define PCIMT_IOADTIMEOUT2 0xbfff0008
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#define PCIMT_IOMEMCONF 0xbfff0010
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#define PCIMT_IOMMU 0xbfff0018
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#define PCIMT_IOADTIMEOUT1 0xbfff0020
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#define PCIMT_DMAACCESS 0xbfff0028
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#define PCIMT_DMAHIT 0xbfff0030
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#define PCIMT_ERRSTATUS 0xbfff0038
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#define PCIMT_ERRADDR 0xbfff0040
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#define PCIMT_SYNDROME 0xbfff0048
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#define PCIMT_ITPEND 0xbfff0050
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#define IT_INT2 0x01
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#define IT_INTD 0x02
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#define IT_INTC 0x04
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#define IT_INTB 0x08
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#define IT_INTA 0x10
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#define IT_EISA 0x20
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#define IT_SCSI 0x40
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#define IT_ETH 0x80
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#define PCIMT_IRQSEL 0xbfff0058
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#define PCIMT_TESTMEM 0xbfff0060
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#define PCIMT_ECCREG 0xbfff0068
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#define PCIMT_CONFIG_ADDRESS 0xbfff0070
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#define PCIMT_ASIC_ID 0xbfff0078 /* read */
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#define PCIMT_SOFT_RESET 0xbfff0078 /* write */
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#define PCIMT_PIA_OE 0xbfff0080
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#define PCIMT_PIA_DATAOUT 0xbfff0088
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#define PCIMT_PIA_DATAIN 0xbfff0090
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#define PCIMT_CACHECONF 0xbfff0098
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#define PCIMT_INVSPACE 0xbfff00a0
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#define PCIMT_PCI_CONF 0xbfff0100
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/*
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2006-06-13 19:59:01 +08:00
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* Data port for the PCI bus in IO space
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2005-04-17 06:20:36 +08:00
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*/
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2006-06-13 19:59:01 +08:00
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#define PCIMT_CONFIG_DATA 0x0cfc
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2005-04-17 06:20:36 +08:00
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/*
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* Board specific registers
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*/
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#define PCIMT_CSMSR 0xbfd00000
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#define PCIMT_CSSWITCH 0xbfd10000
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#define PCIMT_CSITPEND 0xbfd20000
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#define PCIMT_AUTO_PO_EN 0xbfd30000
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#define PCIMT_CLR_TEMP 0xbfd40000
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#define PCIMT_AUTO_PO_DIS 0xbfd50000
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#define PCIMT_EXMSR 0xbfd60000
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#define PCIMT_UNUSED1 0xbfd70000
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#define PCIMT_CSWCSM 0xbfd80000
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#define PCIMT_UNUSED2 0xbfd90000
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#define PCIMT_CSLED 0xbfda0000
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#define PCIMT_CSMAPISA 0xbfdb0000
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#define PCIMT_CSRSTBP 0xbfdc0000
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#define PCIMT_CLRPOFF 0xbfdd0000
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#define PCIMT_CSTIMER 0xbfde0000
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#define PCIMT_PWDN 0xbfdf0000
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/*
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* Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
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* to the other interrupts generated by ASIC PCI.
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*
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* INT2 is a wired-or of the push button interrupt, high temperature interrupt
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* ASIC PCI interrupt.
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*/
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#define PCIMT_KEYBOARD_IRQ 1
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#define PCIMT_IRQ_INT2 16
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#define PCIMT_IRQ_INTD 17
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#define PCIMT_IRQ_INTC 18
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#define PCIMT_IRQ_INTB 19
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#define PCIMT_IRQ_INTA 20
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#define PCIMT_IRQ_EISA 21
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#define PCIMT_IRQ_SCSI 22
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#define PCIMT_IRQ_ETHERNET 23
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#define PCIMT_IRQ_TEMPERATURE 24
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#define PCIMT_IRQ_EISA_NMI 25
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#define PCIMT_IRQ_POWER_OFF 26
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#define PCIMT_IRQ_BUTTON 27
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/*
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* Base address for the mapped 16mb EISA bus segment.
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*/
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#define PCIMT_EISA_BASE 0xb0000000
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/* PCI EISA Interrupt acknowledge */
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#define PCIMT_INT_ACKNOWLEDGE 0xba000000
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#endif /* __ASM_SNI_H */
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