2013-10-08 12:50:06 +08:00
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/dts-v1/;
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2013-12-20 00:06:19 +08:00
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#include <dt-bindings/input/input.h>
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2013-10-08 12:50:06 +08:00
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#include "tegra124.dtsi"
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/ {
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model = "NVIDIA Tegra124 Venice2";
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compatible = "nvidia,venice2", "nvidia,tegra124";
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2013-12-20 02:32:15 +08:00
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aliases {
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rtc0 = "/i2c@7000d000/as3722@40";
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rtc1 = "/rtc@7000e000";
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};
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2013-10-08 12:50:06 +08:00
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memory {
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reg = <0x80000000 0x80000000>;
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};
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2013-12-09 18:33:51 +08:00
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pinmux: pinmux@70000868 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_default>;
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pinmux_default: common {
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dap_mclk1_pw4 {
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nvidia,pins = "dap_mclk1_pw4";
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nvidia,function = "extperiph1";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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dap1_din_pn1 {
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2013-12-18 20:52:58 +08:00
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nvidia,pins = "dap1_din_pn1";
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nvidia,function = "i2s0";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dap1_dout_pn2 {
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nvidia,pins = "dap1_dout_pn2",
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2013-12-09 18:33:51 +08:00
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"dap1_fs_pn0",
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"dap1_sclk_pn3";
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nvidia,function = "i2s0";
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2013-12-18 20:52:58 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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2013-12-09 18:33:51 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dap2_din_pa4 {
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2013-12-18 20:52:58 +08:00
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nvidia,pins = "dap2_din_pa4";
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2013-12-09 18:33:51 +08:00
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nvidia,function = "i2s1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2013-12-13 05:40:30 +08:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2013-12-09 18:33:51 +08:00
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};
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2013-12-18 20:52:58 +08:00
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dap2_dout_pa5 {
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nvidia,pins = "dap2_dout_pa5",
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"dap2_fs_pa2",
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"dap2_sclk_pa3";
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nvidia,function = "i2s1";
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2013-12-09 18:33:51 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2013-12-18 20:52:58 +08:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2013-12-09 18:33:51 +08:00
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};
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2013-12-18 20:52:58 +08:00
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dvfs_pwm_px0 {
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nvidia,pins = "dvfs_pwm_px0",
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"dvfs_clk_px2";
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2013-12-09 18:33:51 +08:00
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nvidia,function = "cldvfs";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi_clk_py0 {
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nvidia,pins = "ulpi_clk_py0",
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"ulpi_nxt_py2",
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"ulpi_stp_py3";
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nvidia,function = "spi1";
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2013-12-18 20:52:58 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi_dir_py1 {
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nvidia,pins = "ulpi_dir_py1";
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nvidia,function = "spi1";
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2013-12-09 18:33:51 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2013-12-18 20:52:58 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2013-12-09 18:33:51 +08:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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cam_i2c_scl_pbb1 {
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nvidia,pins = "cam_i2c_scl_pbb1",
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"cam_i2c_sda_pbb2";
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nvidia,function = "i2c3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gen2_i2c_scl_pt5 {
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nvidia,pins = "gen2_i2c_scl_pt5",
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"gen2_i2c_sda_pt6";
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nvidia,function = "i2c2";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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pg4 {
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nvidia,pins = "pg4",
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"pg5",
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"pg6",
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"pi3";
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nvidia,function = "spi4";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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2013-12-18 20:52:58 +08:00
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pg7 {
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nvidia,pins = "pg7";
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nvidia,function = "spi4";
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2013-12-09 18:33:51 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2013-12-18 20:52:58 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2013-12-09 18:33:51 +08:00
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};
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ph1 {
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nvidia,pins = "ph1";
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nvidia,function = "pwm1";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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2013-12-18 20:52:58 +08:00
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pk0 {
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nvidia,pins = "pk0",
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"kb_row15_ps7",
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"clk_32k_out_pa0";
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nvidia,function = "soc";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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2013-12-14 00:25:04 +08:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2013-12-18 20:52:58 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2013-12-14 00:25:04 +08:00
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};
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2013-12-09 18:33:51 +08:00
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sdmmc1_clk_pz0 {
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nvidia,pins = "sdmmc1_clk_pz0",
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"sdmmc1_cmd_pz1",
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"sdmmc1_dat0_py7",
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"sdmmc1_dat1_py6",
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"sdmmc1_dat2_py5",
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"sdmmc1_dat3_py4";
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nvidia,function = "sdmmc1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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2013-12-18 20:52:58 +08:00
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sdmmc1_cmd_pz1 {
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nvidia,pins = "sdmmc1_cmd_pz1",
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"sdmmc1_dat0_py7",
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"sdmmc1_dat1_py6",
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"sdmmc1_dat2_py5",
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"sdmmc1_dat3_py4";
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nvidia,function = "sdmmc1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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2013-12-09 18:33:51 +08:00
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sdmmc3_clk_pa6 {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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sdmmc3_cmd_pa7 {
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nvidia,pins = "sdmmc3_cmd_pa7",
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"sdmmc3_dat0_pb7",
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"sdmmc3_dat1_pb6",
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"sdmmc3_dat2_pb5",
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"sdmmc3_dat3_pb4",
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"sdmmc3_clk_lb_out_pee4",
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"sdmmc3_clk_lb_in_pee5";
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nvidia,function = "sdmmc3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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sdmmc4_clk_pcc4 {
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nvidia,pins = "sdmmc4_clk_pcc4";
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nvidia,function = "sdmmc4";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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sdmmc4_cmd_pt7 {
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nvidia,pins = "sdmmc4_cmd_pt7",
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"sdmmc4_dat0_paa0",
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"sdmmc4_dat1_paa1",
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"sdmmc4_dat2_paa2",
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"sdmmc4_dat3_paa3",
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"sdmmc4_dat4_paa4",
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"sdmmc4_dat5_paa5",
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"sdmmc4_dat6_paa6",
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"sdmmc4_dat7_paa7";
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nvidia,function = "sdmmc4";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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pwr_i2c_scl_pz6 {
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nvidia,pins = "pwr_i2c_scl_pz6",
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"pwr_i2c_sda_pz7";
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nvidia,function = "i2cpwr";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2013-12-18 20:52:58 +08:00
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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2013-12-09 18:33:51 +08:00
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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jtag_rtck {
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nvidia,pins = "jtag_rtck";
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nvidia,function = "rtck";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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clk_32k_in {
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nvidia,pins = "clk_32k_in";
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nvidia,function = "clk";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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core_pwr_req {
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nvidia,pins = "core_pwr_req";
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nvidia,function = "pwron";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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cpu_pwr_req {
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nvidia,pins = "cpu_pwr_req";
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nvidia,function = "cpu";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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pwr_int_n {
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nvidia,pins = "pwr_int_n";
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nvidia,function = "pmi";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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reset_out_n {
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nvidia,pins = "reset_out_n";
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nvidia,function = "reset_out_n";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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clk3_out_pee0 {
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nvidia,pins = "clk3_out_pee0";
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nvidia,function = "extperiph3";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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dap4_din_pp5 {
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2013-12-18 20:52:58 +08:00
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nvidia,pins = "dap4_din_pp5";
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nvidia,function = "i2s3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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|
dap4_dout_pp6 {
|
|
|
|
|
nvidia,pins = "dap4_dout_pp6",
|
2013-12-09 18:33:51 +08:00
|
|
|
"dap4_fs_pp4",
|
|
|
|
|
"dap4_sclk_pp7";
|
|
|
|
|
nvidia,function = "i2s3";
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
gen1_i2c_sda_pc5 {
|
|
|
|
|
nvidia,pins = "gen1_i2c_sda_pc5",
|
|
|
|
|
"gen1_i2c_scl_pc4";
|
|
|
|
|
nvidia,function = "i2c1";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
};
|
2013-12-18 20:52:58 +08:00
|
|
|
uart2_cts_n_pj5 {
|
|
|
|
|
nvidia,pins = "uart2_cts_n_pj5";
|
|
|
|
|
nvidia,function = "uartb";
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-13 05:40:30 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 20:52:58 +08:00
|
|
|
uart2_rts_n_pj6 {
|
|
|
|
|
nvidia,pins = "uart2_rts_n_pj6";
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,function = "uartb";
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
uart2_rxd_pc3 {
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,pins = "uart2_rxd_pc3";
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,function = "irda";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 20:52:58 +08:00
|
|
|
uart2_txd_pc2 {
|
|
|
|
|
nvidia,pins = "uart2_txd_pc2";
|
|
|
|
|
nvidia,function = "irda";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-09 18:33:51 +08:00
|
|
|
uart3_cts_n_pa1 {
|
|
|
|
|
nvidia,pins = "uart3_cts_n_pa1",
|
2013-12-18 20:52:58 +08:00
|
|
|
"uart3_rxd_pw7";
|
2013-12-09 18:33:51 +08:00
|
|
|
nvidia,function = "uartc";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 20:52:58 +08:00
|
|
|
uart3_rts_n_pc0 {
|
|
|
|
|
nvidia,pins = "uart3_rts_n_pc0",
|
|
|
|
|
"uart3_txd_pw6";
|
|
|
|
|
nvidia,function = "uartc";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-09 18:33:51 +08:00
|
|
|
hdmi_cec_pee3 {
|
|
|
|
|
nvidia,pins = "hdmi_cec_pee3";
|
|
|
|
|
nvidia,function = "cec";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
hdmi_int_pn7 {
|
|
|
|
|
nvidia,pins = "hdmi_int_pn7";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
};
|
|
|
|
|
ddc_scl_pv4 {
|
|
|
|
|
nvidia,pins = "ddc_scl_pv4",
|
|
|
|
|
"ddc_sda_pv5";
|
|
|
|
|
nvidia,function = "i2c4";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pj7 {
|
|
|
|
|
nvidia,pins = "pj7",
|
|
|
|
|
"pk7";
|
|
|
|
|
nvidia,function = "uartd";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
pb0 {
|
|
|
|
|
nvidia,pins = "pb0",
|
|
|
|
|
"pb1";
|
|
|
|
|
nvidia,function = "uartd";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ph0 {
|
|
|
|
|
nvidia,pins = "ph0";
|
|
|
|
|
nvidia,function = "pwm0";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row10_ps2 {
|
|
|
|
|
nvidia,pins = "kb_row10_ps2";
|
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row9_ps1 {
|
|
|
|
|
nvidia,pins = "kb_row9_ps1";
|
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row6_pr6 {
|
|
|
|
|
nvidia,pins = "kb_row6_pr6";
|
|
|
|
|
nvidia,function = "displaya_alt";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
};
|
|
|
|
|
usb_vbus_en0_pn4 {
|
|
|
|
|
nvidia,pins = "usb_vbus_en0_pn4";
|
|
|
|
|
nvidia,function = "usb";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
};
|
|
|
|
|
usb_vbus_en1_pn5 {
|
|
|
|
|
nvidia,pins = "usb_vbus_en1_pn5";
|
|
|
|
|
nvidia,function = "usb";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
2013-12-18 20:52:58 +08:00
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2013-12-09 18:33:51 +08:00
|
|
|
};
|
|
|
|
|
drive_sdio1 {
|
|
|
|
|
nvidia,pins = "drive_sdio1";
|
|
|
|
|
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
|
|
|
|
nvidia,pull-down-strength = <32>;
|
|
|
|
|
nvidia,pull-up-strength = <42>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
};
|
|
|
|
|
drive_sdio3 {
|
|
|
|
|
nvidia,pins = "drive_sdio3";
|
|
|
|
|
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
|
|
|
|
nvidia,pull-down-strength = <20>;
|
|
|
|
|
nvidia,pull-up-strength = <36>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
};
|
|
|
|
|
drive_gma {
|
|
|
|
|
nvidia,pins = "drive_gma";
|
|
|
|
|
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
|
|
|
|
nvidia,pull-down-strength = <1>;
|
|
|
|
|
nvidia,pull-up-strength = <2>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,drive-type = <1>;
|
|
|
|
|
};
|
2013-12-18 20:52:58 +08:00
|
|
|
als_irq_l {
|
|
|
|
|
nvidia,pins = "gpio_x3_aud_px3";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
codec_irq_l {
|
|
|
|
|
nvidia,pins = "ph4";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
lcd_bl_en {
|
|
|
|
|
nvidia,pins = "ph2";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
touch_irq_l {
|
|
|
|
|
nvidia,pins = "gpio_w3_aud_pw3";
|
|
|
|
|
nvidia,function = "spi6";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
tpm_davint_l {
|
|
|
|
|
nvidia,pins = "ph6";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ts_irq_l {
|
|
|
|
|
nvidia,pins = "pk2";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ts_reset_l {
|
|
|
|
|
nvidia,pins = "pk4";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ts_shdn_l {
|
|
|
|
|
nvidia,pins = "pk1";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ph7 {
|
|
|
|
|
nvidia,pins = "ph7";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_col0_ap {
|
|
|
|
|
nvidia,pins = "kb_col0_pq0";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
lid_open {
|
|
|
|
|
nvidia,pins = "kb_row4_pr4";
|
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
en_vdd_sd {
|
|
|
|
|
nvidia,pins = "kb_row0_pr0";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ac_ok {
|
|
|
|
|
nvidia,pins = "pj0";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sensor_irq_l {
|
|
|
|
|
nvidia,pins = "pi6";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
wifi_en {
|
|
|
|
|
nvidia,pins = "gpio_x7_aud_px7";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
wifi_rst_l {
|
|
|
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
|
|
|
nvidia,function = "dap";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
hp_det_l {
|
|
|
|
|
nvidia,pins = "ulpi_data1_po2";
|
|
|
|
|
nvidia,function = "spi3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
2013-12-09 18:33:51 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-08 12:50:06 +08:00
|
|
|
serial@70006000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-19 00:00:35 +08:00
|
|
|
pwm: pwm@7000a000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-04 07:44:35 +08:00
|
|
|
i2c@7000c000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
2013-12-04 08:26:12 +08:00
|
|
|
|
|
|
|
|
acodec: audio-codec@10 {
|
|
|
|
|
compatible = "maxim,max98090";
|
|
|
|
|
reg = <0x10>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
};
|
2013-12-04 07:44:35 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c400 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c500 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c700 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000d000 {
|
|
|
|
|
status = "okay";
|
2013-12-18 20:52:59 +08:00
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
|
|
|
|
|
as3722: as3722@40 {
|
|
|
|
|
compatible = "ams,as3722";
|
|
|
|
|
reg = <0x40>;
|
|
|
|
|
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&as3722_default>;
|
|
|
|
|
|
|
|
|
|
as3722_default: pinmux {
|
|
|
|
|
gpio0 {
|
|
|
|
|
pins = "gpio0";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
bias-pull-down;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1_2_4_7 {
|
|
|
|
|
pins = "gpio1", "gpio2", "gpio4", "gpio7";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3_6 {
|
|
|
|
|
pins = "gpio3", "gpio6";
|
|
|
|
|
bias-high-impedance;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio5 {
|
|
|
|
|
pins = "gpio5";
|
|
|
|
|
function = "clk32k-out";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
regulators {
|
|
|
|
|
vsup-sd2-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vsup-sd3-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vsup-sd4-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vsup-sd5-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vin-ldo0-supply = <&as3722_sd2>;
|
|
|
|
|
vin-ldo1-6-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vin-ldo2-5-7-supply = <&as3722_sd5>;
|
|
|
|
|
vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
vin-ldo11-supply = <&vdd_ac_bat_reg>;
|
|
|
|
|
|
|
|
|
|
sd0 {
|
|
|
|
|
regulator-name = "vdd-cpu";
|
|
|
|
|
regulator-min-microvolt = <700000>;
|
|
|
|
|
regulator-max-microvolt = <1400000>;
|
|
|
|
|
regulator-min-microamp = <3500000>;
|
|
|
|
|
regulator-max-microamp = <3500000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
ams,external-control = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd1 {
|
|
|
|
|
regulator-name = "vdd-core";
|
|
|
|
|
regulator-min-microvolt = <700000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-min-microamp = <2500000>;
|
|
|
|
|
regulator-max-microamp = <2500000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
ams,external-control = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
as3722_sd2: sd2 {
|
|
|
|
|
regulator-name = "vddio-ddr";
|
|
|
|
|
regulator-min-microvolt = <1350000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd3 {
|
|
|
|
|
regulator-name = "vddio-ddr-2phase";
|
|
|
|
|
regulator-min-microvolt = <1350000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd4 {
|
|
|
|
|
regulator-name = "avdd-pex-sata";
|
|
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
as3722_sd5: sd5 {
|
|
|
|
|
regulator-name = "vddio-sys";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd6 {
|
|
|
|
|
regulator-name = "vdd-gpu";
|
|
|
|
|
regulator-min-microvolt = <650000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
regulator-min-microamp = <3500000>;
|
|
|
|
|
regulator-max-microamp = <3500000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo0 {
|
|
|
|
|
regulator-name = "avdd_pll";
|
|
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
ams,external-control = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo1 {
|
|
|
|
|
regulator-name = "run-cam-1.8";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo2 {
|
|
|
|
|
regulator-name = "gen-avdd,vddio-hsic";
|
|
|
|
|
regulator-min-microvolt = <1200000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo3 {
|
|
|
|
|
regulator-name = "vdd-rtc";
|
|
|
|
|
regulator-min-microvolt = <1000000>;
|
|
|
|
|
regulator-max-microvolt = <1000000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
ams,enable-tracking;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo4 {
|
|
|
|
|
regulator-name = "vdd-cam";
|
|
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo5 {
|
|
|
|
|
regulator-name = "vdd-cam-front";
|
|
|
|
|
regulator-min-microvolt = <1200000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo6 {
|
|
|
|
|
regulator-name = "vddio-sdmmc3";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo7 {
|
|
|
|
|
regulator-name = "vdd-cam-rear";
|
|
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo9 {
|
|
|
|
|
regulator-name = "vdd-touch";
|
|
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo10 {
|
|
|
|
|
regulator-name = "vdd-cam-af";
|
|
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo11 {
|
|
|
|
|
regulator-name = "vpp-fuse";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-12-04 07:44:35 +08:00
|
|
|
};
|
|
|
|
|
|
2013-12-20 00:06:19 +08:00
|
|
|
spi@7000d400 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
cros-ec@0 {
|
|
|
|
|
compatible = "google,cros-ec-spi";
|
|
|
|
|
spi-max-frequency = <4000000>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
|
reg = <0>;
|
|
|
|
|
|
|
|
|
|
google,cros-ec-spi-msg-delay = <2000>;
|
|
|
|
|
|
|
|
|
|
cros-ec-keyb {
|
|
|
|
|
compatible = "google,cros-ec-keyb";
|
|
|
|
|
keypad,num-rows = <8>;
|
|
|
|
|
keypad,num-columns = <13>;
|
|
|
|
|
google,needs-ghost-filter;
|
|
|
|
|
|
|
|
|
|
linux,keymap = <
|
|
|
|
|
MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
|
|
|
|
|
MATRIX_KEY(0x00, 0x02, KEY_F1)
|
|
|
|
|
MATRIX_KEY(0x00, 0x03, KEY_B)
|
|
|
|
|
MATRIX_KEY(0x00, 0x04, KEY_F10)
|
|
|
|
|
MATRIX_KEY(0x00, 0x06, KEY_N)
|
|
|
|
|
MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
|
|
|
|
|
MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x01, 0x01, KEY_ESC)
|
|
|
|
|
MATRIX_KEY(0x01, 0x02, KEY_F4)
|
|
|
|
|
MATRIX_KEY(0x01, 0x03, KEY_G)
|
|
|
|
|
MATRIX_KEY(0x01, 0x04, KEY_F7)
|
|
|
|
|
MATRIX_KEY(0x01, 0x06, KEY_H)
|
|
|
|
|
MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
|
|
|
|
|
MATRIX_KEY(0x01, 0x09, KEY_F9)
|
|
|
|
|
MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
|
|
|
|
|
MATRIX_KEY(0x02, 0x01, KEY_TAB)
|
|
|
|
|
MATRIX_KEY(0x02, 0x02, KEY_F3)
|
|
|
|
|
MATRIX_KEY(0x02, 0x03, KEY_T)
|
|
|
|
|
MATRIX_KEY(0x02, 0x04, KEY_F6)
|
|
|
|
|
MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
|
|
|
|
|
MATRIX_KEY(0x02, 0x06, KEY_Y)
|
|
|
|
|
MATRIX_KEY(0x02, 0x07, KEY_102ND)
|
|
|
|
|
MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
|
|
|
|
|
MATRIX_KEY(0x02, 0x09, KEY_F8)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
|
|
|
|
|
MATRIX_KEY(0x03, 0x02, KEY_F2)
|
|
|
|
|
MATRIX_KEY(0x03, 0x03, KEY_5)
|
|
|
|
|
MATRIX_KEY(0x03, 0x04, KEY_F5)
|
|
|
|
|
MATRIX_KEY(0x03, 0x06, KEY_6)
|
|
|
|
|
MATRIX_KEY(0x03, 0x08, KEY_MINUS)
|
|
|
|
|
MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
|
|
|
|
|
MATRIX_KEY(0x04, 0x01, KEY_A)
|
|
|
|
|
MATRIX_KEY(0x04, 0x02, KEY_D)
|
|
|
|
|
MATRIX_KEY(0x04, 0x03, KEY_F)
|
|
|
|
|
MATRIX_KEY(0x04, 0x04, KEY_S)
|
|
|
|
|
MATRIX_KEY(0x04, 0x05, KEY_K)
|
|
|
|
|
MATRIX_KEY(0x04, 0x06, KEY_J)
|
|
|
|
|
MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
|
|
|
|
|
MATRIX_KEY(0x04, 0x09, KEY_L)
|
|
|
|
|
MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
|
|
|
|
|
MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x05, 0x01, KEY_Z)
|
|
|
|
|
MATRIX_KEY(0x05, 0x02, KEY_C)
|
|
|
|
|
MATRIX_KEY(0x05, 0x03, KEY_V)
|
|
|
|
|
MATRIX_KEY(0x05, 0x04, KEY_X)
|
|
|
|
|
MATRIX_KEY(0x05, 0x05, KEY_COMMA)
|
|
|
|
|
MATRIX_KEY(0x05, 0x06, KEY_M)
|
|
|
|
|
MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
|
|
|
|
|
MATRIX_KEY(0x05, 0x08, KEY_SLASH)
|
|
|
|
|
MATRIX_KEY(0x05, 0x09, KEY_DOT)
|
|
|
|
|
MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x06, 0x01, KEY_1)
|
|
|
|
|
MATRIX_KEY(0x06, 0x02, KEY_3)
|
|
|
|
|
MATRIX_KEY(0x06, 0x03, KEY_4)
|
|
|
|
|
MATRIX_KEY(0x06, 0x04, KEY_2)
|
|
|
|
|
MATRIX_KEY(0x06, 0x05, KEY_8)
|
|
|
|
|
MATRIX_KEY(0x06, 0x06, KEY_7)
|
|
|
|
|
MATRIX_KEY(0x06, 0x08, KEY_0)
|
|
|
|
|
MATRIX_KEY(0x06, 0x09, KEY_9)
|
|
|
|
|
MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
|
|
|
|
|
MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
|
|
|
|
|
MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x07, 0x01, KEY_Q)
|
|
|
|
|
MATRIX_KEY(0x07, 0x02, KEY_E)
|
|
|
|
|
MATRIX_KEY(0x07, 0x03, KEY_R)
|
|
|
|
|
MATRIX_KEY(0x07, 0x04, KEY_W)
|
|
|
|
|
MATRIX_KEY(0x07, 0x05, KEY_I)
|
|
|
|
|
MATRIX_KEY(0x07, 0x06, KEY_U)
|
|
|
|
|
MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
|
|
|
|
|
MATRIX_KEY(0x07, 0x08, KEY_P)
|
|
|
|
|
MATRIX_KEY(0x07, 0x09, KEY_O)
|
|
|
|
|
MATRIX_KEY(0x07, 0x0b, KEY_UP)
|
|
|
|
|
MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-08 12:50:06 +08:00
|
|
|
pmc@7000e400 {
|
|
|
|
|
nvidia,invert-interrupt;
|
2013-10-11 17:58:39 +08:00
|
|
|
nvidia,suspend-mode = <1>;
|
|
|
|
|
nvidia,cpu-pwr-good-time = <500>;
|
|
|
|
|
nvidia,cpu-pwr-off-time = <300>;
|
|
|
|
|
nvidia,core-pwr-good-time = <641 3845>;
|
|
|
|
|
nvidia,core-pwr-off-time = <61036>;
|
|
|
|
|
nvidia,core-power-req-active-high;
|
|
|
|
|
nvidia,sys-clock-req-active-high;
|
2013-10-08 12:50:06 +08:00
|
|
|
};
|
2013-10-08 15:47:40 +08:00
|
|
|
|
2013-11-01 07:23:05 +08:00
|
|
|
sdhci@700b0400 {
|
|
|
|
|
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdhci@700b0600 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-04 08:26:12 +08:00
|
|
|
ahub@70300000 {
|
|
|
|
|
i2s@70301100 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-08 15:47:40 +08:00
|
|
|
clocks {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
clk32k_in: clock@0 {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
reg=<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-12-04 08:26:12 +08:00
|
|
|
|
2013-12-20 00:06:20 +08:00
|
|
|
gpio-keys {
|
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
|
|
|
|
power {
|
|
|
|
|
label = "Power";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
|
|
|
|
|
linux,code = <KEY_POWER>;
|
|
|
|
|
debounce-interval = <10>;
|
|
|
|
|
gpio-key,wakeup;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-18 20:52:59 +08:00
|
|
|
regulators {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
vdd_ac_bat_reg: regulator@0 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
regulator-name = "vdd_ac_bat";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_3v3_reg: regulator@1 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
regulator-name = "vdd_3v3";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_3v3_modem_reg: regulator@2 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
regulator-name = "vdd-modem-3v3";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_hdmi_5v0_reg: regulator@3 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <3>;
|
|
|
|
|
regulator-name = "vdd-hdmi-5v0";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_bl_reg: regulator@4 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <4>;
|
|
|
|
|
regulator-name = "vdd-bl";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_ts_sw_5v0: regulator@5 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <5>;
|
|
|
|
|
regulator-name = "vdd_ts_sw";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_vbus_reg: regulator@6 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <6>;
|
|
|
|
|
regulator-name = "usb1_vbus";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
gpio-open-drain;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb3_vbus_reg: regulator@7 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <7>;
|
|
|
|
|
regulator-name = "usb3_vbus";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
gpio-open-drain;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
panel_3v3_reg: regulator@8 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <8>;
|
|
|
|
|
regulator-name = "panel_3v3";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-04 08:26:12 +08:00
|
|
|
sound {
|
|
|
|
|
compatible = "nvidia,tegra-audio-max98090-venice2",
|
|
|
|
|
"nvidia,tegra-audio-max98090";
|
|
|
|
|
nvidia,model = "NVIDIA Tegra Venice2";
|
|
|
|
|
|
|
|
|
|
nvidia,audio-routing =
|
|
|
|
|
"Headphones", "HPR",
|
|
|
|
|
"Headphones", "HPL",
|
|
|
|
|
"Speakers", "SPKR",
|
|
|
|
|
"Speakers", "SPKL",
|
|
|
|
|
"Mic Jack", "MICBIAS",
|
|
|
|
|
"IN34", "Mic Jack";
|
|
|
|
|
|
|
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
|
|
|
nvidia,audio-codec = <&acodec>;
|
|
|
|
|
|
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
|
|
|
|
|
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_car TEGRA124_CLK_EXTERN1>;
|
|
|
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
|
|
|
};
|
2013-10-08 12:50:06 +08:00
|
|
|
};
|
