2018-05-15 04:04:57 +08:00
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include "ocelot.h"
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u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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u32 val;
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WARN_ON(!target);
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regmap_read(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset, &val);
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return val;
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}
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EXPORT_SYMBOL(__ocelot_read_ix);
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void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_write(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset, val);
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}
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EXPORT_SYMBOL(__ocelot_write_ix);
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void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
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u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_update_bits(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset,
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mask, val);
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}
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EXPORT_SYMBOL(__ocelot_rmw_ix);
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u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
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{
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2020-07-14 00:57:01 +08:00
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struct ocelot *ocelot = port->ocelot;
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u16 target = reg >> TARGET_OFFSET;
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u32 val;
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WARN_ON(!target);
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regmap_read(port->target, ocelot->map[target][reg & REG_MASK], &val);
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return val;
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2018-05-15 04:04:57 +08:00
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}
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EXPORT_SYMBOL(ocelot_port_readl);
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void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg)
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{
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2020-07-14 00:57:01 +08:00
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struct ocelot *ocelot = port->ocelot;
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_write(port->target, ocelot->map[target][reg & REG_MASK], val);
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2018-05-15 04:04:57 +08:00
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}
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EXPORT_SYMBOL(ocelot_port_writel);
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net: mscc: ocelot: introduce a new ocelot_target_{read,write} API
There are some targets (register blocks) in the Ocelot switch that are
instantiated more than once. For example, the VCAP IS1, IS2 and ES0
blocks all share the same register layout for interacting with the cache
for the TCAM and the action RAM.
For the VCAPs, the procedure for servicing them is actually common. We
just need an API specifying which VCAP we are talking to, and we do that
via these raw ocelot_target_read and ocelot_target_write accessors.
In plain ocelot_read, the target is encoded into the register enum
itself:
u16 target = reg >> TARGET_OFFSET;
For the VCAPs, the registers are currently defined like this:
enum ocelot_reg {
[...]
S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
S2_CORE_MV_CFG,
S2_CACHE_ENTRY_DAT,
S2_CACHE_MASK_DAT,
S2_CACHE_ACTION_DAT,
S2_CACHE_CNT_DAT,
S2_CACHE_TG_DAT,
[...]
};
which is precisely what we want to avoid, because we'd have to duplicate
the same register map for S1 and for S0, and then figure out how to pass
VCAP instance-specific registers to the ocelot_read calls (basically
another lookup table that undoes the effect of shifting with
TARGET_OFFSET).
So for some targets, propose a more raw API, similar to what is
currently done with ocelot_port_readl and ocelot_port_writel. Those
targets can only be accessed with ocelot_target_{read,write} and not
with ocelot_{read,write} after the conversion, which is fine.
The VCAP registers are not actually modified to use this new API as of
this patch. They will be modified in the next one.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-30 06:27:21 +08:00
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u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
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u32 reg, u32 offset)
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{
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u32 val;
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regmap_read(ocelot->targets[target],
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ocelot->map[target][reg] + offset, &val);
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return val;
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}
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void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
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u32 val, u32 reg, u32 offset)
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{
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regmap_write(ocelot->targets[target],
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ocelot->map[target][reg] + offset, val);
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}
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2018-05-15 04:04:57 +08:00
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int ocelot_regfields_init(struct ocelot *ocelot,
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const struct reg_field *const regfields)
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{
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unsigned int i;
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u16 target;
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for (i = 0; i < REGFIELD_MAX; i++) {
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struct reg_field regfield = {};
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u32 reg = regfields[i].reg;
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if (!reg)
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continue;
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target = regfields[i].reg >> TARGET_OFFSET;
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regfield.reg = ocelot->map[target][reg & REG_MASK];
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regfield.lsb = regfields[i].lsb;
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regfield.msb = regfields[i].msb;
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net: mscc: ocelot: convert QSYS_SWITCH_PORT_MODE and SYS_PORT_MODE to regfields
Currently Felix and Ocelot share the same bit layout in these per-port
registers, but Seville does not. So we need reg_fields for that.
Actually since these are per-port registers, we need to also specify the
number of ports, and register size per port, and use the regmap API for
multiple ports.
There's a more subtle point to be made about the other 2 register
fields:
- QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG
- QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
which we are not writing any longer, for 2 reasons:
- Using the previous API (ocelot_write_rix), we were only writing 1 for
Felix and Ocelot, which was their hardware-default value, and which
there wasn't any intention in changing.
- In the case of SCH_NEXT_CFG, in fact Seville does not have this
register field at all, and therefore, if we want to have common code
we would be required to not write to it.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-14 00:57:03 +08:00
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regfield.id_size = regfields[i].id_size;
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regfield.id_offset = regfields[i].id_offset;
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2018-05-15 04:04:57 +08:00
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ocelot->regfields[i] =
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devm_regmap_field_alloc(ocelot->dev,
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ocelot->targets[target],
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regfield);
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if (IS_ERR(ocelot->regfields[i]))
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return PTR_ERR(ocelot->regfields[i]);
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}
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return 0;
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}
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EXPORT_SYMBOL(ocelot_regfields_init);
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static struct regmap_config ocelot_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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2019-11-14 23:03:20 +08:00
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struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res)
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2018-05-15 04:04:57 +08:00
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{
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void __iomem *regs;
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regs = devm_ioremap_resource(ocelot->dev, res);
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if (IS_ERR(regs))
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return ERR_CAST(regs);
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2019-11-14 23:03:20 +08:00
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ocelot_regmap_config.name = res->name;
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return devm_regmap_init_mmio(ocelot->dev, regs, &ocelot_regmap_config);
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2018-05-15 04:04:57 +08:00
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}
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2019-11-14 23:03:20 +08:00
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EXPORT_SYMBOL(ocelot_regmap_init);
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