2011-07-06 00:55:27 +08:00
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/*
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2012-04-06 05:54:53 +08:00
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* tegra20_spdif.c - Tegra20 SPDIF driver
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2011-07-06 00:55:27 +08:00
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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2012-03-21 04:55:49 +08:00
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* Copyright (C) 2011-2012 - NVIDIA, Inc.
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2011-07-06 00:55:27 +08:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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2012-04-07 01:12:25 +08:00
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#include <linux/io.h>
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#include <linux/module.h>
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2011-07-06 00:55:27 +08:00
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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2012-04-06 05:54:53 +08:00
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#include "tegra20_spdif.h"
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2011-07-06 00:55:27 +08:00
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2012-04-07 00:30:52 +08:00
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#define DRV_NAME "tegra20-spdif"
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2011-07-06 00:55:27 +08:00
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2012-04-07 00:30:52 +08:00
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static inline void tegra20_spdif_write(struct tegra20_spdif *spdif, u32 reg,
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2011-07-06 00:55:27 +08:00
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u32 val)
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{
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__raw_writel(val, spdif->regs + reg);
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}
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2012-04-07 00:30:52 +08:00
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static inline u32 tegra20_spdif_read(struct tegra20_spdif *spdif, u32 reg)
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2011-07-06 00:55:27 +08:00
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{
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return __raw_readl(spdif->regs + reg);
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}
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#ifdef CONFIG_DEBUG_FS
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2012-04-07 00:30:52 +08:00
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static int tegra20_spdif_show(struct seq_file *s, void *unused)
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2011-07-06 00:55:27 +08:00
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{
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#define REG(r) { r, #r }
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static const struct {
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int offset;
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const char *name;
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} regs[] = {
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2012-04-07 00:30:52 +08:00
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REG(TEGRA20_SPDIF_CTRL),
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REG(TEGRA20_SPDIF_STATUS),
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REG(TEGRA20_SPDIF_STROBE_CTRL),
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REG(TEGRA20_SPDIF_DATA_FIFO_CSR),
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REG(TEGRA20_SPDIF_CH_STA_RX_A),
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REG(TEGRA20_SPDIF_CH_STA_RX_B),
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REG(TEGRA20_SPDIF_CH_STA_RX_C),
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REG(TEGRA20_SPDIF_CH_STA_RX_D),
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REG(TEGRA20_SPDIF_CH_STA_RX_E),
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REG(TEGRA20_SPDIF_CH_STA_RX_F),
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REG(TEGRA20_SPDIF_CH_STA_TX_A),
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REG(TEGRA20_SPDIF_CH_STA_TX_B),
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REG(TEGRA20_SPDIF_CH_STA_TX_C),
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REG(TEGRA20_SPDIF_CH_STA_TX_D),
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REG(TEGRA20_SPDIF_CH_STA_TX_E),
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REG(TEGRA20_SPDIF_CH_STA_TX_F),
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2011-07-06 00:55:27 +08:00
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};
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#undef REG
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2012-04-07 00:30:52 +08:00
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struct tegra20_spdif *spdif = s->private;
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2011-07-06 00:55:27 +08:00
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int i;
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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2012-04-07 00:30:52 +08:00
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u32 val = tegra20_spdif_read(spdif, regs[i].offset);
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2011-07-06 00:55:27 +08:00
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seq_printf(s, "%s = %08x\n", regs[i].name, val);
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}
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return 0;
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}
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2012-04-07 00:30:52 +08:00
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static int tegra20_spdif_debug_open(struct inode *inode, struct file *file)
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2011-07-06 00:55:27 +08:00
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{
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2012-04-07 00:30:52 +08:00
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return single_open(file, tegra20_spdif_show, inode->i_private);
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2011-07-06 00:55:27 +08:00
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}
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2012-04-07 00:30:52 +08:00
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static const struct file_operations tegra20_spdif_debug_fops = {
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.open = tegra20_spdif_debug_open,
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2011-07-06 00:55:27 +08:00
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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2012-04-07 00:30:52 +08:00
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static void tegra20_spdif_debug_add(struct tegra20_spdif *spdif)
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2011-07-06 00:55:27 +08:00
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{
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spdif->debug = debugfs_create_file(DRV_NAME, S_IRUGO,
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snd_soc_debugfs_root, spdif,
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2012-04-07 00:30:52 +08:00
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&tegra20_spdif_debug_fops);
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2011-07-06 00:55:27 +08:00
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}
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2012-04-07 00:30:52 +08:00
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static void tegra20_spdif_debug_remove(struct tegra20_spdif *spdif)
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2011-07-06 00:55:27 +08:00
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{
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if (spdif->debug)
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debugfs_remove(spdif->debug);
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}
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#else
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2012-04-07 00:30:52 +08:00
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static inline void tegra20_spdif_debug_add(struct tegra20_spdif *spdif)
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2011-07-06 00:55:27 +08:00
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{
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}
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2012-04-07 00:30:52 +08:00
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static inline void tegra20_spdif_debug_remove(struct tegra20_spdif *spdif)
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2011-07-06 00:55:27 +08:00
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{
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}
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#endif
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2012-04-07 00:30:52 +08:00
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static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
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2011-07-06 00:55:27 +08:00
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = substream->pcm->card->dev;
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2012-04-07 00:30:52 +08:00
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struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
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2011-10-02 21:07:02 +08:00
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int ret, spdifclock;
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2011-07-06 00:55:27 +08:00
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2012-04-07 00:30:52 +08:00
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spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_PACK;
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spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
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2011-07-06 00:55:27 +08:00
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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2012-04-07 00:30:52 +08:00
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spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_PACK;
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spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
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2011-07-06 00:55:27 +08:00
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break;
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default:
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return -EINVAL;
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}
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switch (params_rate(params)) {
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case 32000:
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spdifclock = 4096000;
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break;
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case 44100:
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spdifclock = 5644800;
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break;
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case 48000:
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spdifclock = 6144000;
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break;
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case 88200:
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spdifclock = 11289600;
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break;
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case 96000:
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spdifclock = 12288000;
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break;
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case 176400:
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spdifclock = 22579200;
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break;
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case 192000:
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spdifclock = 24576000;
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break;
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default:
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return -EINVAL;
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}
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ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
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if (ret) {
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dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
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return ret;
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}
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return 0;
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}
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2012-04-07 00:30:52 +08:00
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static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
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2011-07-06 00:55:27 +08:00
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{
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2012-04-07 00:30:52 +08:00
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spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_TX_EN;
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tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
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2011-07-06 00:55:27 +08:00
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}
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2012-04-07 00:30:52 +08:00
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static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
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2011-07-06 00:55:27 +08:00
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{
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2012-04-07 00:30:52 +08:00
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spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_TX_EN;
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tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
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2011-07-06 00:55:27 +08:00
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}
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2012-04-07 00:30:52 +08:00
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static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
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2011-07-06 00:55:27 +08:00
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struct snd_soc_dai *dai)
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{
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2012-04-07 00:30:52 +08:00
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struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
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2011-07-06 00:55:27 +08:00
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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2012-03-31 07:07:16 +08:00
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clk_enable(spdif->clk_spdif_out);
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2012-04-07 00:30:52 +08:00
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tegra20_spdif_start_playback(spdif);
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2011-07-06 00:55:27 +08:00
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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2012-04-07 00:30:52 +08:00
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tegra20_spdif_stop_playback(spdif);
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2012-03-31 07:07:16 +08:00
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clk_disable(spdif->clk_spdif_out);
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2011-07-06 00:55:27 +08:00
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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2012-04-07 00:30:52 +08:00
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static int tegra20_spdif_probe(struct snd_soc_dai *dai)
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2011-07-06 00:55:27 +08:00
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{
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2012-04-07 00:30:52 +08:00
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struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
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2011-07-06 00:55:27 +08:00
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dai->capture_dma_data = NULL;
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dai->playback_dma_data = &spdif->playback_dma_data;
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return 0;
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}
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2012-04-07 00:30:52 +08:00
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static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
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.hw_params = tegra20_spdif_hw_params,
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.trigger = tegra20_spdif_trigger,
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2011-07-06 00:55:27 +08:00
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};
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2012-04-07 00:30:52 +08:00
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static struct snd_soc_dai_driver tegra20_spdif_dai = {
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2011-07-06 00:55:27 +08:00
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.name = DRV_NAME,
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2012-04-07 00:30:52 +08:00
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.probe = tegra20_spdif_probe,
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2011-07-06 00:55:27 +08:00
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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2012-04-07 00:30:52 +08:00
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.ops = &tegra20_spdif_dai_ops,
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2011-07-06 00:55:27 +08:00
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};
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2012-04-07 00:30:52 +08:00
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static __devinit int tegra20_spdif_platform_probe(struct platform_device *pdev)
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2011-07-06 00:55:27 +08:00
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{
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2012-04-07 00:30:52 +08:00
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struct tegra20_spdif *spdif;
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2011-07-06 00:55:27 +08:00
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struct resource *mem, *memregion, *dmareq;
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int ret;
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2012-04-07 00:30:52 +08:00
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spdif = kzalloc(sizeof(struct tegra20_spdif), GFP_KERNEL);
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2011-07-06 00:55:27 +08:00
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if (!spdif) {
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2012-04-07 00:30:52 +08:00
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dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n");
|
2011-07-06 00:55:27 +08:00
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ret = -ENOMEM;
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goto exit;
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}
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dev_set_drvdata(&pdev->dev, spdif);
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spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
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if (IS_ERR(spdif->clk_spdif_out)) {
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pr_err("Can't retrieve spdif clock\n");
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ret = PTR_ERR(spdif->clk_spdif_out);
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goto err_free;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "No memory resource\n");
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ret = -ENODEV;
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goto err_clk_put;
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}
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dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!dmareq) {
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dev_err(&pdev->dev, "No DMA resource\n");
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ret = -ENODEV;
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goto err_clk_put;
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}
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memregion = request_mem_region(mem->start, resource_size(mem),
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DRV_NAME);
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if (!memregion) {
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dev_err(&pdev->dev, "Memory region already claimed\n");
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ret = -EBUSY;
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goto err_clk_put;
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}
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spdif->regs = ioremap(mem->start, resource_size(mem));
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if (!spdif->regs) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto err_release;
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}
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|
2012-04-07 00:30:52 +08:00
|
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spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
|
2011-07-06 00:55:27 +08:00
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|
spdif->playback_dma_data.wrap = 4;
|
|
|
|
spdif->playback_dma_data.width = 32;
|
|
|
|
spdif->playback_dma_data.req_sel = dmareq->start;
|
|
|
|
|
2012-04-07 00:30:52 +08:00
|
|
|
ret = snd_soc_register_dai(&pdev->dev, &tegra20_spdif_dai);
|
2011-07-06 00:55:27 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_unmap;
|
|
|
|
}
|
|
|
|
|
2012-03-21 04:55:49 +08:00
|
|
|
ret = tegra_pcm_platform_register(&pdev->dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
|
|
|
|
goto err_unregister_dai;
|
|
|
|
}
|
|
|
|
|
2012-04-07 00:30:52 +08:00
|
|
|
tegra20_spdif_debug_add(spdif);
|
2011-07-06 00:55:27 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2012-03-21 04:55:49 +08:00
|
|
|
err_unregister_dai:
|
|
|
|
snd_soc_unregister_dai(&pdev->dev);
|
2011-07-06 00:55:27 +08:00
|
|
|
err_unmap:
|
|
|
|
iounmap(spdif->regs);
|
|
|
|
err_release:
|
|
|
|
release_mem_region(mem->start, resource_size(mem));
|
|
|
|
err_clk_put:
|
|
|
|
clk_put(spdif->clk_spdif_out);
|
|
|
|
err_free:
|
|
|
|
kfree(spdif);
|
|
|
|
exit:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-04-07 00:30:52 +08:00
|
|
|
static int __devexit tegra20_spdif_platform_remove(struct platform_device *pdev)
|
2011-07-06 00:55:27 +08:00
|
|
|
{
|
2012-04-07 00:30:52 +08:00
|
|
|
struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev);
|
2011-07-06 00:55:27 +08:00
|
|
|
struct resource *res;
|
|
|
|
|
2012-03-21 04:55:49 +08:00
|
|
|
tegra_pcm_platform_unregister(&pdev->dev);
|
2011-07-06 00:55:27 +08:00
|
|
|
snd_soc_unregister_dai(&pdev->dev);
|
|
|
|
|
2012-04-07 00:30:52 +08:00
|
|
|
tegra20_spdif_debug_remove(spdif);
|
2011-07-06 00:55:27 +08:00
|
|
|
|
|
|
|
iounmap(spdif->regs);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
release_mem_region(res->start, resource_size(res));
|
|
|
|
|
|
|
|
clk_put(spdif->clk_spdif_out);
|
|
|
|
|
|
|
|
kfree(spdif);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-04-07 00:30:52 +08:00
|
|
|
static struct platform_driver tegra20_spdif_driver = {
|
2011-07-06 00:55:27 +08:00
|
|
|
.driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
2012-04-07 00:30:52 +08:00
|
|
|
.probe = tegra20_spdif_platform_probe,
|
|
|
|
.remove = __devexit_p(tegra20_spdif_platform_remove),
|
2011-07-06 00:55:27 +08:00
|
|
|
};
|
|
|
|
|
2012-04-07 00:30:52 +08:00
|
|
|
module_platform_driver(tegra20_spdif_driver);
|
2011-07-06 00:55:27 +08:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
2012-04-07 00:30:52 +08:00
|
|
|
MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
|
2011-07-06 00:55:27 +08:00
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|