OpenCloudOS-Kernel/drivers/gpu/drm/sun4i/sun4i_rgb.c

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Free Electrons
* Copyright (C) 2015 NextThing Co
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*/
#include <linux/clk.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_print.h>
drm: Split out drm_probe_helper.h Having the probe helper stuff (which pretty much everyone needs) in the drm_crtc_helper.h file (which atomic drivers should never need) is confusing. Split them out. To make sure I actually achieved the goal here I went through all drivers. And indeed, all atomic drivers are now free of drm_crtc_helper.h includes. v2: Make it compile. There was so much compile fail on arm drivers that I figured I'll better not include any of the acks on v1. v3: Massive rebase because i915 has lost a lot of drmP.h includes, but not all: Through drm_crtc_helper.h > drm_modeset_helper.h -> drmP.h there was still one, which this patch largely removes. Which means rolling out lots more includes all over. This will also conflict with ongoing drmP.h cleanup by others I expect. v3: Rebase on top of atomic bochs. v4: Review from Laurent for bridge/rcar/omap/shmob/core bits: - (re)move some of the added includes, use the better include files in other places (all suggested from Laurent adopted unchanged). - sort alphabetically v5: Actually try to sort them, and while at it, sort all the ones I touch. v6: Rebase onto i915 changes. v7: Rebase once more. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Acked-by: CK Hu <ck.hu@mediatek.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: virtualization@lists.linux-foundation.org Cc: etnaviv@lists.freedesktop.org Cc: linux-samsung-soc@vger.kernel.org Cc: intel-gfx@lists.freedesktop.org Cc: linux-mediatek@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: spice-devel@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-tegra@vger.kernel.org Cc: xen-devel@lists.xen.org Link: https://patchwork.freedesktop.org/patch/msgid/20190117210334.13234-1-daniel.vetter@ffwll.ch
2019-01-18 05:03:34 +08:00
#include <drm/drm_probe_helper.h>
#include "sun4i_crtc.h"
#include "sun4i_tcon.h"
#include "sun4i_rgb.h"
struct sun4i_rgb {
struct drm_connector connector;
struct drm_encoder encoder;
struct sun4i_tcon *tcon;
struct drm_panel *panel;
struct drm_bridge *bridge;
};
static inline struct sun4i_rgb *
drm_connector_to_sun4i_rgb(struct drm_connector *connector)
{
return container_of(connector, struct sun4i_rgb,
connector);
}
static inline struct sun4i_rgb *
drm_encoder_to_sun4i_rgb(struct drm_encoder *encoder)
{
return container_of(encoder, struct sun4i_rgb,
encoder);
}
static int sun4i_rgb_get_modes(struct drm_connector *connector)
{
struct sun4i_rgb *rgb =
drm_connector_to_sun4i_rgb(connector);
return drm_panel_get_modes(rgb->panel);
}
drm/sun4i: rgb: Change the pixel clock validation check The current code, since commit bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate"), perform some validation on the pixel clock to filter out the EDID modes provided by monitors (through bridges) that we wouldn't be able to reach. For the usual modes, we're able to generate a perfect clock rate, so a strict check was enough. However, this had the side effect of preventing displays that would work otherwise to operate properly, since we would pretty much never be able to generate an exact rate for those displays, even though we would fall within that panel tolerance. This was also shown to happen for unusual modes exposed through EDIDs, for example on eDP panels. We can work around this by simplifying a bit the problem: no panels we've encountered so far actually needed that check. All of them are tied to a particular board when it is produced, and made to work with the Allwinner BSP. That pretty much guarantees that we never have a pixel clock out of reach. On the other hand, the EDIDs modes that needed to be validated have always been exposed through bridges. Let's just use that metric to instead of validating all modes, only validate modes when we have a bridge attached. It should be good enough for now, while we still have room for improvements or refinements using the display_timings structure for example for panels. We also add a tolerance for EDID-based modes instead of doing a strict check. This tolerance is of 0.5% which is the one advertised in the VESA DVT and CVT specs. If that needed to be extended in the future, we can add a custom module parameter to relax it a bit. Fixes: bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # tested on pinebook Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec2dc2a7b3d4bd44f7a2a6e1c1813f92449a7310.1551191081.git-series.maxime.ripard@bootlin.com
2019-02-26 22:25:49 +08:00
/*
* VESA DMT defines a tolerance of 0.5% on the pixel clock, while the
* CVT spec reuses that tolerance in its examples, so it looks to be a
* good default tolerance for the EDID-based modes. Define it to 5 per
* mille to avoid floating point operations.
*/
#define SUN4I_RGB_DOTCLOCK_TOLERANCE_PER_MILLE 5
static enum drm_mode_status sun4i_rgb_mode_valid(struct drm_encoder *crtc,
const struct drm_display_mode *mode)
{
struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(crtc);
struct sun4i_tcon *tcon = rgb->tcon;
u32 hsync = mode->hsync_end - mode->hsync_start;
u32 vsync = mode->vsync_end - mode->vsync_start;
unsigned long long rate = mode->clock * 1000;
drm/sun4i: rgb: Change the pixel clock validation check The current code, since commit bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate"), perform some validation on the pixel clock to filter out the EDID modes provided by monitors (through bridges) that we wouldn't be able to reach. For the usual modes, we're able to generate a perfect clock rate, so a strict check was enough. However, this had the side effect of preventing displays that would work otherwise to operate properly, since we would pretty much never be able to generate an exact rate for those displays, even though we would fall within that panel tolerance. This was also shown to happen for unusual modes exposed through EDIDs, for example on eDP panels. We can work around this by simplifying a bit the problem: no panels we've encountered so far actually needed that check. All of them are tied to a particular board when it is produced, and made to work with the Allwinner BSP. That pretty much guarantees that we never have a pixel clock out of reach. On the other hand, the EDIDs modes that needed to be validated have always been exposed through bridges. Let's just use that metric to instead of validating all modes, only validate modes when we have a bridge attached. It should be good enough for now, while we still have room for improvements or refinements using the display_timings structure for example for panels. We also add a tolerance for EDID-based modes instead of doing a strict check. This tolerance is of 0.5% which is the one advertised in the VESA DVT and CVT specs. If that needed to be extended in the future, we can add a custom module parameter to relax it a bit. Fixes: bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # tested on pinebook Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec2dc2a7b3d4bd44f7a2a6e1c1813f92449a7310.1551191081.git-series.maxime.ripard@bootlin.com
2019-02-26 22:25:49 +08:00
unsigned long long lowest, highest;
unsigned long long rounded_rate;
DRM_DEBUG_DRIVER("Validating modes...\n");
if (hsync < 1)
return MODE_HSYNC_NARROW;
if (hsync > 0x3ff)
return MODE_HSYNC_WIDE;
if ((mode->hdisplay < 1) || (mode->htotal < 1))
return MODE_H_ILLEGAL;
if ((mode->hdisplay > 0x7ff) || (mode->htotal > 0xfff))
return MODE_BAD_HVALUE;
DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
if (vsync < 1)
return MODE_VSYNC_NARROW;
if (vsync > 0x3ff)
return MODE_VSYNC_WIDE;
if ((mode->vdisplay < 1) || (mode->vtotal < 1))
return MODE_V_ILLEGAL;
if ((mode->vdisplay > 0x7ff) || (mode->vtotal > 0xfff))
return MODE_BAD_VVALUE;
DRM_DEBUG_DRIVER("Vertical parameters OK\n");
drm/sun4i: rgb: Change the pixel clock validation check The current code, since commit bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate"), perform some validation on the pixel clock to filter out the EDID modes provided by monitors (through bridges) that we wouldn't be able to reach. For the usual modes, we're able to generate a perfect clock rate, so a strict check was enough. However, this had the side effect of preventing displays that would work otherwise to operate properly, since we would pretty much never be able to generate an exact rate for those displays, even though we would fall within that panel tolerance. This was also shown to happen for unusual modes exposed through EDIDs, for example on eDP panels. We can work around this by simplifying a bit the problem: no panels we've encountered so far actually needed that check. All of them are tied to a particular board when it is produced, and made to work with the Allwinner BSP. That pretty much guarantees that we never have a pixel clock out of reach. On the other hand, the EDIDs modes that needed to be validated have always been exposed through bridges. Let's just use that metric to instead of validating all modes, only validate modes when we have a bridge attached. It should be good enough for now, while we still have room for improvements or refinements using the display_timings structure for example for panels. We also add a tolerance for EDID-based modes instead of doing a strict check. This tolerance is of 0.5% which is the one advertised in the VESA DVT and CVT specs. If that needed to be extended in the future, we can add a custom module parameter to relax it a bit. Fixes: bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # tested on pinebook Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec2dc2a7b3d4bd44f7a2a6e1c1813f92449a7310.1551191081.git-series.maxime.ripard@bootlin.com
2019-02-26 22:25:49 +08:00
/*
* TODO: We should use the struct display_timing if available
* and / or trying to stretch the timings within that
* tolerancy to take care of panels that we wouldn't be able
* to have a exact match for.
*/
if (rgb->panel) {
DRM_DEBUG_DRIVER("RGB panel used, skipping clock rate checks");
goto out;
}
/*
* That shouldn't ever happen unless something is really wrong, but it
* doesn't harm to check.
*/
if (!rgb->bridge)
goto out;
tcon->dclk_min_div = 6;
tcon->dclk_max_div = 127;
rounded_rate = clk_round_rate(tcon->dclk, rate);
drm/sun4i: rgb: Change the pixel clock validation check The current code, since commit bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate"), perform some validation on the pixel clock to filter out the EDID modes provided by monitors (through bridges) that we wouldn't be able to reach. For the usual modes, we're able to generate a perfect clock rate, so a strict check was enough. However, this had the side effect of preventing displays that would work otherwise to operate properly, since we would pretty much never be able to generate an exact rate for those displays, even though we would fall within that panel tolerance. This was also shown to happen for unusual modes exposed through EDIDs, for example on eDP panels. We can work around this by simplifying a bit the problem: no panels we've encountered so far actually needed that check. All of them are tied to a particular board when it is produced, and made to work with the Allwinner BSP. That pretty much guarantees that we never have a pixel clock out of reach. On the other hand, the EDIDs modes that needed to be validated have always been exposed through bridges. Let's just use that metric to instead of validating all modes, only validate modes when we have a bridge attached. It should be good enough for now, while we still have room for improvements or refinements using the display_timings structure for example for panels. We also add a tolerance for EDID-based modes instead of doing a strict check. This tolerance is of 0.5% which is the one advertised in the VESA DVT and CVT specs. If that needed to be extended in the future, we can add a custom module parameter to relax it a bit. Fixes: bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # tested on pinebook Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec2dc2a7b3d4bd44f7a2a6e1c1813f92449a7310.1551191081.git-series.maxime.ripard@bootlin.com
2019-02-26 22:25:49 +08:00
lowest = rate * (1000 - SUN4I_RGB_DOTCLOCK_TOLERANCE_PER_MILLE);
do_div(lowest, 1000);
if (rounded_rate < lowest)
return MODE_CLOCK_LOW;
drm/sun4i: rgb: Change the pixel clock validation check The current code, since commit bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate"), perform some validation on the pixel clock to filter out the EDID modes provided by monitors (through bridges) that we wouldn't be able to reach. For the usual modes, we're able to generate a perfect clock rate, so a strict check was enough. However, this had the side effect of preventing displays that would work otherwise to operate properly, since we would pretty much never be able to generate an exact rate for those displays, even though we would fall within that panel tolerance. This was also shown to happen for unusual modes exposed through EDIDs, for example on eDP panels. We can work around this by simplifying a bit the problem: no panels we've encountered so far actually needed that check. All of them are tied to a particular board when it is produced, and made to work with the Allwinner BSP. That pretty much guarantees that we never have a pixel clock out of reach. On the other hand, the EDIDs modes that needed to be validated have always been exposed through bridges. Let's just use that metric to instead of validating all modes, only validate modes when we have a bridge attached. It should be good enough for now, while we still have room for improvements or refinements using the display_timings structure for example for panels. We also add a tolerance for EDID-based modes instead of doing a strict check. This tolerance is of 0.5% which is the one advertised in the VESA DVT and CVT specs. If that needed to be extended in the future, we can add a custom module parameter to relax it a bit. Fixes: bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # tested on pinebook Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec2dc2a7b3d4bd44f7a2a6e1c1813f92449a7310.1551191081.git-series.maxime.ripard@bootlin.com
2019-02-26 22:25:49 +08:00
highest = rate * (1000 + SUN4I_RGB_DOTCLOCK_TOLERANCE_PER_MILLE);
do_div(highest, 1000);
if (rounded_rate > highest)
return MODE_CLOCK_HIGH;
drm/sun4i: rgb: Change the pixel clock validation check The current code, since commit bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate"), perform some validation on the pixel clock to filter out the EDID modes provided by monitors (through bridges) that we wouldn't be able to reach. For the usual modes, we're able to generate a perfect clock rate, so a strict check was enough. However, this had the side effect of preventing displays that would work otherwise to operate properly, since we would pretty much never be able to generate an exact rate for those displays, even though we would fall within that panel tolerance. This was also shown to happen for unusual modes exposed through EDIDs, for example on eDP panels. We can work around this by simplifying a bit the problem: no panels we've encountered so far actually needed that check. All of them are tied to a particular board when it is produced, and made to work with the Allwinner BSP. That pretty much guarantees that we never have a pixel clock out of reach. On the other hand, the EDIDs modes that needed to be validated have always been exposed through bridges. Let's just use that metric to instead of validating all modes, only validate modes when we have a bridge attached. It should be good enough for now, while we still have room for improvements or refinements using the display_timings structure for example for panels. We also add a tolerance for EDID-based modes instead of doing a strict check. This tolerance is of 0.5% which is the one advertised in the VESA DVT and CVT specs. If that needed to be extended in the future, we can add a custom module parameter to relax it a bit. Fixes: bb43d40d7c83 ("drm/sun4i: rgb: Validate the clock rate") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # tested on pinebook Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec2dc2a7b3d4bd44f7a2a6e1c1813f92449a7310.1551191081.git-series.maxime.ripard@bootlin.com
2019-02-26 22:25:49 +08:00
out:
DRM_DEBUG_DRIVER("Clock rate OK\n");
return MODE_OK;
}
static struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
.get_modes = sun4i_rgb_get_modes,
};
static void
sun4i_rgb_connector_destroy(struct drm_connector *connector)
{
struct sun4i_rgb *rgb = drm_connector_to_sun4i_rgb(connector);
drm_panel_detach(rgb->panel);
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs sun4i_rgb_con_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = sun4i_rgb_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
{
struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
DRM_DEBUG_DRIVER("Enabling RGB output\n");
if (rgb->panel) {
drm_panel_prepare(rgb->panel);
drm_panel_enable(rgb->panel);
}
}
static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
{
struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
DRM_DEBUG_DRIVER("Disabling RGB output\n");
if (rgb->panel) {
drm_panel_disable(rgb->panel);
drm_panel_unprepare(rgb->panel);
}
}
static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
.disable = sun4i_rgb_encoder_disable,
.enable = sun4i_rgb_encoder_enable,
.mode_valid = sun4i_rgb_mode_valid,
};
static void sun4i_rgb_enc_destroy(struct drm_encoder *encoder)
{
drm_encoder_cleanup(encoder);
}
static struct drm_encoder_funcs sun4i_rgb_enc_funcs = {
.destroy = sun4i_rgb_enc_destroy,
};
int sun4i_rgb_init(struct drm_device *drm, struct sun4i_tcon *tcon)
{
struct drm_encoder *encoder;
struct sun4i_rgb *rgb;
int ret;
rgb = devm_kzalloc(drm->dev, sizeof(*rgb), GFP_KERNEL);
if (!rgb)
return -ENOMEM;
rgb->tcon = tcon;
encoder = &rgb->encoder;
ret = drm_of_find_panel_or_bridge(tcon->dev->of_node, 1, 0,
&rgb->panel, &rgb->bridge);
if (ret) {
dev_info(drm->dev, "No panel or bridge found... RGB output disabled\n");
return 0;
}
drm_encoder_helper_add(&rgb->encoder,
&sun4i_rgb_enc_helper_funcs);
ret = drm_encoder_init(drm,
&rgb->encoder,
&sun4i_rgb_enc_funcs,
DRM_MODE_ENCODER_NONE,
NULL);
if (ret) {
dev_err(drm->dev, "Couldn't initialise the rgb encoder\n");
goto err_out;
}
/* The RGB encoder can only work with the TCON channel 0 */
rgb->encoder.possible_crtcs = drm_crtc_mask(&tcon->crtc->crtc);
if (rgb->panel) {
drm_connector_helper_add(&rgb->connector,
&sun4i_rgb_con_helper_funcs);
ret = drm_connector_init(drm, &rgb->connector,
&sun4i_rgb_con_funcs,
DRM_MODE_CONNECTOR_Unknown);
if (ret) {
dev_err(drm->dev, "Couldn't initialise the rgb connector\n");
goto err_cleanup_connector;
}
drm_connector_attach_encoder(&rgb->connector,
&rgb->encoder);
ret = drm_panel_attach(rgb->panel, &rgb->connector);
if (ret) {
dev_err(drm->dev, "Couldn't attach our panel\n");
goto err_cleanup_connector;
}
}
if (rgb->bridge) {
ret = drm_bridge_attach(encoder, rgb->bridge, NULL);
if (ret) {
dev_err(drm->dev, "Couldn't attach our bridge\n");
goto err_cleanup_connector;
}
}
return 0;
err_cleanup_connector:
drm_encoder_cleanup(&rgb->encoder);
err_out:
return ret;
}
EXPORT_SYMBOL(sun4i_rgb_init);