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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2021 Arm Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
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maintainers:
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- Suzuki K Poulose <suzuki.poulose@arm.com>
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- Robin Murphy <robin.murphy@arm.com>
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description:
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ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
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L3 memory system, control logic and external interfaces to form a multicore
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cluster. The PMU enables gathering various statistics on the operation of the
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DSU. The PMU provides independent 32-bit counters that can count any of the
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supported events, along with a 64-bit cycle counter. The PMU is accessed via
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CPU system registers and has no MMIO component.
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properties:
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compatible:
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oneOf:
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- const: arm,dsu-pmu
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- items:
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- const: arm,dsu-110-pmu
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- const: arm,dsu-pmu
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interrupts:
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items:
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- description: nCLUSTERPMUIRQ interrupt
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cpus:
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minItems: 1
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maxItems: 12
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description: List of phandles for the CPUs connected to this DSU instance.
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required:
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- compatible
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- interrupts
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- cpus
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additionalProperties: false
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