2022-05-31 18:04:11 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Author: Huacai Chen <chenhuacai@loongson.cn>
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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2023-05-01 17:19:10 +08:00
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#include <linux/bitfield.h>
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2022-05-31 18:04:11 +08:00
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/context_tracking.h>
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#include <linux/entry-common.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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LoongArch: Add kdump support
This patch adds support for kdump. In kdump case the normal kernel will
reserve a region for the crash kernel and jump there on panic.
Arch-specific functions are added to allow for implementing a crash dump
file interface, /proc/vmcore, which can be viewed as a ELF file.
A user-space tool, such as kexec-tools, is responsible for allocating a
separate region for the core's ELF header within the crash kdump kernel
memory and filling it in when executing kexec_load().
Then, its location will be advertised to the crash dump kernel via a
command line argument "elfcorehdr=", and the crash dump kernel will
preserve this region for later use with arch_reserve_vmcore() at boot
time.
At the same time, the crash kdump kernel is also limited within the
"crashkernel" area via a command line argument "mem=", so as not to
destroy the original kernel dump data.
In the crash dump kernel environment, /proc/vmcore is used to access the
primary kernel's memory with copy_oldmem_page().
I tested kdump on LoongArch machines (Loongson-3A5000) and it works as
expected (suggested crashkernel parameter is "crashkernel=512M@2560M"),
you may test it by triggering a crash through /proc/sysrq-trigger:
$ sudo kexec -p /boot/vmlinux-kdump --reuse-cmdline --append="nr_cpus=1"
# echo c > /proc/sysrq-trigger
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:19 +08:00
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#include <linux/kexec.h>
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2022-05-31 18:04:11 +08:00
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#include <linux/module.h>
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#include <linux/extable.h>
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#include <linux/mm.h>
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#include <linux/sched/mm.h>
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#include <linux/sched/debug.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/memblock.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/kgdb.h>
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#include <linux/kdebug.h>
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#include <linux/notifier.h>
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#include <linux/irq.h>
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#include <linux/perf_event.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/branch.h>
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#include <asm/break.h>
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#include <asm/cpu.h>
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2023-09-20 14:26:28 +08:00
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#include <asm/exception.h>
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2022-05-31 18:04:11 +08:00
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#include <asm/fpu.h>
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2023-09-06 22:53:55 +08:00
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#include <asm/lbt.h>
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LoongArch: Relay BCE exceptions to userland as SIGSEGV with si_code=SEGV_BNDERR
SEGV_BNDERR was introduced initially for supporting the Intel MPX, but
fell into disuse after the MPX support was removed. The LoongArch
bounds-checking instructions behave very differently than MPX, but
overall the interface is still kind of suitable for conveying the
information to userland when bounds-checking assertions trigger, so we
wouldn't have to invent more UAPI. Specifically, when the BCE triggers,
a SEGV_BNDERR is sent to userland, with si_addr set to the out-of-bounds
address or value (in asrt{gt,le}'s case), and one of si_lower or
si_upper set to the configured bound depending on the faulting
instruction. The other bound is set to either 0 or ULONG_MAX to resemble
a range with both lower and upper bounds.
Note that it is possible to have si_addr == si_lower in case of a
failing asrtgt or {ld,st}gt, because those instructions test for strict
greater-than relationship. This should not pose a problem for userland,
though, because the faulting PC is available for the application to
associate back to the exact instruction for figuring out the
expectation.
Example exception context generated by a faulting `asrtgt.d t0, t1`
(assert t0 > t1 or BCE) with t0=100 and t1=200:
> pc 00005555558206a4 ra 00007ffff2d854fc tp 00007ffff2f2f180 sp 00007ffffbf9fb80
> a0 0000000000000002 a1 00007ffffbf9fce8 a2 00007ffffbf9fd00 a3 00007ffff2ed4558
> a4 0000000000000000 a5 00007ffff2f044c8 a6 00007ffffbf9fce0 a7 fffffffffffff000
> t0 0000000000000064 t1 00000000000000c8 t2 00007ffffbfa2d5e t3 00007ffff2f12aa0
> t4 00007ffff2ed6158 t5 00007ffff2ed6158 t6 000000000000002e t7 0000000003d8f538
> t8 0000000000000005 u0 0000000000000000 s9 0000000000000000 s0 00007ffffbf9fce8
> s1 0000000000000002 s2 0000000000000000 s3 00007ffff2f2c038 s4 0000555555820610
> s5 00007ffff2ed5000 s6 0000555555827e38 s7 00007ffffbf9fd00 s8 0000555555827e38
> ra: 00007ffff2d854fc
> ERA: 00005555558206a4
> CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE)
> PRMD: 00000007 (PPLV3 +PIE -PWE)
> EUEN: 00000000 (-FPE -SXE -ASXE -BTE)
> ECFG: 0007181c (LIE=2-4,11-12 VS=7)
> ESTAT: 000a0000 [BCE] (IS= ECode=10 EsubCode=0)
> PRID: 0014c010 (Loongson-64bit, Loongson-3A5000)
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2023-05-01 17:19:27 +08:00
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#include <asm/inst.h>
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2023-09-06 22:53:55 +08:00
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#include <asm/kgdb.h>
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2022-05-31 18:04:11 +08:00
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#include <asm/loongarch.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include <asm/sections.h>
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#include <asm/siginfo.h>
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#include <asm/stacktrace.h>
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#include <asm/tlb.h>
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#include <asm/types.h>
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2022-08-06 16:10:02 +08:00
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#include <asm/unwind.h>
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2023-06-29 20:58:44 +08:00
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#include <asm/uprobes.h>
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2022-05-31 18:04:11 +08:00
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#include "access-helper.h"
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2024-03-11 22:23:47 +08:00
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void *exception_table[EXCCODE_INT_START] = {
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[0 ... EXCCODE_INT_START - 1] = handle_reserved,
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[EXCCODE_TLBI] = handle_tlb_load,
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[EXCCODE_TLBL] = handle_tlb_load,
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[EXCCODE_TLBS] = handle_tlb_store,
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[EXCCODE_TLBM] = handle_tlb_modify,
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[EXCCODE_TLBNR] = handle_tlb_protect,
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[EXCCODE_TLBNX] = handle_tlb_protect,
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[EXCCODE_TLBPE] = handle_tlb_protect,
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[EXCCODE_ADE] = handle_ade,
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[EXCCODE_ALE] = handle_ale,
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[EXCCODE_BCE] = handle_bce,
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[EXCCODE_SYS] = handle_sys,
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[EXCCODE_BP] = handle_bp,
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[EXCCODE_INE] = handle_ri,
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[EXCCODE_IPE] = handle_ri,
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[EXCCODE_FPDIS] = handle_fpu,
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[EXCCODE_LSXDIS] = handle_lsx,
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[EXCCODE_LASXDIS] = handle_lasx,
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[EXCCODE_FPE] = handle_fpe,
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[EXCCODE_WATCH] = handle_watch,
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[EXCCODE_BTDIS] = handle_lbt,
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};
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EXPORT_SYMBOL_GPL(exception_table);
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2022-05-31 18:04:11 +08:00
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static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
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const char *loglvl, bool user)
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{
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unsigned long addr;
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2022-08-06 16:10:02 +08:00
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struct unwind_state state;
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struct pt_regs *pregs = (struct pt_regs *)regs;
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if (!task)
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task = current;
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2022-05-31 18:04:11 +08:00
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printk("%sCall Trace:", loglvl);
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2022-08-06 16:10:02 +08:00
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for (unwind_start(&state, task, pregs);
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!unwind_done(&state); unwind_next_frame(&state)) {
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addr = unwind_get_return_address(&state);
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print_ip_sym(loglvl, addr);
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2022-05-31 18:04:11 +08:00
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}
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printk("%s\n", loglvl);
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}
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static void show_stacktrace(struct task_struct *task,
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const struct pt_regs *regs, const char *loglvl, bool user)
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{
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int i;
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const int field = 2 * sizeof(unsigned long);
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unsigned long stackdata;
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unsigned long *sp = (unsigned long *)regs->regs[3];
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printk("%sStack :", loglvl);
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i = 0;
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while ((unsigned long) sp & (PAGE_SIZE - 1)) {
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if (i && ((i % (64 / field)) == 0)) {
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pr_cont("\n");
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printk("%s ", loglvl);
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}
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if (i > 39) {
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pr_cont(" ...");
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break;
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}
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if (__get_addr(&stackdata, sp++, user)) {
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pr_cont(" (Bad stack address)");
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break;
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}
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pr_cont(" %0*lx", field, stackdata);
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i++;
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}
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pr_cont("\n");
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show_backtrace(task, regs, loglvl, user);
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}
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void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
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{
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struct pt_regs regs;
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regs.csr_crmd = 0;
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if (sp) {
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regs.csr_era = 0;
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regs.regs[1] = 0;
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regs.regs[3] = (unsigned long)sp;
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} else {
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if (!task || task == current)
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prepare_frametrace(®s);
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else {
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regs.csr_era = task->thread.reg01;
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regs.regs[1] = 0;
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regs.regs[3] = task->thread.reg03;
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regs.regs[22] = task->thread.reg22;
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}
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}
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show_stacktrace(task, ®s, loglvl, false);
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}
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static void show_code(unsigned int *pc, bool user)
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{
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long i;
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unsigned int insn;
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printk("Code:");
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for(i = -3 ; i < 6 ; i++) {
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if (__get_inst(&insn, pc + i, user)) {
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pr_cont(" (Bad address in era)\n");
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break;
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}
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pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
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}
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pr_cont("\n");
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}
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2023-05-01 17:19:10 +08:00
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static void print_bool_fragment(const char *key, unsigned long val, bool first)
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{
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/* e.g. "+PG", "-DA" */
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pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key);
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}
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static void print_plv_fragment(const char *key, int val)
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{
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/* e.g. "PLV0", "PPLV3" */
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pr_cont("%s%d", key, val);
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}
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static void print_memory_type_fragment(const char *key, unsigned long val)
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{
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const char *humanized_type;
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switch (val) {
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case 0:
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humanized_type = "SUC";
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break;
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case 1:
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humanized_type = "CC";
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break;
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case 2:
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humanized_type = "WUC";
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break;
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default:
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pr_cont(" %s=Reserved(%lu)", key, val);
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return;
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}
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/* e.g. " DATM=WUC" */
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pr_cont(" %s=%s", key, humanized_type);
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}
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2023-05-01 17:19:27 +08:00
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static void print_intr_fragment(const char *key, unsigned long val)
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{
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/* e.g. "LIE=0-1,3,5-7" */
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pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val);
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}
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2023-05-01 17:19:10 +08:00
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static void print_crmd(unsigned long x)
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{
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printk(" CRMD: %08lx (", x);
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print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x));
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print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false);
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print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false);
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print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false);
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print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x));
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print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x));
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print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false);
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pr_cont(")\n");
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}
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2023-05-01 17:19:10 +08:00
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static void print_prmd(unsigned long x)
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{
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printk(" PRMD: %08lx (", x);
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print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x));
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print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false);
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print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false);
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pr_cont(")\n");
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}
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2023-05-01 17:19:27 +08:00
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static void print_euen(unsigned long x)
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{
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printk(" EUEN: %08lx (", x);
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print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true);
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print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false);
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print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false);
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print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false);
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pr_cont(")\n");
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}
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2023-05-01 17:19:27 +08:00
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static void print_ecfg(unsigned long x)
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{
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printk(" ECFG: %08lx (", x);
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print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x));
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|
|
pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x));
|
|
|
|
|
}
|
|
|
|
|
|
2023-05-01 17:19:27 +08:00
|
|
|
static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* LoongArch users and developers are probably more familiar with
|
|
|
|
|
* those names found in the ISA manual, so we are going to print out
|
|
|
|
|
* the latter. This will require some mapping.
|
|
|
|
|
*/
|
|
|
|
|
switch (ecode) {
|
|
|
|
|
case EXCCODE_RSV: return "INT";
|
|
|
|
|
case EXCCODE_TLBL: return "PIL";
|
|
|
|
|
case EXCCODE_TLBS: return "PIS";
|
|
|
|
|
case EXCCODE_TLBI: return "PIF";
|
|
|
|
|
case EXCCODE_TLBM: return "PME";
|
|
|
|
|
case EXCCODE_TLBNR: return "PNR";
|
|
|
|
|
case EXCCODE_TLBNX: return "PNX";
|
|
|
|
|
case EXCCODE_TLBPE: return "PPI";
|
|
|
|
|
case EXCCODE_ADE:
|
|
|
|
|
switch (esubcode) {
|
|
|
|
|
case EXSUBCODE_ADEF: return "ADEF";
|
|
|
|
|
case EXSUBCODE_ADEM: return "ADEM";
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EXCCODE_ALE: return "ALE";
|
|
|
|
|
case EXCCODE_BCE: return "BCE";
|
|
|
|
|
case EXCCODE_SYS: return "SYS";
|
|
|
|
|
case EXCCODE_BP: return "BRK";
|
|
|
|
|
case EXCCODE_INE: return "INE";
|
|
|
|
|
case EXCCODE_IPE: return "IPE";
|
|
|
|
|
case EXCCODE_FPDIS: return "FPD";
|
|
|
|
|
case EXCCODE_LSXDIS: return "SXD";
|
|
|
|
|
case EXCCODE_LASXDIS: return "ASXD";
|
|
|
|
|
case EXCCODE_FPE:
|
|
|
|
|
switch (esubcode) {
|
|
|
|
|
case EXCSUBCODE_FPE: return "FPE";
|
|
|
|
|
case EXCSUBCODE_VFPE: return "VFPE";
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EXCCODE_WATCH:
|
|
|
|
|
switch (esubcode) {
|
|
|
|
|
case EXCSUBCODE_WPEF: return "WPEF";
|
|
|
|
|
case EXCSUBCODE_WPEM: return "WPEM";
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EXCCODE_BTDIS: return "BTD";
|
|
|
|
|
case EXCCODE_BTE: return "BTE";
|
|
|
|
|
case EXCCODE_GSPR: return "GSPR";
|
|
|
|
|
case EXCCODE_HVC: return "HVC";
|
|
|
|
|
case EXCCODE_GCM:
|
|
|
|
|
switch (esubcode) {
|
|
|
|
|
case EXCSUBCODE_GCSC: return "GCSC";
|
|
|
|
|
case EXCSUBCODE_GCHC: return "GCHC";
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/*
|
|
|
|
|
* The manual did not mention the EXCCODE_SE case, but print out it
|
|
|
|
|
* nevertheless.
|
|
|
|
|
*/
|
|
|
|
|
case EXCCODE_SE: return "SE";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return "???";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void print_estat(unsigned long x)
|
|
|
|
|
{
|
|
|
|
|
unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x);
|
|
|
|
|
unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x);
|
|
|
|
|
|
|
|
|
|
printk("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode));
|
|
|
|
|
print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x));
|
|
|
|
|
pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode);
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
static void __show_regs(const struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
const int field = 2 * sizeof(unsigned long);
|
2023-05-01 17:19:27 +08:00
|
|
|
unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
show_regs_print_info(KERN_DEFAULT);
|
|
|
|
|
|
2023-05-01 17:19:10 +08:00
|
|
|
/* Print saved GPRs except $zero (substituting with PC/ERA) */
|
|
|
|
|
#define GPR_FIELD(x) field, regs->regs[x]
|
|
|
|
|
printk("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n",
|
|
|
|
|
field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3));
|
|
|
|
|
printk("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n",
|
|
|
|
|
GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7));
|
|
|
|
|
printk("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n",
|
|
|
|
|
GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11));
|
|
|
|
|
printk("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n",
|
|
|
|
|
GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15));
|
|
|
|
|
printk("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n",
|
|
|
|
|
GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19));
|
|
|
|
|
printk("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n",
|
|
|
|
|
GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23));
|
|
|
|
|
printk("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n",
|
|
|
|
|
GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27));
|
|
|
|
|
printk("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n",
|
|
|
|
|
GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31));
|
|
|
|
|
|
|
|
|
|
/* The slot for $zero is reused as the syscall restart flag */
|
|
|
|
|
if (regs->regs[0])
|
|
|
|
|
printk("syscall restart flag: %0*lx\n", GPR_FIELD(0));
|
2023-05-01 17:19:10 +08:00
|
|
|
|
|
|
|
|
if (user_mode(regs)) {
|
|
|
|
|
printk(" ra: %0*lx\n", GPR_FIELD(1));
|
|
|
|
|
printk(" ERA: %0*lx\n", field, regs->csr_era);
|
|
|
|
|
} else {
|
|
|
|
|
printk(" ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]);
|
|
|
|
|
printk(" ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era);
|
|
|
|
|
}
|
2023-05-01 17:19:10 +08:00
|
|
|
#undef GPR_FIELD
|
2022-05-31 18:04:11 +08:00
|
|
|
|
2023-05-01 17:19:10 +08:00
|
|
|
/* Print saved important CSRs */
|
2023-05-01 17:19:10 +08:00
|
|
|
print_crmd(regs->csr_crmd);
|
2023-05-01 17:19:10 +08:00
|
|
|
print_prmd(regs->csr_prmd);
|
2023-05-01 17:19:27 +08:00
|
|
|
print_euen(regs->csr_euen);
|
2023-05-01 17:19:27 +08:00
|
|
|
print_ecfg(regs->csr_ecfg);
|
2023-05-01 17:19:27 +08:00
|
|
|
print_estat(regs->csr_estat);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
|
2023-05-01 17:19:27 +08:00
|
|
|
printk(" BADV: %0*lx\n", field, regs->csr_badvaddr);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
2023-05-01 17:19:27 +08:00
|
|
|
printk(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
|
|
|
|
|
cpu_family_string(), cpu_full_name_string());
|
2022-05-31 18:04:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void show_regs(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
__show_regs((struct pt_regs *)regs);
|
|
|
|
|
dump_stack();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void show_registers(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
__show_regs(regs);
|
|
|
|
|
print_modules();
|
|
|
|
|
printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
|
|
|
|
|
current->comm, current->pid, current_thread_info(), current);
|
|
|
|
|
|
|
|
|
|
show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
|
|
|
|
|
show_code((void *)regs->csr_era, user_mode(regs));
|
|
|
|
|
printk("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DEFINE_RAW_SPINLOCK(die_lock);
|
|
|
|
|
|
2023-08-25 23:40:26 +08:00
|
|
|
void die(const char *str, struct pt_regs *regs)
|
2022-05-31 18:04:11 +08:00
|
|
|
{
|
2023-08-25 23:40:26 +08:00
|
|
|
int ret;
|
2022-05-31 18:04:11 +08:00
|
|
|
static int die_counter;
|
|
|
|
|
|
|
|
|
|
oops_enter();
|
|
|
|
|
|
2023-08-25 23:40:26 +08:00
|
|
|
ret = notify_die(DIE_OOPS, str, regs, 0,
|
|
|
|
|
current->thread.trap_nr, SIGSEGV);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
console_verbose();
|
|
|
|
|
raw_spin_lock_irq(&die_lock);
|
|
|
|
|
bust_spinlocks(1);
|
|
|
|
|
|
|
|
|
|
printk("%s[#%d]:\n", str, ++die_counter);
|
|
|
|
|
show_registers(regs);
|
|
|
|
|
add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
|
|
|
|
|
raw_spin_unlock_irq(&die_lock);
|
|
|
|
|
|
|
|
|
|
oops_exit();
|
|
|
|
|
|
2023-08-25 23:40:26 +08:00
|
|
|
if (ret == NOTIFY_STOP)
|
|
|
|
|
return;
|
|
|
|
|
|
LoongArch: Add kdump support
This patch adds support for kdump. In kdump case the normal kernel will
reserve a region for the crash kernel and jump there on panic.
Arch-specific functions are added to allow for implementing a crash dump
file interface, /proc/vmcore, which can be viewed as a ELF file.
A user-space tool, such as kexec-tools, is responsible for allocating a
separate region for the core's ELF header within the crash kdump kernel
memory and filling it in when executing kexec_load().
Then, its location will be advertised to the crash dump kernel via a
command line argument "elfcorehdr=", and the crash dump kernel will
preserve this region for later use with arch_reserve_vmcore() at boot
time.
At the same time, the crash kdump kernel is also limited within the
"crashkernel" area via a command line argument "mem=", so as not to
destroy the original kernel dump data.
In the crash dump kernel environment, /proc/vmcore is used to access the
primary kernel's memory with copy_oldmem_page().
I tested kdump on LoongArch machines (Loongson-3A5000) and it works as
expected (suggested crashkernel parameter is "crashkernel=512M@2560M"),
you may test it by triggering a crash through /proc/sysrq-trigger:
$ sudo kexec -p /boot/vmlinux-kdump --reuse-cmdline --append="nr_cpus=1"
# echo c > /proc/sysrq-trigger
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:19 +08:00
|
|
|
if (regs && kexec_should_crash(current))
|
|
|
|
|
crash_kexec(regs);
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
if (in_interrupt())
|
|
|
|
|
panic("Fatal exception in interrupt");
|
|
|
|
|
|
|
|
|
|
if (panic_on_oops)
|
|
|
|
|
panic("Fatal exception");
|
|
|
|
|
|
2023-08-25 23:40:26 +08:00
|
|
|
make_task_dead(SIGSEGV);
|
2022-05-31 18:04:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void setup_vint_size(unsigned int size)
|
|
|
|
|
{
|
|
|
|
|
unsigned int vs;
|
|
|
|
|
|
|
|
|
|
vs = ilog2(size/4);
|
|
|
|
|
|
|
|
|
|
if (vs == 0 || vs > 7)
|
|
|
|
|
panic("vint_size %d Not support yet", vs);
|
|
|
|
|
|
|
|
|
|
csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Send SIGFPE according to FCSR Cause bits, which must have already
|
|
|
|
|
* been masked against Enable bits. This is impotant as Inexact can
|
|
|
|
|
* happen together with Overflow or Underflow, and `ptrace' can set
|
|
|
|
|
* any bits.
|
|
|
|
|
*/
|
2023-09-20 14:26:28 +08:00
|
|
|
static void force_fcsr_sig(unsigned long fcsr,
|
|
|
|
|
void __user *fault_addr, struct task_struct *tsk)
|
2022-05-31 18:04:11 +08:00
|
|
|
{
|
|
|
|
|
int si_code = FPE_FLTUNK;
|
|
|
|
|
|
|
|
|
|
if (fcsr & FPU_CSR_INV_X)
|
|
|
|
|
si_code = FPE_FLTINV;
|
|
|
|
|
else if (fcsr & FPU_CSR_DIV_X)
|
|
|
|
|
si_code = FPE_FLTDIV;
|
|
|
|
|
else if (fcsr & FPU_CSR_OVF_X)
|
|
|
|
|
si_code = FPE_FLTOVF;
|
|
|
|
|
else if (fcsr & FPU_CSR_UDF_X)
|
|
|
|
|
si_code = FPE_FLTUND;
|
|
|
|
|
else if (fcsr & FPU_CSR_INE_X)
|
|
|
|
|
si_code = FPE_FLTRES;
|
|
|
|
|
|
|
|
|
|
force_sig_fault(SIGFPE, si_code, fault_addr);
|
|
|
|
|
}
|
|
|
|
|
|
2023-09-20 14:26:28 +08:00
|
|
|
static int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr)
|
2022-05-31 18:04:11 +08:00
|
|
|
{
|
|
|
|
|
int si_code;
|
|
|
|
|
|
|
|
|
|
switch (sig) {
|
|
|
|
|
case 0:
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
case SIGFPE:
|
|
|
|
|
force_fcsr_sig(fcsr, fault_addr, current);
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
case SIGBUS:
|
|
|
|
|
force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
case SIGSEGV:
|
|
|
|
|
mmap_read_lock(current->mm);
|
|
|
|
|
if (vma_lookup(current->mm, (unsigned long)fault_addr))
|
|
|
|
|
si_code = SEGV_ACCERR;
|
|
|
|
|
else
|
|
|
|
|
si_code = SEGV_MAPERR;
|
|
|
|
|
mmap_read_unlock(current->mm);
|
|
|
|
|
force_sig_fault(SIGSEGV, si_code, fault_addr);
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
force_sig(sig);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Delayed fp exceptions when doing a lazy ctx switch
|
|
|
|
|
*/
|
|
|
|
|
asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr)
|
|
|
|
|
{
|
|
|
|
|
int sig;
|
|
|
|
|
void __user *fault_addr;
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
|
|
|
|
|
SIGFPE) == NOTIFY_STOP)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
/* Clear FCSR.Cause before enabling interrupts */
|
|
|
|
|
write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr));
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
|
|
|
|
|
die_if_kernel("FP exception in kernel code", regs);
|
|
|
|
|
|
|
|
|
|
sig = SIGFPE;
|
|
|
|
|
fault_addr = (void __user *) regs->csr_era;
|
|
|
|
|
|
|
|
|
|
/* Send a signal if required. */
|
|
|
|
|
process_fpemu_return(sig, fault_addr, fcsr);
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_ade(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
die_if_kernel("Kernel ade access", regs);
|
|
|
|
|
force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);
|
|
|
|
|
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
2022-12-10 22:39:59 +08:00
|
|
|
/* sysctl hooks */
|
|
|
|
|
int unaligned_enabled __read_mostly = 1; /* Enabled by default */
|
|
|
|
|
int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
asmlinkage void noinstr do_ale(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
2023-02-25 15:52:56 +08:00
|
|
|
#ifndef CONFIG_ARCH_STRICT_ALIGN
|
|
|
|
|
die_if_kernel("Kernel ale access", regs);
|
|
|
|
|
force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
|
|
|
|
|
#else
|
|
|
|
|
unsigned int *pc;
|
|
|
|
|
|
2024-10-21 22:11:19 +08:00
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
|
2022-12-10 22:39:59 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Did we catch a fault trying to load an instruction?
|
|
|
|
|
*/
|
|
|
|
|
if (regs->csr_badvaddr == regs->csr_era)
|
|
|
|
|
goto sigbus;
|
|
|
|
|
if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
|
|
|
|
|
goto sigbus;
|
|
|
|
|
if (!unaligned_enabled)
|
|
|
|
|
goto sigbus;
|
|
|
|
|
if (!no_unaligned_warning)
|
|
|
|
|
show_registers(regs);
|
|
|
|
|
|
|
|
|
|
pc = (unsigned int *)exception_era(regs);
|
|
|
|
|
|
|
|
|
|
emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc);
|
|
|
|
|
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
sigbus:
|
2022-05-31 18:04:11 +08:00
|
|
|
die_if_kernel("Kernel ale access", regs);
|
|
|
|
|
force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
|
2022-12-10 22:39:59 +08:00
|
|
|
out:
|
2024-10-21 22:11:19 +08:00
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_disable();
|
2023-02-25 15:52:56 +08:00
|
|
|
#endif
|
2022-05-31 18:04:11 +08:00
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-12 16:36:19 +08:00
|
|
|
#ifdef CONFIG_GENERIC_BUG
|
|
|
|
|
int is_valid_bugaddr(unsigned long addr)
|
|
|
|
|
{
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_GENERIC_BUG */
|
|
|
|
|
|
|
|
|
|
static void bug_handler(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
switch (report_bug(regs->csr_era, regs)) {
|
|
|
|
|
case BUG_TRAP_TYPE_BUG:
|
|
|
|
|
case BUG_TRAP_TYPE_NONE:
|
|
|
|
|
die_if_kernel("Oops - BUG", regs);
|
|
|
|
|
force_sig(SIGTRAP);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BUG_TRAP_TYPE_WARN:
|
|
|
|
|
/* Skip the BUG instruction and continue */
|
|
|
|
|
regs->csr_era += LOONGARCH_INSN_SIZE;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
LoongArch: Relay BCE exceptions to userland as SIGSEGV with si_code=SEGV_BNDERR
SEGV_BNDERR was introduced initially for supporting the Intel MPX, but
fell into disuse after the MPX support was removed. The LoongArch
bounds-checking instructions behave very differently than MPX, but
overall the interface is still kind of suitable for conveying the
information to userland when bounds-checking assertions trigger, so we
wouldn't have to invent more UAPI. Specifically, when the BCE triggers,
a SEGV_BNDERR is sent to userland, with si_addr set to the out-of-bounds
address or value (in asrt{gt,le}'s case), and one of si_lower or
si_upper set to the configured bound depending on the faulting
instruction. The other bound is set to either 0 or ULONG_MAX to resemble
a range with both lower and upper bounds.
Note that it is possible to have si_addr == si_lower in case of a
failing asrtgt or {ld,st}gt, because those instructions test for strict
greater-than relationship. This should not pose a problem for userland,
though, because the faulting PC is available for the application to
associate back to the exact instruction for figuring out the
expectation.
Example exception context generated by a faulting `asrtgt.d t0, t1`
(assert t0 > t1 or BCE) with t0=100 and t1=200:
> pc 00005555558206a4 ra 00007ffff2d854fc tp 00007ffff2f2f180 sp 00007ffffbf9fb80
> a0 0000000000000002 a1 00007ffffbf9fce8 a2 00007ffffbf9fd00 a3 00007ffff2ed4558
> a4 0000000000000000 a5 00007ffff2f044c8 a6 00007ffffbf9fce0 a7 fffffffffffff000
> t0 0000000000000064 t1 00000000000000c8 t2 00007ffffbfa2d5e t3 00007ffff2f12aa0
> t4 00007ffff2ed6158 t5 00007ffff2ed6158 t6 000000000000002e t7 0000000003d8f538
> t8 0000000000000005 u0 0000000000000000 s9 0000000000000000 s0 00007ffffbf9fce8
> s1 0000000000000002 s2 0000000000000000 s3 00007ffff2f2c038 s4 0000555555820610
> s5 00007ffff2ed5000 s6 0000555555827e38 s7 00007ffffbf9fd00 s8 0000555555827e38
> ra: 00007ffff2d854fc
> ERA: 00005555558206a4
> CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE)
> PRMD: 00000007 (PPLV3 +PIE -PWE)
> EUEN: 00000000 (-FPE -SXE -ASXE -BTE)
> ECFG: 0007181c (LIE=2-4,11-12 VS=7)
> ESTAT: 000a0000 [BCE] (IS= ECode=10 EsubCode=0)
> PRID: 0014c010 (Loongson-64bit, Loongson-3A5000)
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2023-05-01 17:19:27 +08:00
|
|
|
asmlinkage void noinstr do_bce(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
bool user = user_mode(regs);
|
|
|
|
|
unsigned long era = exception_era(regs);
|
|
|
|
|
u64 badv = 0, lower = 0, upper = ULONG_MAX;
|
|
|
|
|
union loongarch_instruction insn;
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
|
|
|
|
|
current->thread.trap_nr = read_csr_excode();
|
|
|
|
|
|
|
|
|
|
die_if_kernel("Bounds check error in kernel code", regs);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Pull out the address that failed bounds checking, and the lower /
|
|
|
|
|
* upper bound, by minimally looking at the faulting instruction word
|
|
|
|
|
* and reading from the correct register.
|
|
|
|
|
*/
|
|
|
|
|
if (__get_inst(&insn.word, (u32 *)era, user))
|
|
|
|
|
goto bad_era;
|
|
|
|
|
|
|
|
|
|
switch (insn.reg3_format.opcode) {
|
|
|
|
|
case asrtle_op:
|
|
|
|
|
if (insn.reg3_format.rd != 0)
|
|
|
|
|
break; /* not asrtle */
|
|
|
|
|
badv = regs->regs[insn.reg3_format.rj];
|
|
|
|
|
upper = regs->regs[insn.reg3_format.rk];
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case asrtgt_op:
|
|
|
|
|
if (insn.reg3_format.rd != 0)
|
|
|
|
|
break; /* not asrtgt */
|
|
|
|
|
badv = regs->regs[insn.reg3_format.rj];
|
|
|
|
|
lower = regs->regs[insn.reg3_format.rk];
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ldleb_op:
|
|
|
|
|
case ldleh_op:
|
|
|
|
|
case ldlew_op:
|
|
|
|
|
case ldled_op:
|
|
|
|
|
case stleb_op:
|
|
|
|
|
case stleh_op:
|
|
|
|
|
case stlew_op:
|
|
|
|
|
case stled_op:
|
|
|
|
|
case fldles_op:
|
|
|
|
|
case fldled_op:
|
|
|
|
|
case fstles_op:
|
|
|
|
|
case fstled_op:
|
|
|
|
|
badv = regs->regs[insn.reg3_format.rj];
|
|
|
|
|
upper = regs->regs[insn.reg3_format.rk];
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ldgtb_op:
|
|
|
|
|
case ldgth_op:
|
|
|
|
|
case ldgtw_op:
|
|
|
|
|
case ldgtd_op:
|
|
|
|
|
case stgtb_op:
|
|
|
|
|
case stgth_op:
|
|
|
|
|
case stgtw_op:
|
|
|
|
|
case stgtd_op:
|
|
|
|
|
case fldgts_op:
|
|
|
|
|
case fldgtd_op:
|
|
|
|
|
case fstgts_op:
|
|
|
|
|
case fstgtd_op:
|
|
|
|
|
badv = regs->regs[insn.reg3_format.rj];
|
|
|
|
|
lower = regs->regs[insn.reg3_format.rk];
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper);
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
bad_era:
|
|
|
|
|
/*
|
|
|
|
|
* Cannot pull out the instruction word, hence cannot provide more
|
|
|
|
|
* info than a regular SIGSEGV in this case.
|
|
|
|
|
*/
|
|
|
|
|
force_sig(SIGSEGV);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
asmlinkage void noinstr do_bp(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
bool user = user_mode(regs);
|
|
|
|
|
unsigned int opcode, bcode;
|
|
|
|
|
unsigned long era = exception_era(regs);
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
2023-02-25 15:52:57 +08:00
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
if (__get_inst(&opcode, (u32 *)era, user))
|
|
|
|
|
goto out_sigsegv;
|
|
|
|
|
|
|
|
|
|
bcode = (opcode & 0x7fff);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* notify the kprobe handlers, if instruction is likely to
|
|
|
|
|
* pertain to them.
|
|
|
|
|
*/
|
|
|
|
|
switch (bcode) {
|
2023-09-06 22:53:55 +08:00
|
|
|
case BRK_KDB:
|
|
|
|
|
if (kgdb_breakpoint_handler(regs))
|
|
|
|
|
goto out;
|
|
|
|
|
else
|
|
|
|
|
break;
|
2022-05-31 18:04:11 +08:00
|
|
|
case BRK_KPROBE_BP:
|
2023-02-25 15:52:57 +08:00
|
|
|
if (kprobe_breakpoint_handler(regs))
|
2022-05-31 18:04:11 +08:00
|
|
|
goto out;
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
case BRK_KPROBE_SSTEPBP:
|
2023-02-25 15:52:57 +08:00
|
|
|
if (kprobe_singlestep_handler(regs))
|
2022-05-31 18:04:11 +08:00
|
|
|
goto out;
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
case BRK_UPROBE_BP:
|
2023-06-29 20:58:44 +08:00
|
|
|
if (uprobe_breakpoint_handler(regs))
|
2022-05-31 18:04:11 +08:00
|
|
|
goto out;
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
case BRK_UPROBE_XOLBP:
|
2023-06-29 20:58:44 +08:00
|
|
|
if (uprobe_singlestep_handler(regs))
|
2022-05-31 18:04:11 +08:00
|
|
|
goto out;
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2023-06-29 20:58:44 +08:00
|
|
|
current->thread.trap_nr = read_csr_excode();
|
2022-05-31 18:04:11 +08:00
|
|
|
if (notify_die(DIE_TRAP, "Break", regs, bcode,
|
|
|
|
|
current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
|
|
|
|
|
goto out;
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (bcode) {
|
|
|
|
|
case BRK_BUG:
|
2022-10-12 16:36:19 +08:00
|
|
|
bug_handler(regs);
|
2022-05-31 18:04:11 +08:00
|
|
|
break;
|
|
|
|
|
case BRK_DIVZERO:
|
|
|
|
|
die_if_kernel("Break instruction in kernel code", regs);
|
|
|
|
|
force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era);
|
|
|
|
|
break;
|
|
|
|
|
case BRK_OVERFLOW:
|
|
|
|
|
die_if_kernel("Break instruction in kernel code", regs);
|
|
|
|
|
force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
die_if_kernel("Break instruction in kernel code", regs);
|
|
|
|
|
force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
2023-02-25 15:52:57 +08:00
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
out_sigsegv:
|
|
|
|
|
force_sig(SIGSEGV);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_watch(struct pt_regs *regs)
|
|
|
|
|
{
|
2023-02-25 15:52:57 +08:00
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
2023-02-25 15:52:57 +08:00
|
|
|
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
2022-05-31 18:04:11 +08:00
|
|
|
pr_warn("Hardware watch point handler not implemented!\n");
|
2023-02-25 15:52:57 +08:00
|
|
|
#else
|
2023-09-06 22:53:55 +08:00
|
|
|
if (kgdb_breakpoint_handler(regs))
|
|
|
|
|
goto out;
|
|
|
|
|
|
2023-02-25 15:52:57 +08:00
|
|
|
if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) {
|
|
|
|
|
int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1);
|
|
|
|
|
unsigned long pc = instruction_pointer(regs);
|
|
|
|
|
union loongarch_instruction *ip = (union loongarch_instruction *)pc;
|
|
|
|
|
|
|
|
|
|
if (llbit) {
|
|
|
|
|
/*
|
|
|
|
|
* When the ll-sc combo is encountered, it is regarded as an single
|
|
|
|
|
* instruction. So don't clear llbit and reset CSR.FWPS.Skip until
|
|
|
|
|
* the llsc execution is completed.
|
|
|
|
|
*/
|
|
|
|
|
csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
|
|
|
|
|
csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2023-02-25 15:52:57 +08:00
|
|
|
|
2023-02-25 15:52:57 +08:00
|
|
|
if (pc == current->thread.single_step) {
|
|
|
|
|
/*
|
|
|
|
|
* Certain insns are occasionally not skipped when CSR.FWPS.Skip is
|
|
|
|
|
* set, such as fld.d/fst.d. So singlestep needs to compare whether
|
|
|
|
|
* the csr_era is equal to the value of singlestep which last time set.
|
|
|
|
|
*/
|
|
|
|
|
if (!is_self_loop_ins(ip, regs)) {
|
|
|
|
|
/*
|
|
|
|
|
* Check if the given instruction the target pc is equal to the
|
|
|
|
|
* current pc, If yes, then we should not set the CSR.FWPS.SKIP
|
|
|
|
|
* bit to break the original instruction stream.
|
|
|
|
|
*/
|
|
|
|
|
csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
breakpoint_handler(regs);
|
|
|
|
|
watchpoint_handler(regs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
force_sig(SIGTRAP);
|
|
|
|
|
out:
|
|
|
|
|
#endif
|
2023-02-25 15:52:57 +08:00
|
|
|
irqentry_exit(regs, state);
|
2022-05-31 18:04:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_ri(struct pt_regs *regs)
|
|
|
|
|
{
|
2022-09-26 22:33:39 +08:00
|
|
|
int status = SIGILL;
|
2023-09-20 14:26:28 +08:00
|
|
|
unsigned int __maybe_unused opcode;
|
2022-05-31 18:04:11 +08:00
|
|
|
unsigned int __user *era = (unsigned int __user *)exception_era(regs);
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
current->thread.trap_nr = read_csr_excode();
|
|
|
|
|
|
|
|
|
|
if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
|
|
|
|
|
SIGILL) == NOTIFY_STOP)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
die_if_kernel("Reserved instruction in kernel code", regs);
|
|
|
|
|
|
|
|
|
|
if (unlikely(get_user(opcode, era) < 0)) {
|
|
|
|
|
status = SIGSEGV;
|
|
|
|
|
current->thread.error_code = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-26 22:33:39 +08:00
|
|
|
force_sig(status);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void init_restore_fp(void)
|
|
|
|
|
{
|
|
|
|
|
if (!used_math()) {
|
|
|
|
|
/* First time FP context user. */
|
|
|
|
|
init_fpu();
|
|
|
|
|
} else {
|
|
|
|
|
/* This task has formerly used the FP context */
|
|
|
|
|
if (!is_fpu_owner())
|
|
|
|
|
own_fpu_inatomic(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
BUG_ON(!is_fp_enabled());
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-29 20:58:43 +08:00
|
|
|
static void init_restore_lsx(void)
|
|
|
|
|
{
|
|
|
|
|
enable_lsx();
|
|
|
|
|
|
|
|
|
|
if (!thread_lsx_context_live()) {
|
|
|
|
|
/* First time LSX context user */
|
|
|
|
|
init_restore_fp();
|
|
|
|
|
init_lsx_upper();
|
|
|
|
|
set_thread_flag(TIF_LSX_CTX_LIVE);
|
|
|
|
|
} else {
|
|
|
|
|
if (!is_simd_owner()) {
|
|
|
|
|
if (is_fpu_owner()) {
|
|
|
|
|
restore_lsx_upper(current);
|
|
|
|
|
} else {
|
|
|
|
|
__own_fpu();
|
|
|
|
|
restore_lsx(current);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
set_thread_flag(TIF_USEDSIMD);
|
|
|
|
|
|
|
|
|
|
BUG_ON(!is_fp_enabled());
|
|
|
|
|
BUG_ON(!is_lsx_enabled());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void init_restore_lasx(void)
|
|
|
|
|
{
|
|
|
|
|
enable_lasx();
|
|
|
|
|
|
|
|
|
|
if (!thread_lasx_context_live()) {
|
|
|
|
|
/* First time LASX context user */
|
|
|
|
|
init_restore_lsx();
|
|
|
|
|
init_lasx_upper();
|
|
|
|
|
set_thread_flag(TIF_LASX_CTX_LIVE);
|
|
|
|
|
} else {
|
|
|
|
|
if (is_fpu_owner() || is_simd_owner()) {
|
|
|
|
|
init_restore_lsx();
|
|
|
|
|
restore_lasx_upper(current);
|
|
|
|
|
} else {
|
|
|
|
|
__own_fpu();
|
|
|
|
|
enable_lsx();
|
|
|
|
|
restore_lasx(current);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
set_thread_flag(TIF_USEDSIMD);
|
|
|
|
|
|
|
|
|
|
BUG_ON(!is_fp_enabled());
|
|
|
|
|
BUG_ON(!is_lsx_enabled());
|
|
|
|
|
BUG_ON(!is_lasx_enabled());
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
asmlinkage void noinstr do_fpu(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
die_if_kernel("do_fpu invoked from kernel context!", regs);
|
2023-06-29 20:58:43 +08:00
|
|
|
BUG_ON(is_lsx_enabled());
|
|
|
|
|
BUG_ON(is_lasx_enabled());
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
|
init_restore_fp();
|
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_lsx(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
local_irq_enable();
|
2023-06-29 20:58:43 +08:00
|
|
|
if (!cpu_has_lsx) {
|
|
|
|
|
force_sig(SIGILL);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
die_if_kernel("do_lsx invoked from kernel context!", regs);
|
|
|
|
|
BUG_ON(is_lasx_enabled());
|
2022-05-31 18:04:11 +08:00
|
|
|
|
2023-06-29 20:58:43 +08:00
|
|
|
preempt_disable();
|
|
|
|
|
init_restore_lsx();
|
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
local_irq_disable();
|
2022-05-31 18:04:11 +08:00
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_lasx(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
local_irq_enable();
|
2023-06-29 20:58:43 +08:00
|
|
|
if (!cpu_has_lasx) {
|
|
|
|
|
force_sig(SIGILL);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
die_if_kernel("do_lasx invoked from kernel context!", regs);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
2023-06-29 20:58:43 +08:00
|
|
|
preempt_disable();
|
|
|
|
|
init_restore_lasx();
|
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
local_irq_disable();
|
2022-05-31 18:04:11 +08:00
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
2023-09-06 22:53:55 +08:00
|
|
|
static void init_restore_lbt(void)
|
|
|
|
|
{
|
|
|
|
|
if (!thread_lbt_context_live()) {
|
|
|
|
|
/* First time LBT context user */
|
|
|
|
|
init_lbt();
|
|
|
|
|
set_thread_flag(TIF_LBT_CTX_LIVE);
|
|
|
|
|
} else {
|
|
|
|
|
if (!is_lbt_owner())
|
|
|
|
|
own_lbt_inatomic(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
BUG_ON(!is_lbt_enabled());
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-31 18:04:11 +08:00
|
|
|
asmlinkage void noinstr do_lbt(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
2023-09-06 22:53:55 +08:00
|
|
|
/*
|
|
|
|
|
* BTD (Binary Translation Disable exception) can be triggered
|
|
|
|
|
* during FP save/restore if TM (Top Mode) is on, which may
|
|
|
|
|
* cause irq_enable during 'switch_to'. To avoid this situation
|
|
|
|
|
* (including the user using 'MOVGR2GCSR' to turn on TM, which
|
|
|
|
|
* will not trigger the BTE), we need to check PRMD first.
|
|
|
|
|
*/
|
|
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
|
|
|
|
|
if (!cpu_has_lbt) {
|
|
|
|
|
force_sig(SIGILL);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
BUG_ON(is_lbt_enabled());
|
|
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
|
init_restore_lbt();
|
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
if (regs->csr_prmd & CSR_PRMD_PIE)
|
|
|
|
|
local_irq_disable();
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_reserved(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
/*
|
|
|
|
|
* Game over - no way to handle this if it ever occurs. Most probably
|
|
|
|
|
* caused by a fatal error after another hardware/software error.
|
|
|
|
|
*/
|
|
|
|
|
pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
|
|
|
|
|
read_csr_excode(), current->pid, current->comm);
|
|
|
|
|
die_if_kernel("do_reserved exception", regs);
|
|
|
|
|
force_sig(SIGUNUSED);
|
|
|
|
|
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void cache_parity_error(void)
|
|
|
|
|
{
|
|
|
|
|
/* For the moment, report the problem and hang. */
|
|
|
|
|
pr_err("Cache error exception:\n");
|
|
|
|
|
pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL));
|
2023-06-29 20:58:43 +08:00
|
|
|
pr_err("csr_merrera == %016lx\n", csr_read64(LOONGARCH_CSR_MERRERA));
|
2022-05-31 18:04:11 +08:00
|
|
|
panic("Can't handle the cache error!");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
struct pt_regs *old_regs;
|
|
|
|
|
|
|
|
|
|
irq_enter_rcu();
|
|
|
|
|
old_regs = set_irq_regs(regs);
|
|
|
|
|
handle_arch_irq(regs);
|
|
|
|
|
set_irq_regs(old_regs);
|
|
|
|
|
irq_exit_rcu();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp)
|
|
|
|
|
{
|
|
|
|
|
register int cpu;
|
|
|
|
|
register unsigned long stack;
|
|
|
|
|
irqentry_state_t state = irqentry_enter(regs);
|
|
|
|
|
|
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
|
|
|
|
|
|
if (on_irq_stack(cpu, sp))
|
|
|
|
|
handle_loongarch_irq(regs);
|
|
|
|
|
else {
|
|
|
|
|
stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START;
|
|
|
|
|
|
|
|
|
|
/* Save task's sp on IRQ stack for unwinding */
|
|
|
|
|
*(unsigned long *)stack = sp;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__(
|
|
|
|
|
"move $s0, $sp \n" /* Preserve sp */
|
|
|
|
|
"move $sp, %[stk] \n" /* Switch stack */
|
|
|
|
|
"move $a0, %[regs] \n"
|
|
|
|
|
"bl handle_loongarch_irq \n"
|
|
|
|
|
"move $sp, $s0 \n" /* Restore sp */
|
|
|
|
|
: /* No outputs */
|
|
|
|
|
: [stk] "r" (stack), [regs] "r" (regs)
|
|
|
|
|
: "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0",
|
|
|
|
|
"$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8",
|
|
|
|
|
"memory");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
irqentry_exit(regs, state);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned long eentry;
|
|
|
|
|
unsigned long tlbrentry;
|
|
|
|
|
|
|
|
|
|
long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
|
|
|
|
|
|
|
|
|
|
static void configure_exception_vector(void)
|
|
|
|
|
{
|
|
|
|
|
eentry = (unsigned long)exception_handlers;
|
|
|
|
|
tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE;
|
|
|
|
|
|
|
|
|
|
csr_write64(eentry, LOONGARCH_CSR_EENTRY);
|
|
|
|
|
csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
|
|
|
|
|
csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
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}
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void per_cpu_trap_init(int cpu)
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{
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unsigned int i;
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setup_vint_size(VECSIZE);
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configure_exception_vector();
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if (!cpu_data[cpu].asid_cache)
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cpu_data[cpu].asid_cache = asid_first_version(cpu);
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mmgrab(&init_mm);
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current->active_mm = &init_mm;
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BUG_ON(current->mm);
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enter_lazy_tlb(&init_mm, current);
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/* Initialise exception handlers */
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if (cpu == 0)
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for (i = 0; i < 64; i++)
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set_handler(i * VECSIZE, handle_reserved, VECSIZE);
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|
2022-05-31 18:04:12 +08:00
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|
|
tlb_init(cpu);
|
2022-05-31 18:04:11 +08:00
|
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|
cpu_cache_init();
|
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|
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|
}
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|
|
/* Install CPU exception handler */
|
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|
|
|
void set_handler(unsigned long offset, void *addr, unsigned long size)
|
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|
|
|
{
|
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|
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|
memcpy((void *)(eentry + offset), addr, size);
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|
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local_flush_icache_range(eentry + offset, eentry + offset + size);
|
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|
|
|
}
|
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|
|
|
|
|
static const char panic_null_cerr[] =
|
|
|
|
|
"Trying to set NULL cache error exception handler\n";
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Install uncached CPU exception handler.
|
|
|
|
|
* This is suitable only for the cache error exception which is the only
|
|
|
|
|
* exception handler that is being run uncached.
|
|
|
|
|
*/
|
|
|
|
|
void set_merr_handler(unsigned long offset, void *addr, unsigned long size)
|
|
|
|
|
{
|
|
|
|
|
unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry));
|
|
|
|
|
|
|
|
|
|
if (!addr)
|
|
|
|
|
panic(panic_null_cerr);
|
|
|
|
|
|
|
|
|
|
memcpy((void *)(uncached_eentry + offset), addr, size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init trap_init(void)
|
|
|
|
|
{
|
|
|
|
|
long i;
|
|
|
|
|
|
|
|
|
|
/* Set interrupt vector handler */
|
2023-05-01 17:19:10 +08:00
|
|
|
for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++)
|
2022-05-31 18:04:11 +08:00
|
|
|
set_handler(i * VECSIZE, handle_vint, VECSIZE);
|
|
|
|
|
|
2024-03-11 22:23:47 +08:00
|
|
|
/* Set exception vector handler */
|
|
|
|
|
for (i = EXCCODE_ADE; i <= EXCCODE_BTDIS; i++)
|
|
|
|
|
set_handler(i * VECSIZE, exception_table[i], VECSIZE);
|
2022-05-31 18:04:11 +08:00
|
|
|
|
|
|
|
|
cache_error_setup();
|
|
|
|
|
|
|
|
|
|
local_flush_icache_range(eentry, eentry + 0x400);
|
|
|
|
|
}
|