2019-06-01 16:08:37 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-11-04 22:40:52 +08:00
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/*
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* IMG parallel output controller driver
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*
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* Copyright (C) 2015 Imagination Technologies Ltd.
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*
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* Author: Damien Horsley <Damien.Horsley@imgtec.com>
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#define IMG_PRL_OUT_TX_FIFO 0
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#define IMG_PRL_OUT_CTL 0x4
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#define IMG_PRL_OUT_CTL_CH_MASK BIT(4)
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#define IMG_PRL_OUT_CTL_PACKH_MASK BIT(3)
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#define IMG_PRL_OUT_CTL_EDGE_MASK BIT(2)
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#define IMG_PRL_OUT_CTL_ME_MASK BIT(1)
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#define IMG_PRL_OUT_CTL_SRST_MASK BIT(0)
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struct img_prl_out {
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void __iomem *base;
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struct clk *clk_sys;
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struct clk *clk_ref;
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struct snd_dmaengine_dai_dma_data dma_data;
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struct device *dev;
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struct reset_control *rst;
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};
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static int img_prl_out_suspend(struct device *dev)
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{
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struct img_prl_out *prl = dev_get_drvdata(dev);
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clk_disable_unprepare(prl->clk_ref);
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return 0;
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}
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static int img_prl_out_resume(struct device *dev)
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{
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struct img_prl_out *prl = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(prl->clk_ref);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static inline void img_prl_out_writel(struct img_prl_out *prl,
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u32 val, u32 reg)
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{
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writel(val, prl->base + reg);
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}
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static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
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{
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return readl(prl->base + reg);
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}
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static void img_prl_out_reset(struct img_prl_out *prl)
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{
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u32 ctl;
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ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
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~IMG_PRL_OUT_CTL_ME_MASK;
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reset_control_assert(prl->rst);
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reset_control_deassert(prl->rst);
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img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
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}
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static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
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u32 reg;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
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reg |= IMG_PRL_OUT_CTL_ME_MASK;
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img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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img_prl_out_reset(prl);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
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unsigned int rate, channels;
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u32 reg, control_set = 0;
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rate = params_rate(params);
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channels = params_channels(params);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S32_LE:
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control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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break;
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default:
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return -EINVAL;
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}
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if (channels != 2)
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return -EINVAL;
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clk_set_rate(prl->clk_ref, rate * 256);
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reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
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reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
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img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
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return 0;
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}
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static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
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2015-11-10 22:09:35 +08:00
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u32 reg, control_set = 0;
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2017-10-06 22:57:50 +08:00
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int ret;
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2015-11-04 22:40:52 +08:00
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
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break;
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default:
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return -EINVAL;
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}
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2017-10-06 22:57:50 +08:00
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ret = pm_runtime_get_sync(prl->dev);
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2020-06-14 11:33:43 +08:00
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if (ret < 0) {
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pm_runtime_put_noidle(prl->dev);
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2017-10-06 22:57:50 +08:00
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return ret;
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2020-06-14 11:33:43 +08:00
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}
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2017-10-06 22:57:50 +08:00
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2015-11-04 22:40:52 +08:00
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reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
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reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
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img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
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2017-10-02 18:00:33 +08:00
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pm_runtime_put(prl->dev);
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2015-11-04 22:40:52 +08:00
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return 0;
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}
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static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
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.trigger = img_prl_out_trigger,
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.hw_params = img_prl_out_hw_params,
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.set_fmt = img_prl_out_set_fmt
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};
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static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
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{
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struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
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return 0;
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}
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static struct snd_soc_dai_driver img_prl_out_dai = {
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.probe = img_prl_out_dai_probe,
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
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},
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.ops = &img_prl_out_dai_ops
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};
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static const struct snd_soc_component_driver img_prl_out_component = {
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.name = "img-prl-out"
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};
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static int img_prl_out_probe(struct platform_device *pdev)
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{
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struct img_prl_out *prl;
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struct resource *res;
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void __iomem *base;
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int ret;
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struct device *dev = &pdev->dev;
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prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
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if (!prl)
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return -ENOMEM;
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platform_set_drvdata(pdev, prl);
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prl->dev = &pdev->dev;
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2021-06-15 21:51:58 +08:00
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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2015-11-04 22:40:52 +08:00
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if (IS_ERR(base))
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return PTR_ERR(base);
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prl->base = base;
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2017-07-19 23:26:41 +08:00
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prl->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
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2015-11-04 22:40:52 +08:00
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if (IS_ERR(prl->rst)) {
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if (PTR_ERR(prl->rst) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "No top level reset found\n");
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return PTR_ERR(prl->rst);
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}
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prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
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if (IS_ERR(prl->clk_sys)) {
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if (PTR_ERR(prl->clk_sys) != -EPROBE_DEFER)
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dev_err(dev, "Failed to acquire clock 'sys'\n");
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return PTR_ERR(prl->clk_sys);
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}
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prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
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if (IS_ERR(prl->clk_ref)) {
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if (PTR_ERR(prl->clk_ref) != -EPROBE_DEFER)
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dev_err(dev, "Failed to acquire clock 'ref'\n");
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return PTR_ERR(prl->clk_ref);
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}
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ret = clk_prepare_enable(prl->clk_sys);
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if (ret)
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return ret;
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img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
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img_prl_out_reset(prl);
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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ret = img_prl_out_resume(&pdev->dev);
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if (ret)
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goto err_pm_disable;
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}
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prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
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prl->dma_data.addr_width = 4;
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prl->dma_data.maxburst = 4;
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ret = devm_snd_soc_register_component(&pdev->dev,
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&img_prl_out_component,
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&img_prl_out_dai, 1);
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if (ret)
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goto err_suspend;
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
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if (ret)
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goto err_suspend;
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return 0;
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err_suspend:
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if (!pm_runtime_status_suspended(&pdev->dev))
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img_prl_out_suspend(&pdev->dev);
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err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(prl->clk_sys);
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return ret;
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}
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static int img_prl_out_dev_remove(struct platform_device *pdev)
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{
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struct img_prl_out *prl = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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if (!pm_runtime_status_suspended(&pdev->dev))
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img_prl_out_suspend(&pdev->dev);
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clk_disable_unprepare(prl->clk_sys);
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return 0;
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}
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static const struct of_device_id img_prl_out_of_match[] = {
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{ .compatible = "img,parallel-out" },
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{}
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};
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MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
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static const struct dev_pm_ops img_prl_out_pm_ops = {
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SET_RUNTIME_PM_OPS(img_prl_out_suspend,
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img_prl_out_resume, NULL)
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};
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static struct platform_driver img_prl_out_driver = {
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.driver = {
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.name = "img-parallel-out",
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.of_match_table = img_prl_out_of_match,
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.pm = &img_prl_out_pm_ops
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},
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.probe = img_prl_out_probe,
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.remove = img_prl_out_dev_remove
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};
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module_platform_driver(img_prl_out_driver);
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MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
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MODULE_DESCRIPTION("IMG Parallel Output Driver");
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MODULE_LICENSE("GPL v2");
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