2019-06-04 16:11:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2011-01-05 04:28:14 +08:00
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/*
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* Atheros AR71XX/AR724X/AR913X specific setup
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*
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2012-03-14 17:45:21 +08:00
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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2011-01-05 04:28:14 +08:00
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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2012-03-14 17:45:21 +08:00
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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2011-01-05 04:28:14 +08:00
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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2019-04-19 06:20:22 +08:00
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#include <linux/io.h>
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2018-10-31 06:09:49 +08:00
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#include <linux/memblock.h>
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2011-01-05 04:28:14 +08:00
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#include <linux/err.h>
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#include <linux/clk.h>
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2016-07-24 08:00:15 +08:00
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#include <linux/clk-provider.h>
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2015-05-31 07:52:25 +08:00
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#include <linux/of_fdt.h>
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2019-01-11 22:22:36 +08:00
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#include <linux/irqchip.h>
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2011-01-05 04:28:14 +08:00
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#include <asm/bootinfo.h>
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2013-05-21 22:59:19 +08:00
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#include <asm/idle.h>
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2011-01-05 04:28:14 +08:00
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/reboot.h> /* for _machine_{restart,halt} */
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2011-01-05 04:28:16 +08:00
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#include <asm/mips_machine.h>
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2015-05-31 07:52:25 +08:00
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#include <asm/prom.h>
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#include <asm/fw/fw.h>
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2011-01-05 04:28:14 +08:00
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#define ATH79_SYS_TYPE_LEN 64
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static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
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static void ath79_restart(char *command)
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{
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2018-07-20 19:58:22 +08:00
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local_irq_disable();
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2011-01-05 04:28:14 +08:00
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ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
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for (;;)
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if (cpu_wait)
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cpu_wait();
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}
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static void ath79_halt(void)
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{
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while (1)
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cpu_wait();
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}
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static void __init ath79_detect_sys_type(void)
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{
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char *chip = "????";
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u32 id;
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u32 major;
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u32 minor;
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u32 rev = 0;
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2018-07-20 19:58:19 +08:00
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u32 ver = 1;
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2011-01-05 04:28:14 +08:00
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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switch (major) {
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case REV_ID_MAJOR_AR71XX:
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minor = id & AR71XX_REV_ID_MINOR_MASK;
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rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
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rev &= AR71XX_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR71XX_REV_ID_MINOR_AR7130:
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ath79_soc = ATH79_SOC_AR7130;
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chip = "7130";
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break;
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case AR71XX_REV_ID_MINOR_AR7141:
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ath79_soc = ATH79_SOC_AR7141;
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chip = "7141";
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break;
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case AR71XX_REV_ID_MINOR_AR7161:
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ath79_soc = ATH79_SOC_AR7161;
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chip = "7161";
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break;
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}
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break;
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case REV_ID_MAJOR_AR7240:
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ath79_soc = ATH79_SOC_AR7240;
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chip = "7240";
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2011-06-21 03:26:01 +08:00
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rev = id & AR724X_REV_ID_REVISION_MASK;
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2011-01-05 04:28:14 +08:00
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break;
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case REV_ID_MAJOR_AR7241:
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ath79_soc = ATH79_SOC_AR7241;
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chip = "7241";
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2011-06-21 03:26:01 +08:00
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rev = id & AR724X_REV_ID_REVISION_MASK;
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2011-01-05 04:28:14 +08:00
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break;
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case REV_ID_MAJOR_AR7242:
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ath79_soc = ATH79_SOC_AR7242;
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chip = "7242";
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2011-06-21 03:26:01 +08:00
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rev = id & AR724X_REV_ID_REVISION_MASK;
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2011-01-05 04:28:14 +08:00
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break;
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case REV_ID_MAJOR_AR913X:
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minor = id & AR913X_REV_ID_MINOR_MASK;
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rev = id >> AR913X_REV_ID_REVISION_SHIFT;
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rev &= AR913X_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR913X_REV_ID_MINOR_AR9130:
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ath79_soc = ATH79_SOC_AR9130;
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chip = "9130";
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break;
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case AR913X_REV_ID_MINOR_AR9132:
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ath79_soc = ATH79_SOC_AR9132;
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chip = "9132";
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break;
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}
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break;
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2012-03-14 17:45:20 +08:00
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case REV_ID_MAJOR_AR9330:
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ath79_soc = ATH79_SOC_AR9330;
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chip = "9330";
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9331:
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ath79_soc = ATH79_SOC_AR9331;
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chip = "9331";
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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2012-03-14 17:45:21 +08:00
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case REV_ID_MAJOR_AR9341:
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ath79_soc = ATH79_SOC_AR9341;
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chip = "9341";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9342:
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ath79_soc = ATH79_SOC_AR9342;
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chip = "9342";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9344:
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ath79_soc = ATH79_SOC_AR9344;
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chip = "9344";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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2018-07-20 19:58:19 +08:00
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case REV_ID_MAJOR_QCA9533_V2:
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ver = 2;
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ath79_soc_rev = 2;
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2019-07-16 19:40:16 +08:00
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/* fall through */
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2018-07-20 19:58:19 +08:00
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case REV_ID_MAJOR_QCA9533:
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ath79_soc = ATH79_SOC_QCA9533;
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chip = "9533";
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rev = id & QCA953X_REV_ID_REVISION_MASK;
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break;
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2013-02-15 21:38:16 +08:00
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case REV_ID_MAJOR_QCA9556:
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ath79_soc = ATH79_SOC_QCA9556;
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chip = "9556";
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA9558:
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ath79_soc = ATH79_SOC_QCA9558;
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chip = "9558";
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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2018-07-20 19:58:19 +08:00
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case REV_ID_MAJOR_QCA956X:
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ath79_soc = ATH79_SOC_QCA956X;
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chip = "956X";
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rev = id & QCA956X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_TP9343:
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ath79_soc = ATH79_SOC_TP9343;
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chip = "9343";
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rev = id & QCA956X_REV_ID_REVISION_MASK;
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break;
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2011-01-05 04:28:14 +08:00
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default:
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2011-11-17 23:07:31 +08:00
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panic("ath79: unknown SoC, id:0x%08x", id);
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2011-01-05 04:28:14 +08:00
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}
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2018-07-20 19:58:19 +08:00
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if (ver == 1)
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ath79_soc_rev = rev;
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2011-11-18 08:17:46 +08:00
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2018-07-20 19:58:19 +08:00
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if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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chip, ver, rev);
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else if (soc_is_tp9343())
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sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
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2013-02-15 21:38:16 +08:00
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chip, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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2011-01-05 04:28:14 +08:00
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pr_info("SoC: %s\n", ath79_sys_type);
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}
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const char *get_system_type(void)
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{
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return ath79_sys_type;
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}
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MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 21:38:59 +08:00
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unsigned int get_c0_compare_int(void)
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2011-01-05 04:28:14 +08:00
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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void __init plat_mem_setup(void)
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{
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2015-05-31 07:52:25 +08:00
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unsigned long fdt_start;
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2011-01-05 04:28:14 +08:00
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set_io_port_base(KSEG1);
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2015-05-31 07:52:25 +08:00
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/* Get the position of the FDT passed by the bootloader */
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fdt_start = fw_getenvl("fdt_start");
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if (fdt_start)
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__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
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2016-06-20 17:27:37 +08:00
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else if (fw_passed_dtb)
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__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
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2015-05-31 07:52:25 +08:00
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2020-01-06 16:43:50 +08:00
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ath79_reset_base = ioremap(AR71XX_RESET_BASE,
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2019-01-11 22:22:37 +08:00
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AR71XX_RESET_SIZE);
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2020-01-06 16:43:50 +08:00
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ath79_pll_base = ioremap(AR71XX_PLL_BASE,
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2019-01-11 22:22:37 +08:00
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AR71XX_PLL_SIZE);
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ath79_detect_sys_type();
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ath79_ddr_ctrl_init();
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2016-03-17 11:34:16 +08:00
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2019-01-11 22:22:37 +08:00
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detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
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2016-03-17 11:34:16 +08:00
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2019-01-11 22:22:37 +08:00
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_machine_restart = ath79_restart;
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2011-01-05 04:28:14 +08:00
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_machine_halt = ath79_halt;
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pm_power_off = ath79_halt;
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}
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2019-01-11 22:22:37 +08:00
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void __init plat_time_init(void)
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2016-03-17 11:34:15 +08:00
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{
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struct device_node *np;
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struct clk *clk;
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unsigned long cpu_clk_rate;
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of_clk_init(NULL);
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np = of_get_cpu_node(0, NULL);
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if (!np) {
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pr_err("Failed to get CPU node\n");
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return;
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}
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
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return;
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}
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cpu_clk_rate = clk_get_rate(clk);
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pr_info("CPU clock: %lu.%03lu MHz\n",
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cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
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mips_hpt_frequency = cpu_clk_rate / 2;
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clk_put(clk);
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}
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2019-01-11 22:22:36 +08:00
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void __init arch_init_irq(void)
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{
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irqchip_init();
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}
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2015-05-31 07:52:25 +08:00
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void __init device_tree_init(void)
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{
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unflatten_and_copy_device_tree();
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}
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