2009-04-28 23:21:52 +08:00
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/*
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2013-09-19 03:02:00 +08:00
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* OMAP4 SMP source file. It contains platform specific functions
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2009-04-28 23:21:52 +08:00
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* needed for the linux smp kernel.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Platform file needed for the OMAP4 SMP. This file is based on arm
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* realview smp platform.
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* * Copyright (c) 2002 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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2012-12-28 03:10:24 +08:00
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#include <linux/irqchip/arm-gic.h>
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2009-04-28 23:21:52 +08:00
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2017-03-23 02:01:48 +08:00
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#include <asm/sections.h>
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2009-04-28 23:21:52 +08:00
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#include <asm/smp_scu.h>
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2015-01-06 07:45:45 +08:00
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#include <asm/virt.h>
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2012-02-25 02:34:35 +08:00
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2012-09-21 02:41:14 +08:00
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#include "omap-secure.h"
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2012-09-21 02:41:16 +08:00
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#include "omap-wakeupgen.h"
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2012-05-09 23:08:35 +08:00
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#include <asm/cputype.h>
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2011-11-11 05:45:17 +08:00
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2012-09-01 01:59:07 +08:00
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#include "soc.h"
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2012-02-25 02:34:35 +08:00
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#include "iomap.h"
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2011-11-11 05:45:17 +08:00
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#include "common.h"
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2010-06-17 00:49:49 +08:00
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#include "clockdomain.h"
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
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#include "pm.h"
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2010-06-17 00:49:49 +08:00
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2012-03-19 21:59:41 +08:00
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#define CPU_MASK 0xff0ffff0
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#define CPU_CORTEX_A9 0x410FC090
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#define CPU_CORTEX_A15 0x410FC0F0
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#define OMAP5_CORE_COUNT 0x2
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2017-03-23 02:01:48 +08:00
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#define AUX_CORE_BOOT0_GP_RELEASE 0x020
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#define AUX_CORE_BOOT0_HS_RELEASE 0x200
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2016-06-22 16:59:40 +08:00
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struct omap_smp_config {
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unsigned long cpu1_rstctrl_pa;
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void __iomem *cpu1_rstctrl_va;
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void __iomem *scu_base;
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2017-03-23 02:01:48 +08:00
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void __iomem *wakeupgen_base;
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2016-06-22 16:59:40 +08:00
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void *startup_addr;
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};
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static struct omap_smp_config cfg;
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static const struct omap_smp_config omap443x_cfg __initconst = {
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.cpu1_rstctrl_pa = 0x4824380c,
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.startup_addr = omap4_secondary_startup,
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};
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static const struct omap_smp_config omap446x_cfg __initconst = {
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.cpu1_rstctrl_pa = 0x4824380c,
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.startup_addr = omap4460_secondary_startup,
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};
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static const struct omap_smp_config omap5_cfg __initconst = {
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.cpu1_rstctrl_pa = 0x48243810,
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.startup_addr = omap5_secondary_startup,
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};
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2009-04-28 23:21:52 +08:00
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static DEFINE_SPINLOCK(boot_lock);
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2011-03-03 20:33:25 +08:00
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void __iomem *omap4_get_scu_base(void)
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{
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2016-06-22 16:59:40 +08:00
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return cfg.scu_base;
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2011-03-03 20:33:25 +08:00
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}
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ARM: OMAP5 / DRA7: Introduce workaround for 801819
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Note: the configuration for the workaround needs to be done with
each CPU bringup, since CPU0 bringup is done by bootloader, it is
recommended to have the workaround in the bootloader, kernel also does
ensure that CPU0 has the workaround and makes the workaround active
when CPU1 gets active.
With CONFIG_SMP disabled, it is expected to be done by the bootloader.
This does show significant degradation in synthetic tests such as
mbw (https://packages.qa.debian.org/m/mbw.html)
mbw -n 100 100|grep AVG (on a test platform)
Without enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13406 MiB: 100.00000 Copy: 745.913 MiB/s
AVG Method: DUMB Elapsed: 0.06746 MiB: 100.00000 Copy: 1482.357 MiB/s
AVG Method: MCBLOCK Elapsed: 0.03058 MiB: 100.00000 Copy: 3270.569 MiB/s
After enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13757 MiB: 100.00000 Copy: 726.913 MiB/s
AVG Method: DUMB Elapsed: 0.12024 MiB: 100.00000 Copy: 831.668 MiB/s
AVG Method: MCBLOCK Elapsed: 0.09243 MiB: 100.00000 Copy: 1081.942 MiB/s
Most benchmarks are designed for specific performance analysis, so
overall usecase must be considered before making a decision to
enable/disable the erratum workaround.
Pending internal investigation, the erratum is kept disabled by default.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Tony Lindgren <tony@atomide.com>
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-08-06 23:54:24 +08:00
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#ifdef CONFIG_OMAP5_ERRATA_801819
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void omap5_erratum_workaround_801819(void)
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{
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u32 acr, revidr;
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u32 acr_mask;
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/* REVIDR[3] indicates erratum fix available on silicon */
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asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
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if (revidr & (0x1 << 3))
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return;
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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/*
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* BIT(27) - Disables streaming. All write-allocate lines allocate in
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* the L1 or L2 cache.
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* BIT(25) - Disables streaming. All write-allocate lines allocate in
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* the L1 cache.
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*/
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acr_mask = (0x3 << 25) | (0x3 << 27);
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/* do we already have it done.. if yes, skip expensive smc */
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if ((acr & acr_mask) == acr_mask)
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return;
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acr |= acr_mask;
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omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
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pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
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__func__, smp_processor_id());
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}
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#else
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static inline void omap5_erratum_workaround_801819(void) { }
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#endif
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2013-06-18 03:43:14 +08:00
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static void omap4_secondary_init(unsigned int cpu)
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2009-04-28 23:21:52 +08:00
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{
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2010-06-17 00:49:48 +08:00
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/*
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* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
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* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
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* init and for CPU1, a secure PPA API provided. CPU0 must be ON
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* while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
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* OMAP443X GP devices- SMP bit isn't accessible.
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* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
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*/
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2016-06-22 16:59:40 +08:00
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if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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2010-06-17 00:49:48 +08:00
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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ARM: OMAP5 / DRA7: Introduce workaround for 801819
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Note: the configuration for the workaround needs to be done with
each CPU bringup, since CPU0 bringup is done by bootloader, it is
recommended to have the workaround in the bootloader, kernel also does
ensure that CPU0 has the workaround and makes the workaround active
when CPU1 gets active.
With CONFIG_SMP disabled, it is expected to be done by the bootloader.
This does show significant degradation in synthetic tests such as
mbw (https://packages.qa.debian.org/m/mbw.html)
mbw -n 100 100|grep AVG (on a test platform)
Without enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13406 MiB: 100.00000 Copy: 745.913 MiB/s
AVG Method: DUMB Elapsed: 0.06746 MiB: 100.00000 Copy: 1482.357 MiB/s
AVG Method: MCBLOCK Elapsed: 0.03058 MiB: 100.00000 Copy: 3270.569 MiB/s
After enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13757 MiB: 100.00000 Copy: 726.913 MiB/s
AVG Method: DUMB Elapsed: 0.12024 MiB: 100.00000 Copy: 831.668 MiB/s
AVG Method: MCBLOCK Elapsed: 0.09243 MiB: 100.00000 Copy: 1081.942 MiB/s
Most benchmarks are designed for specific performance analysis, so
overall usecase must be considered before making a decision to
enable/disable the erratum workaround.
Pending internal investigation, the erratum is kept disabled by default.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Tony Lindgren <tony@atomide.com>
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-08-06 23:54:24 +08:00
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if (soc_is_omap54xx() || soc_is_dra7xx()) {
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/*
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* Configure the CNTFRQ register for the secondary cpu's which
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* indicates the frequency of the cpu local timers.
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*/
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2013-10-10 15:43:48 +08:00
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set_cntfreq();
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ARM: OMAP5 / DRA7: Introduce workaround for 801819
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Note: the configuration for the workaround needs to be done with
each CPU bringup, since CPU0 bringup is done by bootloader, it is
recommended to have the workaround in the bootloader, kernel also does
ensure that CPU0 has the workaround and makes the workaround active
when CPU1 gets active.
With CONFIG_SMP disabled, it is expected to be done by the bootloader.
This does show significant degradation in synthetic tests such as
mbw (https://packages.qa.debian.org/m/mbw.html)
mbw -n 100 100|grep AVG (on a test platform)
Without enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13406 MiB: 100.00000 Copy: 745.913 MiB/s
AVG Method: DUMB Elapsed: 0.06746 MiB: 100.00000 Copy: 1482.357 MiB/s
AVG Method: MCBLOCK Elapsed: 0.03058 MiB: 100.00000 Copy: 3270.569 MiB/s
After enabling the erratum:
AVG Method: MEMCPY Elapsed: 0.13757 MiB: 100.00000 Copy: 726.913 MiB/s
AVG Method: DUMB Elapsed: 0.12024 MiB: 100.00000 Copy: 831.668 MiB/s
AVG Method: MCBLOCK Elapsed: 0.09243 MiB: 100.00000 Copy: 1081.942 MiB/s
Most benchmarks are designed for specific performance analysis, so
overall usecase must be considered before making a decision to
enable/disable the erratum workaround.
Pending internal investigation, the erratum is kept disabled by default.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Tony Lindgren <tony@atomide.com>
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-08-06 23:54:24 +08:00
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|
/* Configure ACR to disable streaming WA for 801819 */
|
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|
omap5_erratum_workaround_801819();
|
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|
|
}
|
2013-10-10 15:43:48 +08:00
|
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2009-04-28 23:21:52 +08:00
|
|
|
/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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|
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}
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|
2013-06-18 03:43:14 +08:00
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|
|
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
2009-04-28 23:21:52 +08:00
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{
|
2010-06-17 00:49:49 +08:00
|
|
|
static struct clockdomain *cpu1_clkdm;
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static bool booted;
|
2013-02-09 01:20:58 +08:00
|
|
|
static struct powerdomain *cpu1_pwrdm;
|
2012-05-09 23:08:35 +08:00
|
|
|
|
2009-04-28 23:21:52 +08:00
|
|
|
/*
|
|
|
|
* Set synchronisation state between this boot processor
|
|
|
|
* and the secondary one
|
|
|
|
*/
|
|
|
|
spin_lock(&boot_lock);
|
|
|
|
|
|
|
|
/*
|
2009-12-12 08:16:35 +08:00
|
|
|
* Update the AuxCoreBoot0 with boot state for secondary core.
|
2013-04-05 20:59:02 +08:00
|
|
|
* omap4_secondary_startup() routine will hold the secondary core till
|
2009-04-28 23:21:52 +08:00
|
|
|
* the AuxCoreBoot1 register is updated with cpu state
|
|
|
|
* A barrier is added to ensure that write buffer is drained
|
|
|
|
*/
|
2012-05-09 23:08:35 +08:00
|
|
|
if (omap_secure_apis_support())
|
2017-03-23 02:01:48 +08:00
|
|
|
omap_modify_auxcoreboot0(AUX_CORE_BOOT0_HS_RELEASE,
|
|
|
|
0xfffffdff);
|
2012-05-09 23:08:35 +08:00
|
|
|
else
|
2017-03-23 02:01:48 +08:00
|
|
|
writel_relaxed(AUX_CORE_BOOT0_GP_RELEASE,
|
|
|
|
cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
|
2012-05-09 23:08:35 +08:00
|
|
|
|
2013-02-09 01:20:58 +08:00
|
|
|
if (!cpu1_clkdm && !cpu1_pwrdm) {
|
2010-06-17 00:49:49 +08:00
|
|
|
cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
|
2013-02-09 01:20:58 +08:00
|
|
|
cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
|
|
|
|
}
|
2010-06-17 00:49:49 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The SGI(Software Generated Interrupts) are not wakeup capable
|
|
|
|
* from low power states. This is known limitation on OMAP4 and
|
|
|
|
* needs to be worked around by using software forced clockdomain
|
|
|
|
* wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
|
|
|
|
* software force wakeup. The clockdomain is then put back to
|
|
|
|
* hardware supervised mode.
|
|
|
|
* More details can be found in OMAP4430 TRM - Version J
|
|
|
|
* Section :
|
|
|
|
* 4.3.4.2 Power States of CPU0 and CPU1
|
|
|
|
*/
|
2013-02-09 01:20:58 +08:00
|
|
|
if (booted && cpu1_pwrdm && cpu1_clkdm) {
|
ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
|
|
|
/*
|
|
|
|
* GIC distributor control register has changed between
|
|
|
|
* CortexA9 r1pX and r2pX. The Control Register secure
|
|
|
|
* banked version is now composed of 2 bits:
|
|
|
|
* bit 0 == Secure Enable
|
|
|
|
* bit 1 == Non-Secure Enable
|
|
|
|
* The Non-Secure banked register has not changed
|
|
|
|
* Because the ROM Code is based on the r1pX GIC, the CPU1
|
|
|
|
* GIC restoration will cause a problem to CPU0 Non-Secure SW.
|
|
|
|
* The workaround must be:
|
|
|
|
* 1) Before doing the CPU1 wakeup, CPU0 must disable
|
|
|
|
* the GIC distributor
|
|
|
|
* 2) CPU1 must re-enable the GIC distributor on
|
|
|
|
* it's wakeup path.
|
|
|
|
*/
|
2012-10-18 17:20:08 +08:00
|
|
|
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
|
|
|
|
local_irq_disable();
|
ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
|
|
|
gic_dist_disable();
|
2012-10-18 17:20:08 +08:00
|
|
|
}
|
ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
|
|
|
|
2013-02-09 01:20:58 +08:00
|
|
|
/*
|
|
|
|
* Ensure that CPU power state is set to ON to avoid CPU
|
|
|
|
* powerdomain transition on wfi
|
|
|
|
*/
|
2016-06-30 21:15:02 +08:00
|
|
|
clkdm_deny_idle_nolock(cpu1_clkdm);
|
ARM: OMAP4+: SMP: use lockless clkdm/pwrdm api in omap4_boot_secondary
OMAP CPU hotplug uses cpu1's clocks and power domains for CPU1 wake up
from low power states (or turn on CPU1). This part of code is also
part of system suspend (disable_nonboot_cpus()).
>From other side, cpu1's clocks and power domains are used by CPUIdle. All above
functionality is mutually exclusive and, therefore, lockless clkdm/pwrdm api
can be used in omap4_boot_secondary().
This fixes below back-trace on -RT which is triggered by
pwrdm_lock/unlock():
BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
in_atomic(): 1, irqs_disabled(): 0, pid: 118, name: sh
9 locks held by sh/118:
#0: (sb_writers#4){.+.+.+}, at: [<c0144a6c>] vfs_write+0x13c/0x164
#1: (&of->mutex){+.+.+.}, at: [<c01b4c70>] kernfs_fop_write+0x48/0x19c
#2: (s_active#24){.+.+.+}, at: [<c01b4c78>] kernfs_fop_write+0x50/0x19c
#3: (device_hotplug_lock){+.+.+.}, at: [<c03cbff0>] lock_device_hotplug_sysfs+0xc/0x4c
#4: (&dev->mutex){......}, at: [<c03cd284>] device_online+0x14/0x88
#5: (cpu_add_remove_lock){+.+.+.}, at: [<c003af90>] cpu_up+0x50/0x1a0
#6: (cpu_hotplug.lock){++++++}, at: [<c003ae48>] cpu_hotplug_begin+0x0/0xc4
#7: (cpu_hotplug.lock#2){+.+.+.}, at: [<c003aec0>] cpu_hotplug_begin+0x78/0xc4
#8: (boot_lock){+.+...}, at: [<c002b254>] omap4_boot_secondary+0x1c/0x178
Preemption disabled at:[< (null)>] (null)
CPU: 0 PID: 118 Comm: sh Not tainted 4.1.12-rt11-01998-gb4a62c3-dirty #137
Hardware name: Generic DRA74X (Flattened Device Tree)
[<c0017574>] (unwind_backtrace) from [<c0013be8>] (show_stack+0x10/0x14)
[<c0013be8>] (show_stack) from [<c05a8670>] (dump_stack+0x80/0x94)
[<c05a8670>] (dump_stack) from [<c05ad158>] (rt_spin_lock+0x24/0x54)
[<c05ad158>] (rt_spin_lock) from [<c0030dac>] (clkdm_wakeup+0x10/0x2c)
[<c0030dac>] (clkdm_wakeup) from [<c002b2c0>] (omap4_boot_secondary+0x88/0x178)
[<c002b2c0>] (omap4_boot_secondary) from [<c0015d00>] (__cpu_up+0xc4/0x164)
[<c0015d00>] (__cpu_up) from [<c003b09c>] (cpu_up+0x15c/0x1a0)
[<c003b09c>] (cpu_up) from [<c03cd2d4>] (device_online+0x64/0x88)
[<c03cd2d4>] (device_online) from [<c03cd360>] (online_store+0x68/0x74)
[<c03cd360>] (online_store) from [<c01b4ce0>] (kernfs_fop_write+0xb8/0x19c)
[<c01b4ce0>] (kernfs_fop_write) from [<c0144124>] (__vfs_write+0x20/0xd8)
[<c0144124>] (__vfs_write) from [<c01449c0>] (vfs_write+0x90/0x164)
[<c01449c0>] (vfs_write) from [<c01451e4>] (SyS_write+0x44/0x9c)
[<c01451e4>] (SyS_write) from [<c0010240>] (ret_fast_syscall+0x0/0x54)
CPU1: smp_ops.cpu_die() returned, trying to resuscitate
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-11-17 01:38:53 +08:00
|
|
|
pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
|
|
|
|
clkdm_allow_idle_nolock(cpu1_clkdm);
|
2012-10-18 17:20:08 +08:00
|
|
|
|
|
|
|
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
|
|
|
|
while (gic_dist_disabled()) {
|
|
|
|
udelay(1);
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
gic_timer_retrigger();
|
|
|
|
local_irq_enable();
|
|
|
|
}
|
2010-06-17 00:49:49 +08:00
|
|
|
} else {
|
|
|
|
dsb_sev();
|
|
|
|
booted = true;
|
|
|
|
}
|
|
|
|
|
2012-11-27 05:05:48 +08:00
|
|
|
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
2009-04-28 23:21:52 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Now the secondary core is starting up let it run its
|
|
|
|
* calibrations, then wait for it to finish
|
|
|
|
*/
|
|
|
|
spin_unlock(&boot_lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialise the CPU possible map early - this describes the CPUs
|
|
|
|
* which may be present or become present in the system.
|
|
|
|
*/
|
2011-09-08 20:15:22 +08:00
|
|
|
static void __init omap4_smp_init_cpus(void)
|
2009-04-28 23:21:52 +08:00
|
|
|
{
|
2012-03-19 21:59:41 +08:00
|
|
|
unsigned int i = 0, ncores = 1, cpu_id;
|
|
|
|
|
|
|
|
/* Use ARM cpuid check here, as SoC detection will not work so early */
|
2013-01-31 00:38:21 +08:00
|
|
|
cpu_id = read_cpuid_id() & CPU_MASK;
|
2012-03-19 21:59:41 +08:00
|
|
|
if (cpu_id == CPU_CORTEX_A9) {
|
|
|
|
/*
|
|
|
|
* Currently we can't call ioremap here because
|
|
|
|
* SoC detection won't work until after init_early.
|
|
|
|
*/
|
2016-06-22 16:59:40 +08:00
|
|
|
cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
|
|
|
|
BUG_ON(!cfg.scu_base);
|
|
|
|
ncores = scu_get_core_count(cfg.scu_base);
|
2012-03-19 21:59:41 +08:00
|
|
|
} else if (cpu_id == CPU_CORTEX_A15) {
|
|
|
|
ncores = OMAP5_CORE_COUNT;
|
|
|
|
}
|
2009-04-28 23:21:52 +08:00
|
|
|
|
|
|
|
/* sanity check */
|
2011-10-21 05:04:18 +08:00
|
|
|
if (ncores > nr_cpu_ids) {
|
|
|
|
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
|
|
|
|
ncores, nr_cpu_ids);
|
|
|
|
ncores = nr_cpu_ids;
|
2009-04-28 23:21:52 +08:00
|
|
|
}
|
|
|
|
|
2010-12-03 18:42:58 +08:00
|
|
|
for (i = 0; i < ncores; i++)
|
|
|
|
set_cpu_possible(i, true);
|
|
|
|
}
|
|
|
|
|
2017-03-23 02:01:48 +08:00
|
|
|
/*
|
|
|
|
* For now, just make sure the start-up address is not within the booting
|
|
|
|
* kernel space as that means we just overwrote whatever secondary_startup()
|
|
|
|
* code there was.
|
|
|
|
*/
|
|
|
|
static bool __init omap4_smp_cpu1_startup_valid(unsigned long addr)
|
|
|
|
{
|
|
|
|
if ((addr >= __pa(PAGE_OFFSET)) && (addr <= __pa(__bss_start)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We may need to reset CPU1 before configuring, otherwise kexec boot can end
|
|
|
|
* up trying to use old kernel startup address or suspend-resume will
|
|
|
|
* occasionally fail to bring up CPU1 on 4430 if CPU1 fails to enter deeper
|
|
|
|
* idle states.
|
|
|
|
*/
|
|
|
|
static void __init omap4_smp_maybe_reset_cpu1(struct omap_smp_config *c)
|
|
|
|
{
|
|
|
|
unsigned long cpu1_startup_pa, cpu1_ns_pa_addr;
|
|
|
|
bool needs_reset = false;
|
|
|
|
u32 released;
|
|
|
|
|
|
|
|
if (omap_secure_apis_support())
|
|
|
|
released = omap_read_auxcoreboot0() & AUX_CORE_BOOT0_HS_RELEASE;
|
|
|
|
else
|
|
|
|
released = readl_relaxed(cfg.wakeupgen_base +
|
|
|
|
OMAP_AUX_CORE_BOOT_0) &
|
|
|
|
AUX_CORE_BOOT0_GP_RELEASE;
|
|
|
|
if (released) {
|
|
|
|
pr_warn("smp: CPU1 not parked?\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu1_startup_pa = readl_relaxed(cfg.wakeupgen_base +
|
|
|
|
OMAP_AUX_CORE_BOOT_1);
|
|
|
|
cpu1_ns_pa_addr = omap4_get_cpu1_ns_pa_addr();
|
|
|
|
|
|
|
|
/* Did the configured secondary_startup() get overwritten? */
|
|
|
|
if (!omap4_smp_cpu1_startup_valid(cpu1_startup_pa))
|
|
|
|
needs_reset = true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If omap4 or 5 has NS_PA_ADDR configured, CPU1 may be in a
|
|
|
|
* deeper idle state in WFI and will wake to an invalid address.
|
|
|
|
*/
|
|
|
|
if ((soc_is_omap44xx() || soc_is_omap54xx()) &&
|
|
|
|
!omap4_smp_cpu1_startup_valid(cpu1_ns_pa_addr))
|
|
|
|
needs_reset = true;
|
|
|
|
|
|
|
|
if (!needs_reset || !c->cpu1_rstctrl_va)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pr_info("smp: CPU1 parked within kernel, needs reset (0x%lx 0x%lx)\n",
|
|
|
|
cpu1_startup_pa, cpu1_ns_pa_addr);
|
|
|
|
|
|
|
|
writel_relaxed(1, c->cpu1_rstctrl_va);
|
|
|
|
readl_relaxed(c->cpu1_rstctrl_va);
|
|
|
|
writel_relaxed(0, c->cpu1_rstctrl_va);
|
|
|
|
}
|
|
|
|
|
2011-09-08 20:15:22 +08:00
|
|
|
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
2010-12-03 18:42:58 +08:00
|
|
|
{
|
2016-06-22 16:59:40 +08:00
|
|
|
const struct omap_smp_config *c = NULL;
|
|
|
|
|
|
|
|
if (soc_is_omap443x())
|
|
|
|
c = &omap443x_cfg;
|
|
|
|
else if (soc_is_omap446x())
|
|
|
|
c = &omap446x_cfg;
|
|
|
|
else if (soc_is_dra74x() || soc_is_omap54xx())
|
|
|
|
c = &omap5_cfg;
|
|
|
|
|
|
|
|
if (!c) {
|
|
|
|
pr_err("%s Unknown SMP SoC?\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Must preserve cfg.scu_base set earlier */
|
|
|
|
cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;
|
|
|
|
cfg.startup_addr = c->startup_addr;
|
2017-03-23 02:01:48 +08:00
|
|
|
cfg.wakeupgen_base = omap_get_wakeupgen_base();
|
2016-06-22 16:59:40 +08:00
|
|
|
|
|
|
|
if (soc_is_dra74x() || soc_is_omap54xx()) {
|
|
|
|
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
|
|
|
|
cfg.startup_addr = omap5_secondary_hyp_startup;
|
|
|
|
omap5_erratum_workaround_801819();
|
|
|
|
}
|
|
|
|
|
|
|
|
cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4);
|
|
|
|
if (!cfg.cpu1_rstctrl_va)
|
|
|
|
return;
|
2009-04-28 23:21:52 +08:00
|
|
|
|
2010-12-03 19:09:48 +08:00
|
|
|
/*
|
|
|
|
* Initialise the SCU and wake up the secondary core using
|
|
|
|
* wakeup_secondary().
|
|
|
|
*/
|
2016-06-22 16:59:40 +08:00
|
|
|
if (cfg.scu_base)
|
|
|
|
scu_enable(cfg.scu_base);
|
2013-02-10 16:24:00 +08:00
|
|
|
|
2017-03-23 02:01:48 +08:00
|
|
|
omap4_smp_maybe_reset_cpu1(&cfg);
|
2013-02-10 16:24:00 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Write the address of secondary startup routine into the
|
|
|
|
* AuxCoreBoot1 where ROM code will jump and start executing
|
|
|
|
* on secondary core once out of WFE
|
|
|
|
* A barrier is added to ensure that write buffer is drained
|
|
|
|
*/
|
|
|
|
if (omap_secure_apis_support())
|
2017-01-15 10:59:29 +08:00
|
|
|
omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
|
2013-02-10 16:24:00 +08:00
|
|
|
else
|
2017-01-15 10:59:29 +08:00
|
|
|
writel_relaxed(__pa_symbol(cfg.startup_addr),
|
2017-03-23 02:01:48 +08:00
|
|
|
cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
|
2009-04-28 23:21:52 +08:00
|
|
|
}
|
2011-09-08 20:15:22 +08:00
|
|
|
|
2015-11-15 09:39:53 +08:00
|
|
|
const struct smp_operations omap4_smp_ops __initconst = {
|
2011-09-08 20:15:22 +08:00
|
|
|
.smp_init_cpus = omap4_smp_init_cpus,
|
|
|
|
.smp_prepare_cpus = omap4_smp_prepare_cpus,
|
|
|
|
.smp_secondary_init = omap4_secondary_init,
|
|
|
|
.smp_boot_secondary = omap4_boot_secondary,
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
.cpu_die = omap4_cpu_die,
|
2016-06-22 16:59:40 +08:00
|
|
|
.cpu_kill = omap4_cpu_kill,
|
2011-09-08 20:15:22 +08:00
|
|
|
#endif
|
|
|
|
};
|