2018-05-30 23:34:03 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Mobiveil PCIe Host controller
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*
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* Copyright (c) 2018 Mobiveil Inc.
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2020-02-13 12:06:32 +08:00
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* Copyright 2019-2020 NXP
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*
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2018-05-30 23:34:03 +08:00
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* Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
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2020-02-13 12:06:32 +08:00
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* Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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2018-05-30 23:34:03 +08:00
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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2018-05-30 23:34:10 +08:00
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#include <linux/msi.h>
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2018-05-30 23:34:03 +08:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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2020-02-13 12:06:35 +08:00
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#include "pcie-mobiveil.h"
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2018-05-30 23:34:03 +08:00
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static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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{
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/* Only one device down on each root port */
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2020-07-22 10:25:01 +08:00
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if (pci_is_root_bus(bus) && (devfn > 0))
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2018-05-30 23:34:03 +08:00
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return false;
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/*
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* Do not read more than one device on the bus directly
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* attached to RC
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*/
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2020-07-22 10:25:01 +08:00
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if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0))
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2018-05-30 23:34:03 +08:00
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return false;
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return true;
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}
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/*
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* mobiveil_pcie_map_bus - routine to get the configuration base of either
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* root port or endpoint
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*/
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static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
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2019-07-05 17:56:41 +08:00
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unsigned int devfn, int where)
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2018-05-30 23:34:03 +08:00
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{
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struct mobiveil_pcie *pcie = bus->sysdata;
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2020-02-13 12:06:32 +08:00
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struct mobiveil_root_port *rp = &pcie->rp;
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2019-07-05 17:56:42 +08:00
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u32 value;
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2018-05-30 23:34:03 +08:00
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if (!mobiveil_pcie_valid_device(bus, devfn))
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return NULL;
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2019-07-05 17:56:41 +08:00
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/* RC config access */
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2020-07-22 10:25:01 +08:00
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if (pci_is_root_bus(bus))
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2018-05-30 23:34:03 +08:00
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return pcie->csr_axi_slave_base + where;
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/*
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* EP config access (in Config/APIO space)
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* Program PEX Address base (31..16 bits) with appropriate value
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* (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
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* Relies on pci_lock serialization
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*/
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2019-07-05 17:56:42 +08:00
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value = bus->number << PAB_BUS_SHIFT |
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PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
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PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
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2019-07-05 17:56:42 +08:00
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2020-02-13 12:06:32 +08:00
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return rp->config_axi_slave_base + where;
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2018-05-30 23:34:03 +08:00
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}
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static struct pci_ops mobiveil_pcie_ops = {
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.map_bus = mobiveil_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static void mobiveil_pcie_isr(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
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struct device *dev = &pcie->pdev->dev;
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2020-02-13 12:06:32 +08:00
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struct mobiveil_root_port *rp = &pcie->rp;
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struct mobiveil_msi *msi = &rp->msi;
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2018-05-30 23:34:10 +08:00
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u32 msi_data, msi_addr_lo, msi_addr_hi;
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u32 intr_status, msi_status;
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2018-05-30 23:34:03 +08:00
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unsigned long shifted_status;
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2021-08-03 00:26:19 +08:00
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u32 bit, val, mask;
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2018-05-30 23:34:03 +08:00
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/*
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2018-05-30 23:34:10 +08:00
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* The core provides a single interrupt for both INTx/MSI messages.
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* So we'll read both INTx and MSI status
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2018-05-30 23:34:03 +08:00
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*/
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chained_irq_enter(chip, desc);
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/* read INTx status */
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2019-10-04 12:19:25 +08:00
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val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
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mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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2018-05-30 23:34:03 +08:00
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intr_status = val & mask;
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/* Handle INTx */
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if (intr_status & PAB_INTP_INTX_MASK) {
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2019-10-04 12:19:25 +08:00
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shifted_status = mobiveil_csr_readl(pcie,
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PAB_INTP_AMBA_MISC_STAT);
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2019-07-05 17:56:55 +08:00
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shifted_status &= PAB_INTP_INTX_MASK;
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shifted_status >>= PAB_INTX_START;
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2018-05-30 23:34:03 +08:00
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do {
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for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
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2021-08-03 00:26:19 +08:00
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int ret;
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ret = generic_handle_domain_irq(rp->intx_domain,
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bit + 1);
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if (ret)
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2019-07-05 17:56:41 +08:00
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dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
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bit);
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2018-05-30 23:34:03 +08:00
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2019-07-05 17:56:56 +08:00
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/* clear interrupt handled */
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie,
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1 << (PAB_INTX_START + bit),
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PAB_INTP_AMBA_MISC_STAT);
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2018-05-30 23:34:03 +08:00
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}
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2019-07-05 17:56:55 +08:00
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2019-10-04 12:19:25 +08:00
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shifted_status = mobiveil_csr_readl(pcie,
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PAB_INTP_AMBA_MISC_STAT);
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2019-07-05 17:56:55 +08:00
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shifted_status &= PAB_INTP_INTX_MASK;
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shifted_status >>= PAB_INTX_START;
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} while (shifted_status != 0);
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2018-05-30 23:34:03 +08:00
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}
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2018-05-30 23:34:10 +08:00
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/* read extra MSI status register */
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msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
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/* handle MSI interrupts */
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while (msi_status & 1) {
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2019-07-05 17:56:41 +08:00
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msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
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2018-05-30 23:34:10 +08:00
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/*
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* MSI_STATUS_OFFSET register gets updated to zero
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* once we pop not only the MSI data but also address
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* from MSI hardware FIFO. So keeping these following
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* two dummy reads.
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*/
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msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
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2019-07-05 17:56:41 +08:00
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MSI_ADDR_L_OFFSET);
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2018-05-30 23:34:10 +08:00
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msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
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2019-07-05 17:56:41 +08:00
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MSI_ADDR_H_OFFSET);
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2018-05-30 23:34:10 +08:00
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
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2019-07-05 17:56:41 +08:00
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msi_data, msi_addr_hi, msi_addr_lo);
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2018-05-30 23:34:10 +08:00
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2021-08-03 00:26:19 +08:00
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generic_handle_domain_irq(msi->dev_domain, msi_data);
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2018-05-30 23:34:10 +08:00
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msi_status = readl_relaxed(pcie->apb_csr_base +
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2019-07-05 17:56:41 +08:00
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MSI_STATUS_OFFSET);
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2018-05-30 23:34:10 +08:00
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}
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2018-05-30 23:34:03 +08:00
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/* Clear the interrupt status */
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
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2018-05-30 23:34:03 +08:00
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chained_irq_exit(chip, desc);
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}
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static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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struct platform_device *pdev = pcie->pdev;
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struct device_node *node = dev->of_node;
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2020-02-13 12:06:32 +08:00
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struct mobiveil_root_port *rp = &pcie->rp;
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2018-05-30 23:34:03 +08:00
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struct resource *res;
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/* map config resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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2019-07-05 17:56:41 +08:00
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"config_axi_slave");
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2020-02-13 12:06:32 +08:00
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rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(rp->config_axi_slave_base))
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return PTR_ERR(rp->config_axi_slave_base);
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rp->ob_io_res = res;
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2018-05-30 23:34:03 +08:00
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/* map csr resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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2019-07-05 17:56:41 +08:00
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"csr_axi_slave");
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2018-05-30 23:34:03 +08:00
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pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->csr_axi_slave_base))
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return PTR_ERR(pcie->csr_axi_slave_base);
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pcie->pcie_reg_base = res->start;
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/* read the number of windows requested */
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if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
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pcie->apio_wins = MAX_PIO_WINDOWS;
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if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
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pcie->ppio_wins = MAX_PIO_WINDOWS;
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return 0;
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}
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2018-05-30 23:34:10 +08:00
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static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
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{
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phys_addr_t msg_addr = pcie->pcie_reg_base;
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2020-02-13 12:06:32 +08:00
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struct mobiveil_msi *msi = &pcie->rp.msi;
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2018-05-30 23:34:10 +08:00
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2020-02-13 12:06:32 +08:00
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msi->num_of_vectors = PCI_NUM_MSI;
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2018-05-30 23:34:10 +08:00
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msi->msi_pages_phys = (phys_addr_t)msg_addr;
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writel_relaxed(lower_32_bits(msg_addr),
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2019-07-05 17:56:41 +08:00
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pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
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2018-05-30 23:34:10 +08:00
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writel_relaxed(upper_32_bits(msg_addr),
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2019-07-05 17:56:41 +08:00
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pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
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2018-05-30 23:34:10 +08:00
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writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
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writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
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}
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2020-02-13 12:06:38 +08:00
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int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
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2018-05-30 23:34:03 +08:00
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{
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2020-02-13 12:06:32 +08:00
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struct mobiveil_root_port *rp = &pcie->rp;
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struct pci_host_bridge *bridge = rp->bridge;
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2019-07-05 17:56:43 +08:00
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u32 value, pab_ctrl, type;
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2019-07-05 17:56:32 +08:00
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struct resource_entry *win;
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2018-05-30 23:34:03 +08:00
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2020-02-13 12:06:38 +08:00
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pcie->ib_wins_configured = 0;
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pcie->ob_wins_configured = 0;
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if (!reinit) {
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/* setup bus numbers */
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value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
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value &= 0xff000000;
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value |= 0x00ff0100;
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mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
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}
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2019-07-05 17:56:38 +08:00
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2018-05-30 23:34:03 +08:00
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/*
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* program Bus Master Enable Bit in Command Register in PAB Config
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* Space
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*/
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2019-10-04 12:19:25 +08:00
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value = mobiveil_csr_readl(pcie, PCI_COMMAND);
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2019-07-05 17:56:42 +08:00
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value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie, value, PCI_COMMAND);
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2018-05-30 23:34:03 +08:00
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/*
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* program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
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* register
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*/
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2019-10-04 12:19:25 +08:00
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pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
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2019-07-05 17:56:42 +08:00
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pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
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2018-05-30 23:34:03 +08:00
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/*
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* program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
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* PAB_AXI_PIO_CTRL Register
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*/
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2019-10-04 12:19:25 +08:00
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value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
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2019-07-05 17:56:42 +08:00
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value |= APIO_EN_MASK;
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
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2018-05-30 23:34:03 +08:00
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2019-07-05 17:56:54 +08:00
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/* Enable PCIe PIO master */
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2019-10-04 12:19:25 +08:00
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value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
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2019-07-05 17:56:54 +08:00
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value |= 1 << PIO_ENABLE_SHIFT;
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2019-10-04 12:19:25 +08:00
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mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
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2019-07-05 17:56:54 +08:00
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2018-05-30 23:34:03 +08:00
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/*
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* we'll program one outbound window for config reads and
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|
|
* another default inbound window for all the upstream traffic
|
|
|
|
* rest of the outbound windows will be configured according to
|
|
|
|
* the "ranges" field defined in device tree
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* config outbound translation window */
|
2020-02-13 12:06:32 +08:00
|
|
|
program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,
|
|
|
|
CFG_WINDOW_TYPE, resource_size(rp->ob_io_res));
|
2018-05-30 23:34:03 +08:00
|
|
|
|
|
|
|
/* memory inbound translation window */
|
2019-07-13 22:11:29 +08:00
|
|
|
program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
|
2018-05-30 23:34:03 +08:00
|
|
|
|
|
|
|
/* Get the I/O and memory ranges from DT */
|
2019-10-29 00:32:40 +08:00
|
|
|
resource_list_for_each_entry(win, &bridge->windows) {
|
2018-05-30 23:34:03 +08:00
|
|
|
if (resource_type(win->res) == IORESOURCE_MEM)
|
|
|
|
type = MEM_WINDOW_TYPE;
|
2019-07-05 17:56:43 +08:00
|
|
|
else if (resource_type(win->res) == IORESOURCE_IO)
|
2018-05-30 23:34:03 +08:00
|
|
|
type = IO_WINDOW_TYPE;
|
2019-07-05 17:56:43 +08:00
|
|
|
else
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* configure outbound translation window */
|
|
|
|
program_ob_windows(pcie, pcie->ob_wins_configured,
|
|
|
|
win->res->start,
|
|
|
|
win->res->start - win->offset,
|
|
|
|
type, resource_size(win->res));
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
2019-07-05 17:56:35 +08:00
|
|
|
/* fixup for PCIe class register */
|
2019-10-04 12:19:25 +08:00
|
|
|
value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
|
2019-07-05 17:56:35 +08:00
|
|
|
value &= 0xff;
|
2022-02-14 19:41:08 +08:00
|
|
|
value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
|
2019-10-04 12:19:25 +08:00
|
|
|
mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
|
2019-07-05 17:56:35 +08:00
|
|
|
|
2019-07-05 17:56:36 +08:00
|
|
|
return 0;
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mobiveil_mask_intx_irq(struct irq_data *data)
|
|
|
|
{
|
2020-12-11 03:25:55 +08:00
|
|
|
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
|
2020-02-13 12:06:32 +08:00
|
|
|
struct mobiveil_root_port *rp;
|
2018-05-30 23:34:03 +08:00
|
|
|
unsigned long flags;
|
|
|
|
u32 mask, shifted_val;
|
|
|
|
|
2020-02-13 12:06:32 +08:00
|
|
|
rp = &pcie->rp;
|
2018-05-30 23:34:03 +08:00
|
|
|
mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
|
2020-02-13 12:06:32 +08:00
|
|
|
raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);
|
2019-10-04 12:19:25 +08:00
|
|
|
shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
|
2019-07-05 17:56:42 +08:00
|
|
|
shifted_val &= ~mask;
|
2019-10-04 12:19:25 +08:00
|
|
|
mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
|
2020-02-13 12:06:32 +08:00
|
|
|
raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mobiveil_unmask_intx_irq(struct irq_data *data)
|
|
|
|
{
|
2020-12-11 03:25:55 +08:00
|
|
|
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
|
2020-02-13 12:06:32 +08:00
|
|
|
struct mobiveil_root_port *rp;
|
2018-05-30 23:34:03 +08:00
|
|
|
unsigned long flags;
|
|
|
|
u32 shifted_val, mask;
|
|
|
|
|
2020-02-13 12:06:32 +08:00
|
|
|
rp = &pcie->rp;
|
2018-05-30 23:34:03 +08:00
|
|
|
mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
|
2020-02-13 12:06:32 +08:00
|
|
|
raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);
|
2019-10-04 12:19:25 +08:00
|
|
|
shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
|
2019-07-05 17:56:42 +08:00
|
|
|
shifted_val |= mask;
|
2019-10-04 12:19:25 +08:00
|
|
|
mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
|
2020-02-13 12:06:32 +08:00
|
|
|
raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct irq_chip intx_irq_chip = {
|
|
|
|
.name = "mobiveil_pcie:intx",
|
|
|
|
.irq_enable = mobiveil_unmask_intx_irq,
|
|
|
|
.irq_disable = mobiveil_mask_intx_irq,
|
|
|
|
.irq_mask = mobiveil_mask_intx_irq,
|
|
|
|
.irq_unmask = mobiveil_unmask_intx_irq,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* routine to setup the INTx related data */
|
|
|
|
static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
2019-07-05 17:56:41 +08:00
|
|
|
irq_hw_number_t hwirq)
|
2018-05-30 23:34:03 +08:00
|
|
|
{
|
|
|
|
irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
|
|
|
|
irq_set_chip_data(irq, domain->host_data);
|
2019-07-05 17:56:41 +08:00
|
|
|
|
2018-05-30 23:34:03 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* INTx domain operations structure */
|
|
|
|
static const struct irq_domain_ops intx_domain_ops = {
|
|
|
|
.map = mobiveil_pcie_intx_map,
|
|
|
|
};
|
|
|
|
|
2018-05-30 23:34:10 +08:00
|
|
|
static struct irq_chip mobiveil_msi_irq_chip = {
|
|
|
|
.name = "Mobiveil PCIe MSI",
|
|
|
|
.irq_mask = pci_msi_mask_irq,
|
|
|
|
.irq_unmask = pci_msi_unmask_irq,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct msi_domain_info mobiveil_msi_domain_info = {
|
|
|
|
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
|
2019-07-05 17:56:30 +08:00
|
|
|
MSI_FLAG_PCI_MSIX),
|
2018-05-30 23:34:10 +08:00
|
|
|
.chip = &mobiveil_msi_irq_chip,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
|
|
|
{
|
|
|
|
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
|
|
|
|
phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
|
|
|
|
|
|
|
|
msg->address_lo = lower_32_bits(addr);
|
|
|
|
msg->address_hi = upper_32_bits(addr);
|
|
|
|
msg->data = data->hwirq;
|
|
|
|
|
|
|
|
dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
|
|
|
|
(int)data->hwirq, msg->address_hi, msg->address_lo);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
|
2019-07-05 17:56:41 +08:00
|
|
|
const struct cpumask *mask, bool force)
|
2018-05-30 23:34:10 +08:00
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct irq_chip mobiveil_msi_bottom_irq_chip = {
|
|
|
|
.name = "Mobiveil MSI",
|
|
|
|
.irq_compose_msi_msg = mobiveil_compose_msi_msg,
|
|
|
|
.irq_set_affinity = mobiveil_msi_set_affinity,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
|
2019-07-05 17:56:41 +08:00
|
|
|
unsigned int virq,
|
|
|
|
unsigned int nr_irqs, void *args)
|
2018-05-30 23:34:10 +08:00
|
|
|
{
|
|
|
|
struct mobiveil_pcie *pcie = domain->host_data;
|
2020-02-13 12:06:32 +08:00
|
|
|
struct mobiveil_msi *msi = &pcie->rp.msi;
|
2018-05-30 23:34:10 +08:00
|
|
|
unsigned long bit;
|
|
|
|
|
|
|
|
WARN_ON(nr_irqs != 1);
|
|
|
|
mutex_lock(&msi->lock);
|
|
|
|
|
|
|
|
bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
|
|
|
|
if (bit >= msi->num_of_vectors) {
|
|
|
|
mutex_unlock(&msi->lock);
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
set_bit(bit, msi->msi_irq_in_use);
|
|
|
|
|
|
|
|
mutex_unlock(&msi->lock);
|
|
|
|
|
|
|
|
irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
|
2019-07-05 17:56:41 +08:00
|
|
|
domain->host_data, handle_level_irq, NULL, NULL);
|
2018-05-30 23:34:10 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
|
2019-07-05 17:56:41 +08:00
|
|
|
unsigned int virq,
|
|
|
|
unsigned int nr_irqs)
|
2018-05-30 23:34:10 +08:00
|
|
|
{
|
|
|
|
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
|
|
|
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
|
2020-02-13 12:06:32 +08:00
|
|
|
struct mobiveil_msi *msi = &pcie->rp.msi;
|
2018-05-30 23:34:10 +08:00
|
|
|
|
|
|
|
mutex_lock(&msi->lock);
|
|
|
|
|
2019-07-05 17:56:41 +08:00
|
|
|
if (!test_bit(d->hwirq, msi->msi_irq_in_use))
|
2018-05-30 23:34:10 +08:00
|
|
|
dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
|
|
|
|
d->hwirq);
|
2019-07-05 17:56:41 +08:00
|
|
|
else
|
2018-05-30 23:34:10 +08:00
|
|
|
__clear_bit(d->hwirq, msi->msi_irq_in_use);
|
|
|
|
|
|
|
|
mutex_unlock(&msi->lock);
|
|
|
|
}
|
|
|
|
static const struct irq_domain_ops msi_domain_ops = {
|
|
|
|
.alloc = mobiveil_irq_msi_domain_alloc,
|
|
|
|
.free = mobiveil_irq_msi_domain_free,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
|
2020-02-13 12:06:32 +08:00
|
|
|
struct mobiveil_msi *msi = &pcie->rp.msi;
|
2018-05-30 23:34:10 +08:00
|
|
|
|
2020-02-13 12:06:32 +08:00
|
|
|
mutex_init(&msi->lock);
|
2018-05-30 23:34:10 +08:00
|
|
|
msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
|
|
|
|
&msi_domain_ops, pcie);
|
|
|
|
if (!msi->dev_domain) {
|
|
|
|
dev_err(dev, "failed to create IRQ domain\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
msi->msi_domain = pci_msi_create_irq_domain(fwnode,
|
2019-07-05 17:56:41 +08:00
|
|
|
&mobiveil_msi_domain_info,
|
|
|
|
msi->dev_domain);
|
2018-05-30 23:34:10 +08:00
|
|
|
if (!msi->msi_domain) {
|
|
|
|
dev_err(dev, "failed to create MSI domain\n");
|
|
|
|
irq_domain_remove(msi->dev_domain);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2019-07-05 17:56:41 +08:00
|
|
|
|
2018-05-30 23:34:10 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-05-30 23:34:03 +08:00
|
|
|
static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
struct device_node *node = dev->of_node;
|
2020-02-13 12:06:32 +08:00
|
|
|
struct mobiveil_root_port *rp = &pcie->rp;
|
2018-05-30 23:34:03 +08:00
|
|
|
|
|
|
|
/* setup INTx */
|
2020-02-13 12:06:32 +08:00
|
|
|
rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
|
|
|
|
&intx_domain_ops, pcie);
|
2018-05-30 23:34:03 +08:00
|
|
|
|
2020-02-13 12:06:32 +08:00
|
|
|
if (!rp->intx_domain) {
|
2018-05-30 23:34:03 +08:00
|
|
|
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
2019-07-05 17:56:44 +08:00
|
|
|
return -ENOMEM;
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:32 +08:00
|
|
|
raw_spin_lock_init(&rp->intx_mask_lock);
|
2018-05-30 23:34:03 +08:00
|
|
|
|
2018-05-30 23:34:10 +08:00
|
|
|
/* setup MSI */
|
2020-09-21 16:24:47 +08:00
|
|
|
return mobiveil_allocate_msi_domains(pcie);
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:36 +08:00
|
|
|
static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie)
|
2020-02-13 12:06:34 +08:00
|
|
|
{
|
|
|
|
struct platform_device *pdev = pcie->pdev;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct mobiveil_root_port *rp = &pcie->rp;
|
|
|
|
struct resource *res;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* map MSI config resource */
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
|
|
|
|
pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
|
|
|
|
if (IS_ERR(pcie->apb_csr_base))
|
|
|
|
return PTR_ERR(pcie->apb_csr_base);
|
|
|
|
|
|
|
|
/* setup MSI hardware registers */
|
|
|
|
mobiveil_pcie_enable_msi(pcie);
|
|
|
|
|
|
|
|
rp->irq = platform_get_irq(pdev, 0);
|
2020-08-02 22:25:53 +08:00
|
|
|
if (rp->irq < 0)
|
2020-03-12 03:19:02 +08:00
|
|
|
return rp->irq;
|
2020-02-13 12:06:34 +08:00
|
|
|
|
|
|
|
/* initialize the IRQ domains */
|
|
|
|
ret = mobiveil_pcie_init_irq_domain(pcie);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed creating IRQ Domain\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);
|
|
|
|
|
|
|
|
/* Enable interrupts */
|
|
|
|
mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
|
|
|
|
PAB_INTP_AMBA_MISC_ENB);
|
|
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:36 +08:00
|
|
|
static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct mobiveil_root_port *rp = &pcie->rp;
|
|
|
|
|
|
|
|
if (rp->ops->interrupt_init)
|
|
|
|
return rp->ops->interrupt_init(pcie);
|
|
|
|
|
|
|
|
return mobiveil_pcie_integrated_interrupt_init(pcie);
|
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:40 +08:00
|
|
|
static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie)
|
|
|
|
{
|
|
|
|
u32 header_type;
|
|
|
|
|
|
|
|
header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE);
|
|
|
|
header_type &= 0x7f;
|
|
|
|
|
|
|
|
return header_type == PCI_HEADER_TYPE_BRIDGE;
|
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:35 +08:00
|
|
|
int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
|
2018-05-30 23:34:03 +08:00
|
|
|
{
|
2020-02-13 12:06:33 +08:00
|
|
|
struct mobiveil_root_port *rp = &pcie->rp;
|
|
|
|
struct pci_host_bridge *bridge = rp->bridge;
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
2018-05-30 23:34:03 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mobiveil_pcie_parse_dt(pcie);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:40 +08:00
|
|
|
if (!mobiveil_pcie_is_bridge(pcie))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2018-05-30 23:34:03 +08:00
|
|
|
/*
|
|
|
|
* configure all inbound and outbound windows and prepare the RC for
|
|
|
|
* config access
|
|
|
|
*/
|
2020-02-13 12:06:38 +08:00
|
|
|
ret = mobiveil_host_init(pcie, false);
|
2018-05-30 23:34:03 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to initialize host\n");
|
2019-10-29 00:32:40 +08:00
|
|
|
return ret;
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
2020-02-13 12:06:34 +08:00
|
|
|
ret = mobiveil_pcie_interrupt_init(pcie);
|
2018-05-30 23:34:03 +08:00
|
|
|
if (ret) {
|
2020-02-13 12:06:34 +08:00
|
|
|
dev_err(dev, "Interrupt init failed\n");
|
2019-10-29 00:32:40 +08:00
|
|
|
return ret;
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize bridge */
|
|
|
|
bridge->sysdata = pcie;
|
|
|
|
bridge->ops = &mobiveil_pcie_ops;
|
|
|
|
|
2019-07-05 17:56:36 +08:00
|
|
|
ret = mobiveil_bringup_link(pcie);
|
|
|
|
if (ret) {
|
|
|
|
dev_info(dev, "link bring-up failed\n");
|
2019-10-29 00:32:40 +08:00
|
|
|
return ret;
|
2019-07-05 17:56:36 +08:00
|
|
|
}
|
|
|
|
|
2020-05-23 07:48:22 +08:00
|
|
|
return pci_host_probe(bridge);
|
2018-05-30 23:34:03 +08:00
|
|
|
}
|