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OpenCloudOS-Kernel/drivers/clk/meson/gxbb.h

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clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright (c) 2016 AmLogic, Inc.
* Author: Michael Turquette <mturquette@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
* The full GNU General Public License is included in this distribution
* in the file called COPYING
*
* BSD LICENSE
*
* Copyright (c) 2016 BayLibre, Inc.
* Author: Michael Turquette <mturquette@baylibre.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __GXBB_H
#define __GXBB_H
/*
* Clock controller register offsets
*
* Register offsets from the data sheet are listed in comment blocks below.
* Those offsets must be multiplied by 4 before adding them to the base address
* to get the right value
*/
#define SCR 0x2C /* 0x0b offset in data sheet */
#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
clk: meson-gxbb: Add GXL/GXM GP0 Variant The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM SoCs embeds a different GP0 PLL, and needs different parameters with a vendor provided reduced rate table. This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order to use the GXL GP0 PLL instead of the GXBB specific one. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com
2017-03-22 18:32:25 +08:00
#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */
#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */
#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */
#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */
#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
/*
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
* Migrate them out of this header and into the DT header file when they need
* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
*/
#define CLKID_SYS_PLL 0
clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver It seems that the "cpu_clk" was carried over from the meson8b clock controller driver. On Meson GX (GXBB/GXL/GXM) the registers which are used by the cpu_clk have a different purpose (in other words: they don't control the CPU clock anymore). HHI_SYS_CPU_CLK_CNTL1 bits 31:24 are reserved according to the public S905 datasheet, while bit 23 is the "A53_trace_clk_DIS" gate (which according to the datasheet should only be used in case a silicon bug is discovered) and bits 22:20 are a divider (A53_trace_clk). The meson clk-cpu code however expects that bits 28:20 are reserved for a divider (according to the public S805 datasheet this "SCALE_DIV: This value represents an N+1 divider of the input clock."). The CPU clock on Meson GX SoCs is provided by the SCPI DVFS clock driver instead. Two examples from a Meson GXL S905X SoC: - vcpu (SCPI DVFS clock 0) rate: 1000000000 / cpu_clk rate: 708000000 - vcpu (SCPI DVFS clock 0) rate: 1512000000 / cpu_clk rate: 708000000 Unfortunately the CLKID_CPUCLK was already exported (but is currently not used) to DT. Due to the removal of this clock definition there is now a hole in the clk_hw_onecell_data (which is not a problem because this case is already handled in gxbb_clkc_probe). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-05 02:19:20 +08:00
/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
clk: meson-gxbb: Export PWM related clocks for DT Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com
2016-08-22 20:49:37 +08:00
/* CLKID_HDMI_PLL */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_FIXED_PLL 3
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-03 05:40:11 +08:00
/* CLKID_FCLK_DIV2 */
clk: meson-gxbb: Export PWM related clocks for DT Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com
2016-08-22 20:49:37 +08:00
/* CLKID_FCLK_DIV3 */
/* CLKID_FCLK_DIV4 */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_FCLK_DIV5 7
#define CLKID_FCLK_DIV7 8
clk: meson-gxbb: Expose GP0 dt-bindings clock id This patch exposes the GP0 PLL clock id in the dt bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-5-git-send-email-narmstrong@baylibre.com
2017-03-22 18:32:26 +08:00
/* CLKID_GP0_PLL */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_MPEG_SEL 10
#define CLKID_MPEG_DIV 11
/* CLKID_CLK81 */
#define CLKID_MPLL0 13
#define CLKID_MPLL1 14
clk: gxbb: expose MPLL2 clock for use by DT This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-07 05:38:44 +08:00
/* CLKID_MPLL2 */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_DDR 16
#define CLKID_DOS 17
#define CLKID_ISA 18
#define CLKID_PL301 19
#define CLKID_PERIPHS 20
clk: meson-gxbb: expose SPICC gate Expose the SPICC gate clock to enable the SPICC controller. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy commit message to match similar changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-20 19:59:10 +08:00
/* CLKID_SPICC */
clk: gxbb: expose i2c clocks I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14 18:06:05 +08:00
/* CLKID_I2C */
clk: gxbb: add the SAR ADC clocks and expose them The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-19 22:58:20 +08:00
/* #define CLKID_SAR_ADC */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_SMART_CARD 24
clk: meson-gxbb: expose clock CLKID_RNG0 Expose clock CLKID_RNG0 which is needed for the HW random number generator. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-02-22 14:55:24 +08:00
/* CLKID_RNG0 */
clk: meson-gxbb: expose UART clocks Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy the commit message to match similar change] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-01 00:54:34 +08:00
/* CLKID_UART0 */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_SDHC 27
#define CLKID_STREAM 28
#define CLKID_ASYNC_FIFO 29
#define CLKID_SDIO 30
#define CLKID_ABUF 31
#define CLKID_HIU_IFACE 32
#define CLKID_ASSIST_MISC 33
clk: gxbb: expose spifc clock SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-07 23:13:39 +08:00
/* CLKID_SPI */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_I2S_SPDIF 35
clk: gxbb: fix CLKID_ETH defined twice CLKID_ETH is define in the dt-bindings but has not be commented out in the clock driver. Just do it now. Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-27 00:05:49 +08:00
/* CLKID_ETH */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_DEMUX 37
dt-bindings: clk: gxbb: expose i2s output clock gates Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-09 18:41:54 +08:00
/* CLKID_AIU_GLUE */
clk: meson-gxbb: expose spdif clock gates Expose the clock gates required for the spdif output Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-03-02 22:22:29 +08:00
/* CLKID_IEC958 */
dt-bindings: clk: gxbb: expose i2s output clock gates Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-09 18:41:54 +08:00
/* CLKID_I2S_OUT */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_AMCLK 41
#define CLKID_AIFIFO2 42
#define CLKID_MIXER 43
dt-bindings: clk: gxbb: expose i2s output clock gates Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-09 18:41:54 +08:00
/* CLKID_MIXER_IFACE */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_ADC 45
#define CLKID_BLKMV 46
dt-bindings: clk: gxbb: expose i2s output clock gates Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-09 18:41:54 +08:00
/* CLKID_AIU */
clk: meson-gxbb: expose UART clocks Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy the commit message to match similar change] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-01 00:54:34 +08:00
/* CLKID_UART1 */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_G2D 49
clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-05 05:31:46 +08:00
/* CLKID_USB0 */
/* CLKID_USB1 */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_RESET 52
#define CLKID_NAND 53
#define CLKID_DOS_PARSER 54
clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-05 05:31:46 +08:00
/* CLKID_USB */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_VDIN1 56
#define CLKID_AHB_ARB0 57
#define CLKID_EFUSE 58
#define CLKID_BOOT_ROM 59
#define CLKID_AHB_DATA_BUS 60
#define CLKID_AHB_CTRL_BUS 61
#define CLKID_HDMI_INTR_SYNC 62
clk: meson-gxbb: Export HDMI clocks Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-17 20:08:48 +08:00
/* CLKID_HDMI_PCLK */
clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-05 05:31:46 +08:00
/* CLKID_USB1_DDR_BRIDGE */
/* CLKID_USB0_DDR_BRIDGE */
Revert "clk: gxbb: expose CLKID_MMC_PCLK" This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-07-16 10:13:36 +08:00
#define CLKID_MMC_PCLK 66
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_DVIN 67
clk: meson-gxbb: expose UART clocks Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy the commit message to match similar change] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-04-01 00:54:34 +08:00
/* CLKID_UART2 */
clk: gxbb: add the SAR ADC clocks and expose them The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-19 22:58:20 +08:00
/* #define CLKID_SANA */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
#define CLKID_VCLK2_VENCI0 73
#define CLKID_VCLK2_VENCI1 74
#define CLKID_VCLK2_VENCP0 75
#define CLKID_VCLK2_VENCP1 76
clk: meson-gxbb: Export HDMI clocks Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-17 20:08:48 +08:00
/* CLKID_GCLK_VENCI_INT0 */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_GCLK_VENCI_INT 78
#define CLKID_DAC_CLK 79
dt-bindings: clk: gxbb: expose i2s output clock gates Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-09 18:41:54 +08:00
/* CLKID_AOCLK_GATE */
clk: meson-gxbb: expose spdif clock gates Expose the clock gates required for the spdif output Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-03-02 22:22:29 +08:00
/* CLKID_IEC958_GATE */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
#define CLKID_ENC480P 82
#define CLKID_RNG1 83
#define CLKID_GCLK_VENCI_INT1 84
#define CLKID_VCLK2_VENCLMCC 85
#define CLKID_VCLK2_VENCL 86
#define CLKID_VCLK_OTHER 87
#define CLKID_EDP 88
#define CLKID_AO_MEDIA_CPU 89
#define CLKID_AO_AHB_SRAM 90
#define CLKID_AO_AHB_BUS 91
#define CLKID_AO_IFACE 92
clk: gxbb: expose i2c clocks I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14 18:06:05 +08:00
/* CLKID_AO_I2C */
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-03 05:40:11 +08:00
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
clk: gxbb: add the SAR ADC clocks and expose them The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-19 22:58:20 +08:00
/* CLKID_SAR_ADC_CLK */
/* CLKID_SAR_ADC_SEL */
#define CLKID_SAR_ADC_DIV 99
clk: meson-gxbb: Add MALI clock IDS Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-2-git-send-email-narmstrong@baylibre.com
2017-03-22 18:18:53 +08:00
/* CLKID_MALI_0_SEL */
#define CLKID_MALI_0_DIV 101
/* CLKID_MALI_0 */
/* CLKID_MALI_1_SEL */
#define CLKID_MALI_1_DIV 104
/* CLKID_MALI_1 */
/* CLKID_MALI */
clk: meson-gxbb: expose i2s master clock Expose cts_amclk in the device tree bindings Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-01-26 18:12:52 +08:00
/* CLKID_CTS_AMCLK */
clk: meson: gxbb: add cts_amclk Add the i2s master clock also referred as cts_amclk Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-01-25 01:35:23 +08:00
#define CLKID_CTS_AMCLK_SEL 108
#define CLKID_CTS_AMCLK_DIV 109
clk: meson-gxbb: expose spdif master clock Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-03-02 22:23:38 +08:00
/* CLKID_CTS_MCLK_I958 */
clk: meson: gxbb: add cts_mclk_i958 Add the spdif master clock also referred as cts_mclk_i958 Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-02-21 01:02:34 +08:00
#define CLKID_CTS_MCLK_I958_SEL 111
#define CLKID_CTS_MCLK_I958_DIV 112
clk: meson-gxbb: expose spdif master clock Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-03-02 22:23:38 +08:00
/* CLKID_CTS_I958 */
clk: meson-gxbb: Add EE 32K Clock for CEC On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-24 17:43:45 +08:00
#define CLKID_32K_CLK 114
#define CLKID_32K_CLK_SEL 115
#define CLKID_32K_CLK_DIV 116
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
clk: meson-gxbb: Add EE 32K Clock for CEC On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-24 17:43:45 +08:00
#define NR_CLKS 117
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-05-24 06:44:26 +08:00
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
#endif /* __GXBB_H */