License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2011-07-27 07:09:08 +08:00
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/* Atomic operations usable in machine independent code */
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2010-11-12 06:05:08 +08:00
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#ifndef _LINUX_ATOMIC_H
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#define _LINUX_ATOMIC_H
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#include <asm/atomic.h>
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locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
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#include <asm/barrier.h>
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/*
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* Relaxed variants of xchg, cmpxchg and some atomic operations.
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*
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* We support four variants:
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*
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* - Fully ordered: The default implementation, no suffix required.
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* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
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* - Release: Provides RELEASE semantics, _release suffix.
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* - Relaxed: No ordering guarantees, _relaxed suffix.
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*
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* For compound atomics performing both a load and a store, ACQUIRE
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* semantics apply only to the load and RELEASE semantics only to the
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* store portion of the operation. Note that a failed cmpxchg_acquire
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* does -not- imply any memory ordering constraints.
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*
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* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
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*/
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#ifndef atomic_read_acquire
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#define atomic_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic_set_release
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#define atomic_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/*
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* The idea here is to build acquire/release variants by adding explicit
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* barriers on top of the relaxed variant. In the case where the relaxed
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* variant is already fully ordered, no additional barriers are needed.
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2015-12-15 22:24:14 +08:00
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*
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* Besides, if an arch has a special barrier for acquire/release, it could
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* implement its own __atomic_op_* and use the same framework for building
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* variants
|
locking: Introduce smp_mb__after_spinlock()
Since its inception, our understanding of ACQUIRE, esp. as applied to
spinlocks, has changed somewhat. Also, I wonder if, with a simple
change, we cannot make it provide more.
The problem with the comment is that the STORE done by spin_lock isn't
itself ordered by the ACQUIRE, and therefore a later LOAD can pass over
it and cross with any prior STORE, rendering the default WMB
insufficient (pointed out by Alan).
Now, this is only really a problem on PowerPC and ARM64, both of
which already defined smp_mb__before_spinlock() as a smp_mb().
At the same time, we can get a much stronger construct if we place
that same barrier _inside_ the spin_lock(). In that case we upgrade
the RCpc spinlock to an RCsc. That would make all schedule() calls
fully transitive against one another.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-09-05 17:37:53 +08:00
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*
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* If an architecture overrides __atomic_op_acquire() it will probably want
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* to define smp_mb__after_spinlock().
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
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*/
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2015-12-15 22:24:14 +08:00
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#ifndef __atomic_op_acquire
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locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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2015-12-15 22:24:14 +08:00
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#endif
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locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
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2015-12-15 22:24:14 +08:00
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#ifndef __atomic_op_release
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locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
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#define __atomic_op_release(op, args...) \
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({ \
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smp_mb__before_atomic(); \
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op##_relaxed(args); \
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})
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2015-12-15 22:24:14 +08:00
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#endif
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
|
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|
2015-12-15 22:24:14 +08:00
|
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|
#ifndef __atomic_op_fence
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
|
|
|
#define __atomic_op_fence(op, args...) \
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({ \
|
|
|
|
|
typeof(op##_relaxed(args)) __ret; \
|
|
|
|
|
smp_mb__before_atomic(); \
|
|
|
|
|
__ret = op##_relaxed(args); \
|
|
|
|
|
smp_mb__after_atomic(); \
|
|
|
|
|
__ret; \
|
|
|
|
|
})
|
2015-12-15 22:24:14 +08:00
|
|
|
#endif
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
|
|
|
|
|
|
|
|
/* atomic_add_return_relaxed */
|
|
|
|
|
#ifndef atomic_add_return_relaxed
|
|
|
|
|
#define atomic_add_return_relaxed atomic_add_return
|
|
|
|
|
#define atomic_add_return_acquire atomic_add_return
|
|
|
|
|
#define atomic_add_return_release atomic_add_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic_add_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_add_return_acquire
|
|
|
|
|
#define atomic_add_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_add_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_add_return_release
|
|
|
|
|
#define atomic_add_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_add_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_add_return
|
|
|
|
|
#define atomic_add_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic_add_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_add_return_relaxed */
|
|
|
|
|
|
2015-10-01 04:03:11 +08:00
|
|
|
/* atomic_inc_return_relaxed */
|
|
|
|
|
#ifndef atomic_inc_return_relaxed
|
|
|
|
|
#define atomic_inc_return_relaxed atomic_inc_return
|
|
|
|
|
#define atomic_inc_return_acquire atomic_inc_return
|
|
|
|
|
#define atomic_inc_return_release atomic_inc_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic_inc_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_inc_return_acquire
|
|
|
|
|
#define atomic_inc_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_inc_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_inc_return_release
|
|
|
|
|
#define atomic_inc_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_inc_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_inc_return
|
|
|
|
|
#define atomic_inc_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic_inc_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_inc_return_relaxed */
|
|
|
|
|
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
|
|
|
/* atomic_sub_return_relaxed */
|
|
|
|
|
#ifndef atomic_sub_return_relaxed
|
|
|
|
|
#define atomic_sub_return_relaxed atomic_sub_return
|
|
|
|
|
#define atomic_sub_return_acquire atomic_sub_return
|
|
|
|
|
#define atomic_sub_return_release atomic_sub_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic_sub_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_sub_return_acquire
|
|
|
|
|
#define atomic_sub_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_sub_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_sub_return_release
|
|
|
|
|
#define atomic_sub_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_sub_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_sub_return
|
|
|
|
|
#define atomic_sub_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic_sub_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_sub_return_relaxed */
|
|
|
|
|
|
2015-10-01 04:03:11 +08:00
|
|
|
/* atomic_dec_return_relaxed */
|
|
|
|
|
#ifndef atomic_dec_return_relaxed
|
|
|
|
|
#define atomic_dec_return_relaxed atomic_dec_return
|
|
|
|
|
#define atomic_dec_return_acquire atomic_dec_return
|
|
|
|
|
#define atomic_dec_return_release atomic_dec_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic_dec_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_dec_return_acquire
|
|
|
|
|
#define atomic_dec_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_dec_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_dec_return_release
|
|
|
|
|
#define atomic_dec_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_dec_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_dec_return
|
|
|
|
|
#define atomic_dec_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic_dec_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_dec_return_relaxed */
|
|
|
|
|
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
|
|
|
|
|
/* atomic_fetch_add_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_add_relaxed
|
|
|
|
|
#define atomic_fetch_add_relaxed atomic_fetch_add
|
|
|
|
|
#define atomic_fetch_add_acquire atomic_fetch_add
|
|
|
|
|
#define atomic_fetch_add_release atomic_fetch_add
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_add_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_add_acquire
|
|
|
|
|
#define atomic_fetch_add_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_add, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_add_release
|
|
|
|
|
#define atomic_fetch_add_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_add, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_add
|
|
|
|
|
#define atomic_fetch_add(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_add, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_add_relaxed */
|
|
|
|
|
|
2016-06-29 05:56:51 +08:00
|
|
|
/* atomic_fetch_inc_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_inc_relaxed
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_inc
|
|
|
|
|
#define atomic_fetch_inc(v) atomic_fetch_add(1, (v))
|
|
|
|
|
#define atomic_fetch_inc_relaxed(v) atomic_fetch_add_relaxed(1, (v))
|
|
|
|
|
#define atomic_fetch_inc_acquire(v) atomic_fetch_add_acquire(1, (v))
|
|
|
|
|
#define atomic_fetch_inc_release(v) atomic_fetch_add_release(1, (v))
|
|
|
|
|
#else /* atomic_fetch_inc */
|
|
|
|
|
#define atomic_fetch_inc_relaxed atomic_fetch_inc
|
|
|
|
|
#define atomic_fetch_inc_acquire atomic_fetch_inc
|
|
|
|
|
#define atomic_fetch_inc_release atomic_fetch_inc
|
|
|
|
|
#endif /* atomic_fetch_inc */
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_inc_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_inc_acquire
|
|
|
|
|
#define atomic_fetch_inc_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_inc, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_inc_release
|
|
|
|
|
#define atomic_fetch_inc_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_inc, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_inc
|
|
|
|
|
#define atomic_fetch_inc(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_inc, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_inc_relaxed */
|
|
|
|
|
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
/* atomic_fetch_sub_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_sub_relaxed
|
|
|
|
|
#define atomic_fetch_sub_relaxed atomic_fetch_sub
|
|
|
|
|
#define atomic_fetch_sub_acquire atomic_fetch_sub
|
|
|
|
|
#define atomic_fetch_sub_release atomic_fetch_sub
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_sub_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_sub_acquire
|
|
|
|
|
#define atomic_fetch_sub_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_sub, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_sub_release
|
|
|
|
|
#define atomic_fetch_sub_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_sub, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_sub
|
|
|
|
|
#define atomic_fetch_sub(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_sub, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_sub_relaxed */
|
|
|
|
|
|
2016-06-29 05:56:51 +08:00
|
|
|
/* atomic_fetch_dec_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_dec_relaxed
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_dec
|
|
|
|
|
#define atomic_fetch_dec(v) atomic_fetch_sub(1, (v))
|
|
|
|
|
#define atomic_fetch_dec_relaxed(v) atomic_fetch_sub_relaxed(1, (v))
|
|
|
|
|
#define atomic_fetch_dec_acquire(v) atomic_fetch_sub_acquire(1, (v))
|
|
|
|
|
#define atomic_fetch_dec_release(v) atomic_fetch_sub_release(1, (v))
|
|
|
|
|
#else /* atomic_fetch_dec */
|
|
|
|
|
#define atomic_fetch_dec_relaxed atomic_fetch_dec
|
|
|
|
|
#define atomic_fetch_dec_acquire atomic_fetch_dec
|
|
|
|
|
#define atomic_fetch_dec_release atomic_fetch_dec
|
|
|
|
|
#endif /* atomic_fetch_dec */
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_dec_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_dec_acquire
|
|
|
|
|
#define atomic_fetch_dec_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_dec, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_dec_release
|
|
|
|
|
#define atomic_fetch_dec_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_dec, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_dec
|
|
|
|
|
#define atomic_fetch_dec(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_dec, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_dec_relaxed */
|
|
|
|
|
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
/* atomic_fetch_or_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_or_relaxed
|
|
|
|
|
#define atomic_fetch_or_relaxed atomic_fetch_or
|
|
|
|
|
#define atomic_fetch_or_acquire atomic_fetch_or
|
|
|
|
|
#define atomic_fetch_or_release atomic_fetch_or
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_or_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_or_acquire
|
|
|
|
|
#define atomic_fetch_or_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_or, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_or_release
|
|
|
|
|
#define atomic_fetch_or_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_or, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_or
|
|
|
|
|
#define atomic_fetch_or(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_or, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_or_relaxed */
|
|
|
|
|
|
|
|
|
|
/* atomic_fetch_and_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_and_relaxed
|
|
|
|
|
#define atomic_fetch_and_relaxed atomic_fetch_and
|
|
|
|
|
#define atomic_fetch_and_acquire atomic_fetch_and
|
|
|
|
|
#define atomic_fetch_and_release atomic_fetch_and
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_and_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_and_acquire
|
|
|
|
|
#define atomic_fetch_and_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_and, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_and_release
|
|
|
|
|
#define atomic_fetch_and_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_and, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_and
|
|
|
|
|
#define atomic_fetch_and(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_and, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_and_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifdef atomic_andnot
|
|
|
|
|
/* atomic_fetch_andnot_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_andnot_relaxed
|
|
|
|
|
#define atomic_fetch_andnot_relaxed atomic_fetch_andnot
|
|
|
|
|
#define atomic_fetch_andnot_acquire atomic_fetch_andnot
|
|
|
|
|
#define atomic_fetch_andnot_release atomic_fetch_andnot
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_andnot_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_andnot_acquire
|
|
|
|
|
#define atomic_fetch_andnot_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_andnot, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_andnot_release
|
|
|
|
|
#define atomic_fetch_andnot_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_andnot, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_andnot
|
|
|
|
|
#define atomic_fetch_andnot(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_andnot, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_andnot_relaxed */
|
|
|
|
|
#endif /* atomic_andnot */
|
|
|
|
|
|
|
|
|
|
/* atomic_fetch_xor_relaxed */
|
|
|
|
|
#ifndef atomic_fetch_xor_relaxed
|
|
|
|
|
#define atomic_fetch_xor_relaxed atomic_fetch_xor
|
|
|
|
|
#define atomic_fetch_xor_acquire atomic_fetch_xor
|
|
|
|
|
#define atomic_fetch_xor_release atomic_fetch_xor
|
|
|
|
|
|
|
|
|
|
#else /* atomic_fetch_xor_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_xor_acquire
|
|
|
|
|
#define atomic_fetch_xor_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_fetch_xor, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_xor_release
|
|
|
|
|
#define atomic_fetch_xor_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_fetch_xor, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_fetch_xor
|
|
|
|
|
#define atomic_fetch_xor(...) \
|
|
|
|
|
__atomic_op_fence(atomic_fetch_xor, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_fetch_xor_relaxed */
|
|
|
|
|
|
|
|
|
|
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
|
|
|
/* atomic_xchg_relaxed */
|
|
|
|
|
#ifndef atomic_xchg_relaxed
|
|
|
|
|
#define atomic_xchg_relaxed atomic_xchg
|
|
|
|
|
#define atomic_xchg_acquire atomic_xchg
|
|
|
|
|
#define atomic_xchg_release atomic_xchg
|
|
|
|
|
|
|
|
|
|
#else /* atomic_xchg_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_xchg_acquire
|
|
|
|
|
#define atomic_xchg_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_xchg_release
|
|
|
|
|
#define atomic_xchg_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_xchg
|
|
|
|
|
#define atomic_xchg(...) \
|
|
|
|
|
__atomic_op_fence(atomic_xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_xchg_relaxed */
|
|
|
|
|
|
|
|
|
|
/* atomic_cmpxchg_relaxed */
|
|
|
|
|
#ifndef atomic_cmpxchg_relaxed
|
|
|
|
|
#define atomic_cmpxchg_relaxed atomic_cmpxchg
|
|
|
|
|
#define atomic_cmpxchg_acquire atomic_cmpxchg
|
|
|
|
|
#define atomic_cmpxchg_release atomic_cmpxchg
|
|
|
|
|
|
|
|
|
|
#else /* atomic_cmpxchg_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_cmpxchg_acquire
|
|
|
|
|
#define atomic_cmpxchg_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic_cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_cmpxchg_release
|
|
|
|
|
#define atomic_cmpxchg_release(...) \
|
|
|
|
|
__atomic_op_release(atomic_cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_cmpxchg
|
|
|
|
|
#define atomic_cmpxchg(...) \
|
|
|
|
|
__atomic_op_fence(atomic_cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic_cmpxchg_relaxed */
|
|
|
|
|
|
locking/atomic: Introduce atomic_try_cmpxchg()
Add a new cmpxchg interface:
bool try_cmpxchg(u{8,16,32,64} *ptr, u{8,16,32,64} *val, u{8,16,32,64} new);
Where the boolean returns the result of the compare; and thus if the
exchange happened; and in case of failure, the new value of *ptr is
returned in *val.
This allows simplification/improvement of loops like:
for (;;) {
new = val $op $imm;
old = cmpxchg(ptr, val, new);
if (old == val)
break;
val = old;
}
into:
do {
} while (!try_cmpxchg(ptr, &val, val $op $imm));
while also generating better code (GCC6 and onwards).
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-01 23:39:38 +08:00
|
|
|
#ifndef atomic_try_cmpxchg
|
|
|
|
|
|
|
|
|
|
#define __atomic_try_cmpxchg(type, _p, _po, _n) \
|
|
|
|
|
({ \
|
|
|
|
|
typeof(_po) __po = (_po); \
|
2017-03-27 19:54:38 +08:00
|
|
|
typeof(*(_po)) __r, __o = *__po; \
|
|
|
|
|
__r = atomic_cmpxchg##type((_p), __o, (_n)); \
|
|
|
|
|
if (unlikely(__r != __o)) \
|
|
|
|
|
*__po = __r; \
|
|
|
|
|
likely(__r == __o); \
|
locking/atomic: Introduce atomic_try_cmpxchg()
Add a new cmpxchg interface:
bool try_cmpxchg(u{8,16,32,64} *ptr, u{8,16,32,64} *val, u{8,16,32,64} new);
Where the boolean returns the result of the compare; and thus if the
exchange happened; and in case of failure, the new value of *ptr is
returned in *val.
This allows simplification/improvement of loops like:
for (;;) {
new = val $op $imm;
old = cmpxchg(ptr, val, new);
if (old == val)
break;
val = old;
}
into:
do {
} while (!try_cmpxchg(ptr, &val, val $op $imm));
while also generating better code (GCC6 and onwards).
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-01 23:39:38 +08:00
|
|
|
})
|
|
|
|
|
|
|
|
|
|
#define atomic_try_cmpxchg(_p, _po, _n) __atomic_try_cmpxchg(, _p, _po, _n)
|
|
|
|
|
#define atomic_try_cmpxchg_relaxed(_p, _po, _n) __atomic_try_cmpxchg(_relaxed, _p, _po, _n)
|
|
|
|
|
#define atomic_try_cmpxchg_acquire(_p, _po, _n) __atomic_try_cmpxchg(_acquire, _p, _po, _n)
|
|
|
|
|
#define atomic_try_cmpxchg_release(_p, _po, _n) __atomic_try_cmpxchg(_release, _p, _po, _n)
|
|
|
|
|
|
|
|
|
|
#else /* atomic_try_cmpxchg */
|
|
|
|
|
#define atomic_try_cmpxchg_relaxed atomic_try_cmpxchg
|
|
|
|
|
#define atomic_try_cmpxchg_acquire atomic_try_cmpxchg
|
|
|
|
|
#define atomic_try_cmpxchg_release atomic_try_cmpxchg
|
|
|
|
|
#endif /* atomic_try_cmpxchg */
|
|
|
|
|
|
locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-08-07 00:54:37 +08:00
|
|
|
/* cmpxchg_relaxed */
|
|
|
|
|
#ifndef cmpxchg_relaxed
|
|
|
|
|
#define cmpxchg_relaxed cmpxchg
|
|
|
|
|
#define cmpxchg_acquire cmpxchg
|
|
|
|
|
#define cmpxchg_release cmpxchg
|
|
|
|
|
|
|
|
|
|
#else /* cmpxchg_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef cmpxchg_acquire
|
|
|
|
|
#define cmpxchg_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef cmpxchg_release
|
|
|
|
|
#define cmpxchg_release(...) \
|
|
|
|
|
__atomic_op_release(cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef cmpxchg
|
|
|
|
|
#define cmpxchg(...) \
|
|
|
|
|
__atomic_op_fence(cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* cmpxchg_relaxed */
|
|
|
|
|
|
|
|
|
|
/* cmpxchg64_relaxed */
|
|
|
|
|
#ifndef cmpxchg64_relaxed
|
|
|
|
|
#define cmpxchg64_relaxed cmpxchg64
|
|
|
|
|
#define cmpxchg64_acquire cmpxchg64
|
|
|
|
|
#define cmpxchg64_release cmpxchg64
|
|
|
|
|
|
|
|
|
|
#else /* cmpxchg64_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef cmpxchg64_acquire
|
|
|
|
|
#define cmpxchg64_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(cmpxchg64, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef cmpxchg64_release
|
|
|
|
|
#define cmpxchg64_release(...) \
|
|
|
|
|
__atomic_op_release(cmpxchg64, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef cmpxchg64
|
|
|
|
|
#define cmpxchg64(...) \
|
|
|
|
|
__atomic_op_fence(cmpxchg64, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* cmpxchg64_relaxed */
|
|
|
|
|
|
|
|
|
|
/* xchg_relaxed */
|
|
|
|
|
#ifndef xchg_relaxed
|
|
|
|
|
#define xchg_relaxed xchg
|
|
|
|
|
#define xchg_acquire xchg
|
|
|
|
|
#define xchg_release xchg
|
|
|
|
|
|
|
|
|
|
#else /* xchg_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef xchg_acquire
|
|
|
|
|
#define xchg_acquire(...) __atomic_op_acquire(xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef xchg_release
|
|
|
|
|
#define xchg_release(...) __atomic_op_release(xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef xchg
|
|
|
|
|
#define xchg(...) __atomic_op_fence(xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* xchg_relaxed */
|
2010-11-12 06:05:08 +08:00
|
|
|
|
2011-07-27 07:09:07 +08:00
|
|
|
/**
|
|
|
|
|
* atomic_add_unless - add unless the number is already a given value
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
* @a: the amount to add to v...
|
|
|
|
|
* @u: ...unless v is equal to u.
|
|
|
|
|
*
|
|
|
|
|
* Atomically adds @a to @v, so long as @v was not already @u.
|
|
|
|
|
* Returns non-zero if @v was not @u, and zero otherwise.
|
|
|
|
|
*/
|
|
|
|
|
static inline int atomic_add_unless(atomic_t *v, int a, int u)
|
|
|
|
|
{
|
|
|
|
|
return __atomic_add_unless(v, a, u) != u;
|
|
|
|
|
}
|
|
|
|
|
|
2011-07-27 07:09:06 +08:00
|
|
|
/**
|
|
|
|
|
* atomic_inc_not_zero - increment unless the number is zero
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
*
|
|
|
|
|
* Atomically increments @v by 1, so long as @v is non-zero.
|
|
|
|
|
* Returns non-zero if @v was non-zero, and zero otherwise.
|
|
|
|
|
*/
|
2012-03-01 05:09:53 +08:00
|
|
|
#ifndef atomic_inc_not_zero
|
2011-07-27 07:09:06 +08:00
|
|
|
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
|
2012-03-01 05:09:53 +08:00
|
|
|
#endif
|
2011-07-27 07:09:06 +08:00
|
|
|
|
2015-04-24 07:12:32 +08:00
|
|
|
#ifndef atomic_andnot
|
|
|
|
|
static inline void atomic_andnot(int i, atomic_t *v)
|
|
|
|
|
{
|
|
|
|
|
atomic_and(~i, v);
|
|
|
|
|
}
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
|
|
|
|
|
static inline int atomic_fetch_andnot(int i, atomic_t *v)
|
|
|
|
|
{
|
|
|
|
|
return atomic_fetch_and(~i, v);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int atomic_fetch_andnot_relaxed(int i, atomic_t *v)
|
|
|
|
|
{
|
|
|
|
|
return atomic_fetch_and_relaxed(~i, v);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int atomic_fetch_andnot_acquire(int i, atomic_t *v)
|
|
|
|
|
{
|
|
|
|
|
return atomic_fetch_and_acquire(~i, v);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int atomic_fetch_andnot_release(int i, atomic_t *v)
|
|
|
|
|
{
|
|
|
|
|
return atomic_fetch_and_release(~i, v);
|
|
|
|
|
}
|
2015-04-24 07:12:32 +08:00
|
|
|
#endif
|
|
|
|
|
|
2010-11-12 06:05:08 +08:00
|
|
|
/**
|
|
|
|
|
* atomic_inc_not_zero_hint - increment if not null
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
* @hint: probable value of the atomic before the increment
|
|
|
|
|
*
|
|
|
|
|
* This version of atomic_inc_not_zero() gives a hint of probable
|
|
|
|
|
* value of the atomic. This helps processor to not read the memory
|
|
|
|
|
* before doing the atomic read/modify/write cycle, lowering
|
|
|
|
|
* number of bus transactions on some arches.
|
|
|
|
|
*
|
|
|
|
|
* Returns: 0 if increment was not done, 1 otherwise.
|
|
|
|
|
*/
|
|
|
|
|
#ifndef atomic_inc_not_zero_hint
|
|
|
|
|
static inline int atomic_inc_not_zero_hint(atomic_t *v, int hint)
|
|
|
|
|
{
|
|
|
|
|
int val, c = hint;
|
|
|
|
|
|
|
|
|
|
/* sanity test, should be removed by compiler if hint is a constant */
|
|
|
|
|
if (!hint)
|
|
|
|
|
return atomic_inc_not_zero(v);
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
val = atomic_cmpxchg(v, c, c + 1);
|
|
|
|
|
if (val == c)
|
|
|
|
|
return 1;
|
|
|
|
|
c = val;
|
|
|
|
|
} while (c);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-06-20 22:52:57 +08:00
|
|
|
#ifndef atomic_inc_unless_negative
|
|
|
|
|
static inline int atomic_inc_unless_negative(atomic_t *p)
|
|
|
|
|
{
|
|
|
|
|
int v, v1;
|
|
|
|
|
for (v = 0; v >= 0; v = v1) {
|
|
|
|
|
v1 = atomic_cmpxchg(p, v, v + 1);
|
|
|
|
|
if (likely(v1 == v))
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic_dec_unless_positive
|
|
|
|
|
static inline int atomic_dec_unless_positive(atomic_t *p)
|
|
|
|
|
{
|
|
|
|
|
int v, v1;
|
|
|
|
|
for (v = 0; v <= 0; v = v1) {
|
|
|
|
|
v1 = atomic_cmpxchg(p, v, v - 1);
|
|
|
|
|
if (likely(v1 == v))
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-10-09 07:32:18 +08:00
|
|
|
/*
|
|
|
|
|
* atomic_dec_if_positive - decrement by 1 if old value positive
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
*
|
|
|
|
|
* The function returns the old value of *v minus 1, even if
|
|
|
|
|
* the atomic variable, v, was not decremented.
|
|
|
|
|
*/
|
|
|
|
|
#ifndef atomic_dec_if_positive
|
|
|
|
|
static inline int atomic_dec_if_positive(atomic_t *v)
|
|
|
|
|
{
|
|
|
|
|
int c, old, dec;
|
|
|
|
|
c = atomic_read(v);
|
|
|
|
|
for (;;) {
|
|
|
|
|
dec = c - 1;
|
|
|
|
|
if (unlikely(dec < 0))
|
|
|
|
|
break;
|
|
|
|
|
old = atomic_cmpxchg((v), c, dec);
|
|
|
|
|
if (likely(old == c))
|
|
|
|
|
break;
|
|
|
|
|
c = old;
|
|
|
|
|
}
|
|
|
|
|
return dec;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2018-04-26 18:34:15 +08:00
|
|
|
#define atomic_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
|
2017-10-12 20:20:48 +08:00
|
|
|
#define atomic_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
|
|
|
|
|
|
2011-07-27 07:09:08 +08:00
|
|
|
#ifdef CONFIG_GENERIC_ATOMIC64
|
|
|
|
|
#include <asm-generic/atomic64.h>
|
|
|
|
|
#endif
|
2015-04-24 07:12:32 +08:00
|
|
|
|
2016-04-18 06:52:13 +08:00
|
|
|
#ifndef atomic64_read_acquire
|
|
|
|
|
#define atomic64_read_acquire(v) smp_load_acquire(&(v)->counter)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_set_release
|
|
|
|
|
#define atomic64_set_release(v, i) smp_store_release(&(v)->counter, (i))
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* atomic64_add_return_relaxed */
|
|
|
|
|
#ifndef atomic64_add_return_relaxed
|
|
|
|
|
#define atomic64_add_return_relaxed atomic64_add_return
|
|
|
|
|
#define atomic64_add_return_acquire atomic64_add_return
|
|
|
|
|
#define atomic64_add_return_release atomic64_add_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_add_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_add_return_acquire
|
|
|
|
|
#define atomic64_add_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_add_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_add_return_release
|
|
|
|
|
#define atomic64_add_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_add_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_add_return
|
|
|
|
|
#define atomic64_add_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_add_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_add_return_relaxed */
|
|
|
|
|
|
|
|
|
|
/* atomic64_inc_return_relaxed */
|
|
|
|
|
#ifndef atomic64_inc_return_relaxed
|
|
|
|
|
#define atomic64_inc_return_relaxed atomic64_inc_return
|
|
|
|
|
#define atomic64_inc_return_acquire atomic64_inc_return
|
|
|
|
|
#define atomic64_inc_return_release atomic64_inc_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_inc_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_inc_return_acquire
|
|
|
|
|
#define atomic64_inc_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_inc_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_inc_return_release
|
|
|
|
|
#define atomic64_inc_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_inc_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_inc_return
|
|
|
|
|
#define atomic64_inc_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_inc_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_inc_return_relaxed */
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* atomic64_sub_return_relaxed */
|
|
|
|
|
#ifndef atomic64_sub_return_relaxed
|
|
|
|
|
#define atomic64_sub_return_relaxed atomic64_sub_return
|
|
|
|
|
#define atomic64_sub_return_acquire atomic64_sub_return
|
|
|
|
|
#define atomic64_sub_return_release atomic64_sub_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_sub_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_sub_return_acquire
|
|
|
|
|
#define atomic64_sub_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_sub_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_sub_return_release
|
|
|
|
|
#define atomic64_sub_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_sub_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_sub_return
|
|
|
|
|
#define atomic64_sub_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_sub_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_sub_return_relaxed */
|
|
|
|
|
|
|
|
|
|
/* atomic64_dec_return_relaxed */
|
|
|
|
|
#ifndef atomic64_dec_return_relaxed
|
|
|
|
|
#define atomic64_dec_return_relaxed atomic64_dec_return
|
|
|
|
|
#define atomic64_dec_return_acquire atomic64_dec_return
|
|
|
|
|
#define atomic64_dec_return_release atomic64_dec_return
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_dec_return_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_dec_return_acquire
|
|
|
|
|
#define atomic64_dec_return_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_dec_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_dec_return_release
|
|
|
|
|
#define atomic64_dec_return_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_dec_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_dec_return
|
|
|
|
|
#define atomic64_dec_return(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_dec_return, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_dec_return_relaxed */
|
|
|
|
|
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
|
|
|
|
|
/* atomic64_fetch_add_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_add_relaxed
|
|
|
|
|
#define atomic64_fetch_add_relaxed atomic64_fetch_add
|
|
|
|
|
#define atomic64_fetch_add_acquire atomic64_fetch_add
|
|
|
|
|
#define atomic64_fetch_add_release atomic64_fetch_add
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_add_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_add_acquire
|
|
|
|
|
#define atomic64_fetch_add_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_add, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_add_release
|
|
|
|
|
#define atomic64_fetch_add_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_add, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_add
|
|
|
|
|
#define atomic64_fetch_add(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_add, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_add_relaxed */
|
|
|
|
|
|
2016-06-29 05:56:51 +08:00
|
|
|
/* atomic64_fetch_inc_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_inc_relaxed
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_inc
|
|
|
|
|
#define atomic64_fetch_inc(v) atomic64_fetch_add(1, (v))
|
|
|
|
|
#define atomic64_fetch_inc_relaxed(v) atomic64_fetch_add_relaxed(1, (v))
|
|
|
|
|
#define atomic64_fetch_inc_acquire(v) atomic64_fetch_add_acquire(1, (v))
|
|
|
|
|
#define atomic64_fetch_inc_release(v) atomic64_fetch_add_release(1, (v))
|
|
|
|
|
#else /* atomic64_fetch_inc */
|
|
|
|
|
#define atomic64_fetch_inc_relaxed atomic64_fetch_inc
|
|
|
|
|
#define atomic64_fetch_inc_acquire atomic64_fetch_inc
|
|
|
|
|
#define atomic64_fetch_inc_release atomic64_fetch_inc
|
|
|
|
|
#endif /* atomic64_fetch_inc */
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_inc_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_inc_acquire
|
|
|
|
|
#define atomic64_fetch_inc_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_inc, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_inc_release
|
|
|
|
|
#define atomic64_fetch_inc_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_inc, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_inc
|
|
|
|
|
#define atomic64_fetch_inc(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_inc, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_inc_relaxed */
|
|
|
|
|
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
/* atomic64_fetch_sub_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_sub_relaxed
|
|
|
|
|
#define atomic64_fetch_sub_relaxed atomic64_fetch_sub
|
|
|
|
|
#define atomic64_fetch_sub_acquire atomic64_fetch_sub
|
|
|
|
|
#define atomic64_fetch_sub_release atomic64_fetch_sub
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_sub_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_sub_acquire
|
|
|
|
|
#define atomic64_fetch_sub_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_sub, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_sub_release
|
|
|
|
|
#define atomic64_fetch_sub_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_sub, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_sub
|
|
|
|
|
#define atomic64_fetch_sub(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_sub, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_sub_relaxed */
|
|
|
|
|
|
2016-06-29 05:56:51 +08:00
|
|
|
/* atomic64_fetch_dec_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_dec_relaxed
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_dec
|
|
|
|
|
#define atomic64_fetch_dec(v) atomic64_fetch_sub(1, (v))
|
|
|
|
|
#define atomic64_fetch_dec_relaxed(v) atomic64_fetch_sub_relaxed(1, (v))
|
|
|
|
|
#define atomic64_fetch_dec_acquire(v) atomic64_fetch_sub_acquire(1, (v))
|
|
|
|
|
#define atomic64_fetch_dec_release(v) atomic64_fetch_sub_release(1, (v))
|
|
|
|
|
#else /* atomic64_fetch_dec */
|
|
|
|
|
#define atomic64_fetch_dec_relaxed atomic64_fetch_dec
|
|
|
|
|
#define atomic64_fetch_dec_acquire atomic64_fetch_dec
|
|
|
|
|
#define atomic64_fetch_dec_release atomic64_fetch_dec
|
|
|
|
|
#endif /* atomic64_fetch_dec */
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_dec_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_dec_acquire
|
|
|
|
|
#define atomic64_fetch_dec_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_dec, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_dec_release
|
|
|
|
|
#define atomic64_fetch_dec_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_dec, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_dec
|
|
|
|
|
#define atomic64_fetch_dec(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_dec, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_dec_relaxed */
|
|
|
|
|
|
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
|
|
|
/* atomic64_fetch_or_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_or_relaxed
|
|
|
|
|
#define atomic64_fetch_or_relaxed atomic64_fetch_or
|
|
|
|
|
#define atomic64_fetch_or_acquire atomic64_fetch_or
|
|
|
|
|
#define atomic64_fetch_or_release atomic64_fetch_or
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_or_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_or_acquire
|
|
|
|
|
#define atomic64_fetch_or_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_or, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_or_release
|
|
|
|
|
#define atomic64_fetch_or_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_or, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_or
|
|
|
|
|
#define atomic64_fetch_or(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_or, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_or_relaxed */
|
|
|
|
|
|
|
|
|
|
/* atomic64_fetch_and_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_and_relaxed
|
|
|
|
|
#define atomic64_fetch_and_relaxed atomic64_fetch_and
|
|
|
|
|
#define atomic64_fetch_and_acquire atomic64_fetch_and
|
|
|
|
|
#define atomic64_fetch_and_release atomic64_fetch_and
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_and_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_and_acquire
|
|
|
|
|
#define atomic64_fetch_and_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_and, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_and_release
|
|
|
|
|
#define atomic64_fetch_and_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_and, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_and
|
|
|
|
|
#define atomic64_fetch_and(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_and, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_and_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifdef atomic64_andnot
|
|
|
|
|
/* atomic64_fetch_andnot_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_andnot_relaxed
|
|
|
|
|
#define atomic64_fetch_andnot_relaxed atomic64_fetch_andnot
|
|
|
|
|
#define atomic64_fetch_andnot_acquire atomic64_fetch_andnot
|
|
|
|
|
#define atomic64_fetch_andnot_release atomic64_fetch_andnot
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_andnot_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_andnot_acquire
|
|
|
|
|
#define atomic64_fetch_andnot_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_andnot, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_andnot_release
|
|
|
|
|
#define atomic64_fetch_andnot_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_andnot, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_andnot
|
|
|
|
|
#define atomic64_fetch_andnot(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_andnot, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_andnot_relaxed */
|
|
|
|
|
#endif /* atomic64_andnot */
|
|
|
|
|
|
|
|
|
|
/* atomic64_fetch_xor_relaxed */
|
|
|
|
|
#ifndef atomic64_fetch_xor_relaxed
|
|
|
|
|
#define atomic64_fetch_xor_relaxed atomic64_fetch_xor
|
|
|
|
|
#define atomic64_fetch_xor_acquire atomic64_fetch_xor
|
|
|
|
|
#define atomic64_fetch_xor_release atomic64_fetch_xor
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_fetch_xor_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_xor_acquire
|
|
|
|
|
#define atomic64_fetch_xor_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_fetch_xor, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_xor_release
|
|
|
|
|
#define atomic64_fetch_xor_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_fetch_xor, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_fetch_xor
|
|
|
|
|
#define atomic64_fetch_xor(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_fetch_xor, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_fetch_xor_relaxed */
|
|
|
|
|
|
|
|
|
|
|
2016-04-18 06:52:13 +08:00
|
|
|
/* atomic64_xchg_relaxed */
|
|
|
|
|
#ifndef atomic64_xchg_relaxed
|
|
|
|
|
#define atomic64_xchg_relaxed atomic64_xchg
|
|
|
|
|
#define atomic64_xchg_acquire atomic64_xchg
|
|
|
|
|
#define atomic64_xchg_release atomic64_xchg
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_xchg_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_xchg_acquire
|
|
|
|
|
#define atomic64_xchg_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_xchg_release
|
|
|
|
|
#define atomic64_xchg_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_xchg
|
|
|
|
|
#define atomic64_xchg(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_xchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_xchg_relaxed */
|
|
|
|
|
|
|
|
|
|
/* atomic64_cmpxchg_relaxed */
|
|
|
|
|
#ifndef atomic64_cmpxchg_relaxed
|
|
|
|
|
#define atomic64_cmpxchg_relaxed atomic64_cmpxchg
|
|
|
|
|
#define atomic64_cmpxchg_acquire atomic64_cmpxchg
|
|
|
|
|
#define atomic64_cmpxchg_release atomic64_cmpxchg
|
|
|
|
|
|
|
|
|
|
#else /* atomic64_cmpxchg_relaxed */
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_cmpxchg_acquire
|
|
|
|
|
#define atomic64_cmpxchg_acquire(...) \
|
|
|
|
|
__atomic_op_acquire(atomic64_cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_cmpxchg_release
|
|
|
|
|
#define atomic64_cmpxchg_release(...) \
|
|
|
|
|
__atomic_op_release(atomic64_cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef atomic64_cmpxchg
|
|
|
|
|
#define atomic64_cmpxchg(...) \
|
|
|
|
|
__atomic_op_fence(atomic64_cmpxchg, __VA_ARGS__)
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* atomic64_cmpxchg_relaxed */
|
|
|
|
|
|
locking/atomic: Introduce atomic_try_cmpxchg()
Add a new cmpxchg interface:
bool try_cmpxchg(u{8,16,32,64} *ptr, u{8,16,32,64} *val, u{8,16,32,64} new);
Where the boolean returns the result of the compare; and thus if the
exchange happened; and in case of failure, the new value of *ptr is
returned in *val.
This allows simplification/improvement of loops like:
for (;;) {
new = val $op $imm;
old = cmpxchg(ptr, val, new);
if (old == val)
break;
val = old;
}
into:
do {
} while (!try_cmpxchg(ptr, &val, val $op $imm));
while also generating better code (GCC6 and onwards).
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-01 23:39:38 +08:00
|
|
|
#ifndef atomic64_try_cmpxchg
|
|
|
|
|
|
|
|
|
|
#define __atomic64_try_cmpxchg(type, _p, _po, _n) \
|
|
|
|
|
({ \
|
|
|
|
|
typeof(_po) __po = (_po); \
|
2017-03-27 19:54:38 +08:00
|
|
|
typeof(*(_po)) __r, __o = *__po; \
|
|
|
|
|
__r = atomic64_cmpxchg##type((_p), __o, (_n)); \
|
|
|
|
|
if (unlikely(__r != __o)) \
|
|
|
|
|
*__po = __r; \
|
|
|
|
|
likely(__r == __o); \
|
locking/atomic: Introduce atomic_try_cmpxchg()
Add a new cmpxchg interface:
bool try_cmpxchg(u{8,16,32,64} *ptr, u{8,16,32,64} *val, u{8,16,32,64} new);
Where the boolean returns the result of the compare; and thus if the
exchange happened; and in case of failure, the new value of *ptr is
returned in *val.
This allows simplification/improvement of loops like:
for (;;) {
new = val $op $imm;
old = cmpxchg(ptr, val, new);
if (old == val)
break;
val = old;
}
into:
do {
} while (!try_cmpxchg(ptr, &val, val $op $imm));
while also generating better code (GCC6 and onwards).
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-01 23:39:38 +08:00
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})
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#define atomic64_try_cmpxchg(_p, _po, _n) __atomic64_try_cmpxchg(, _p, _po, _n)
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#define atomic64_try_cmpxchg_relaxed(_p, _po, _n) __atomic64_try_cmpxchg(_relaxed, _p, _po, _n)
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#define atomic64_try_cmpxchg_acquire(_p, _po, _n) __atomic64_try_cmpxchg(_acquire, _p, _po, _n)
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#define atomic64_try_cmpxchg_release(_p, _po, _n) __atomic64_try_cmpxchg(_release, _p, _po, _n)
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#else /* atomic64_try_cmpxchg */
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#define atomic64_try_cmpxchg_relaxed atomic64_try_cmpxchg
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#define atomic64_try_cmpxchg_acquire atomic64_try_cmpxchg
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#define atomic64_try_cmpxchg_release atomic64_try_cmpxchg
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#endif /* atomic64_try_cmpxchg */
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2015-04-24 07:12:32 +08:00
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#ifndef atomic64_andnot
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static inline void atomic64_andnot(long long i, atomic64_t *v)
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{
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atomic64_and(~i, v);
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}
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locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
Now that all the architectures have implemented support for these new
atomic primitives add on the generic infrastructure to expose and use
it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-18 06:54:38 +08:00
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static inline long long atomic64_fetch_andnot(long long i, atomic64_t *v)
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{
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return atomic64_fetch_and(~i, v);
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}
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static inline long long atomic64_fetch_andnot_relaxed(long long i, atomic64_t *v)
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{
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return atomic64_fetch_and_relaxed(~i, v);
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}
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static inline long long atomic64_fetch_andnot_acquire(long long i, atomic64_t *v)
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{
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return atomic64_fetch_and_acquire(~i, v);
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}
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static inline long long atomic64_fetch_andnot_release(long long i, atomic64_t *v)
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{
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return atomic64_fetch_and_release(~i, v);
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}
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2015-04-24 07:12:32 +08:00
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#endif
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2018-04-26 18:34:15 +08:00
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#define atomic64_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
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2017-10-12 20:20:48 +08:00
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#define atomic64_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
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2015-09-18 21:04:59 +08:00
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#include <asm-generic/atomic-long.h>
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2010-11-12 06:05:08 +08:00
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#endif /* _LINUX_ATOMIC_H */
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