2013-02-25 22:44:26 +08:00
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#
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# Makefile for sunxi specific clk
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#
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obj-y += clk-sunxi.o clk-factors.o
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2014-07-19 02:49:37 +08:00
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obj-y += clk-a10-codec.o
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2014-05-10 11:33:38 +08:00
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obj-y += clk-a10-hosc.o
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2014-07-19 02:28:02 +08:00
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obj-y += clk-a10-mod1.o
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clk: sunxi: Add a driver for the PLL2
The PLL2 on the A10 and later SoCs is the clock used for all the audio
related operations.
This clock has a somewhat complex output tree, with three outputs (2X, 4X
and 8X) with a fixed divider from the base clock, and an output (1X) with a
post divider.
However, we can simplify things since the 1X divider can be fixed, and we
end up by having a base clock not exposed to any device (or at least
directly, since the 4X output doesn't have any divider), and 4 fixed
divider clocks that will be exposed.
This clock seems to have been introduced, at least in this form, in the
revision B of the A10, but we don't have any information on the clock used
on the revision A.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2014-07-19 02:48:35 +08:00
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obj-y += clk-a10-pll2.o
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2014-05-10 11:33:38 +08:00
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obj-y += clk-a20-gmac.o
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2014-07-11 05:55:18 +08:00
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obj-y += clk-mod0.o
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2015-08-01 01:46:22 +08:00
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obj-y += clk-simple-gates.o
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2014-09-16 18:04:01 +08:00
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obj-y += clk-sun8i-mbus.o
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2014-10-20 22:10:27 +08:00
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obj-y += clk-sun9i-core.o
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2015-01-20 23:46:31 +08:00
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obj-y += clk-sun9i-mmc.o
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2015-01-28 03:54:06 +08:00
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obj-y += clk-usb.o
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2014-05-15 16:55:11 +08:00
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2015-11-29 11:03:08 +08:00
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obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
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2014-07-03 22:55:41 +08:00
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obj-$(CONFIG_MFD_SUN6I_PRCM) += \
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clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
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clk-sun8i-apb0.o
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