2019-05-29 01:10:04 +08:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
clk: tegra: add Tegra specific clocks
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 15:46:20 +08:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/clk-provider.h>
|
|
|
|
#include <linux/slab.h>
|
|
|
|
#include <linux/err.h>
|
|
|
|
|
|
|
|
#include "clk.h"
|
|
|
|
|
|
|
|
static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
|
|
|
|
|
|
|
|
return sync->rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *prate)
|
|
|
|
{
|
|
|
|
struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
|
|
|
|
|
|
|
|
if (rate > sync->max_rate)
|
|
|
|
return -EINVAL;
|
|
|
|
else
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
|
|
|
|
|
|
|
|
sync->rate = rate;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops tegra_clk_sync_source_ops = {
|
|
|
|
.round_rate = clk_sync_source_round_rate,
|
|
|
|
.set_rate = clk_sync_source_set_rate,
|
|
|
|
.recalc_rate = clk_sync_source_recalc_rate,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct clk *tegra_clk_register_sync_source(const char *name,
|
2018-12-03 18:28:40 +08:00
|
|
|
unsigned long max_rate)
|
clk: tegra: add Tegra specific clocks
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 15:46:20 +08:00
|
|
|
{
|
|
|
|
struct tegra_clk_sync_source *sync;
|
|
|
|
struct clk_init_data init;
|
|
|
|
struct clk *clk;
|
|
|
|
|
|
|
|
sync = kzalloc(sizeof(*sync), GFP_KERNEL);
|
|
|
|
if (!sync) {
|
|
|
|
pr_err("%s: could not allocate sync source clk\n", __func__);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
sync->max_rate = max_rate;
|
|
|
|
|
|
|
|
init.ops = &tegra_clk_sync_source_ops;
|
|
|
|
init.name = name;
|
2016-03-02 03:00:02 +08:00
|
|
|
init.flags = 0;
|
clk: tegra: add Tegra specific clocks
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 15:46:20 +08:00
|
|
|
init.parent_names = NULL;
|
|
|
|
init.num_parents = 0;
|
|
|
|
|
|
|
|
/* Data in .init is copied by clk_register(), so stack variable OK */
|
|
|
|
sync->hw.init = &init;
|
|
|
|
|
|
|
|
clk = clk_register(NULL, &sync->hw);
|
|
|
|
if (IS_ERR(clk))
|
|
|
|
kfree(sync);
|
|
|
|
|
|
|
|
return clk;
|
|
|
|
}
|