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OpenCloudOS-Kernel/drivers/clk/sunxi-ng/Kconfig

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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 20:07:45 +08:00
# SPDX-License-Identifier: GPL-2.0-only
clk: sunxi-ng: Add common infrastructure Start our new clock infrastructure by adding the registration code, common structure and common code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
2016-06-30 03:05:23 +08:00
config SUNXI_CCU
bool "Clock support for Allwinner SoCs"
clk: sunxi-ng: Add hardware dependency The sunxi-ng clock driver is useless for other architectures. Signed-off-by: Jean Delvare <jdelvare@suse.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-09-09 05:28:29 +08:00
depends on ARCH_SUNXI || COMPILE_TEST
clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER With CONFIG_RESET_CONTROLLER=n we get the following link error in the sunxi-ng clk driver: drivers/built-in.o: In function `sunxi_ccu_probe': mux-core.c:(.text+0x12fe68): undefined reference to 'reset_controller_register' mux-core.c:(.text+0x12fe68): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol 'reset_controller_register' Fix this by adding the appropriate select statement. Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27 17:57:53 +08:00
select RESET_CONTROLLER
clk: sunxi-ng: Add common infrastructure Start our new clock infrastructure by adding the registration code, common structure and common code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
2016-06-30 03:05:23 +08:00
default ARCH_SUNXI
clk: sunxi-ng: Add fractional lib Some clocks can be switched to a mode called fractional that have two fixed output rate you can choose from. Add a small library to deal with those clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-4-maxime.ripard@free-electrons.com
2016-06-30 03:05:24 +08:00
if SUNXI_CCU
clk: sunxi-ng: add support for suniv F1C100s SoC The suniv F1C100s SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-03 04:23:47 +08:00
config SUNIV_F1C100S_CCU
bool "Support for the Allwinner newer F1C100s CCU"
default MACH_SUNIV
depends on MACH_SUNIV || COMPILE_TEST
clk: sunxi-ng: Add A64 clocks Add the A64 CCU clocks set. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-07-06 14:31:34 +08:00
config SUN50I_A64_CCU
bool "Support for the Allwinner A64 CCU"
default ARM64 && ARCH_SUNXI
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
clk: sunxi-ng: Add A64 clocks Add the A64 CCU clocks set. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-07-06 14:31:34 +08:00
clk: sunxi-ng: add support for the Allwinner A100 CCU Add support for a100 in the sunxi-ng CCU framework. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1eb41bf6c966a0e54820200650d27a5d4f2ac160.1595572867.git.frank@allwinnertech.com
2020-07-24 14:58:43 +08:00
config SUN50I_A100_CCU
bool "Support for the Allwinner A100 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_A100_R_CCU
bool "Support for the Allwinner A100 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
clk: sunxi-ng: add support for the Allwinner H6 CCU The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-16 22:02:13 +08:00
config SUN50I_H6_CCU
bool "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
clk: sunxi-ng: Add support for the Allwinner H616 CCU While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
2021-01-28 01:24:43 +08:00
config SUN50I_H616_CCU
bool "Support for the Allwinner H616 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
clk: sunxi-ng: add support for H6 PRCM CCU The H6 has clock/reset controls in PRCM part, like old SoCs such as H3 and A64. However, the PRCM CCU is rearranged; the register arragement is now similar to the main CCU of H6, and the PRCM now has two APB buses to control -- one is clocked from AHB clock derivde from AR100 clock, the other is clocked from the same mux with AR100 clock. Therefore a new driver is written for it. As there's no official document about the PRCM in H6, all the information are indirectly collected from BSP and parts of the document, and the information source is noted as comments in the driver's source code. If reliable information is provided furtherly, the driver needs to be rechecked. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-05-04 02:38:41 +08:00
config SUN50I_H6_R_CCU
clk: sunxi-ng: Add support for the Allwinner H616 R-CCU The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-3-andre.przywara@arm.com
2021-01-28 01:24:42 +08:00
bool "Support for the Allwinner H6 and H616 PRCM CCU"
clk: sunxi-ng: add support for H6 PRCM CCU The H6 has clock/reset controls in PRCM part, like old SoCs such as H3 and A64. However, the PRCM CCU is rearranged; the register arragement is now similar to the main CCU of H6, and the PRCM now has two APB buses to control -- one is clocked from AHB clock derivde from AR100 clock, the other is clocked from the same mux with AR100 clock. Therefore a new driver is written for it. As there's no official document about the PRCM in H6, all the information are indirectly collected from BSP and parts of the document, and the information source is noted as comments in the driver's source code. If reliable information is provided furtherly, the driver needs to be rechecked. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-05-04 02:38:41 +08:00
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
clk: sunxi-ng: Add sun4i/sun7i CCU driver Introduce a clock controller driver for sun4i A10 and sun7i A20 series SoCs. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-24 01:23:29 +08:00
config SUN4I_A10_CCU
bool "Support for the Allwinner A10/A20 CCU"
default MACH_SUN4I
default MACH_SUN7I
depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
clk: sunxi-ng: Add sun5i CCU driver The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-04 16:09:58 +08:00
config SUN5I_CCU
bool "Support for the Allwinner sun5i family CCM"
default MACH_SUN5I
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN5I || COMPILE_TEST
clk: sunxi-ng: Add sun5i CCU driver The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-04 16:09:58 +08:00
clk: sunxi-ng: Add A31/A31s clocks Add a new style driver for the clock control unit in Allwinner A31/A31s. A few clocks are still missing: - MIPI PLL's HDMI mode support - EMAC clock Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-25 14:21:59 +08:00
config SUN6I_A31_CCU
bool "Support for the Allwinner A31/A31s CCU"
default MACH_SUN6I
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN6I || COMPILE_TEST
clk: sunxi-ng: Add A31/A31s clocks Add a new style driver for the clock control unit in Allwinner A31/A31s. A few clocks are still missing: - MIPI PLL's HDMI mode support - EMAC clock Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-25 14:21:59 +08:00
clk: sunxi-ng: Add A23 CCU Add support for the clock unit found in the A23. Due to the similarities with the A33, it also shares its clock IDs to allow sharing the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-08-31 22:55:00 +08:00
config SUN8I_A23_CCU
bool "Support for the Allwinner A23 CCU"
default MACH_SUN8I
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN8I || COMPILE_TEST
clk: sunxi-ng: Add A23 CCU Add support for the clock unit found in the A23. Due to the similarities with the A33, it also shares its clock IDs to allow sharing the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-08-31 22:55:00 +08:00
clk: sunxi-ng: Add A33 CCU support This commit introduces the clocks found in the Allwinner A33 CCU. Since this SoC is very similar to the A23, and we share a significant share of the DTSI, the clock IDs that are going to be used will also be shared with the A23, hence the name of the various header files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-08-24 20:10:15 +08:00
config SUN8I_A33_CCU
bool "Support for the Allwinner A33 CCU"
default MACH_SUN8I
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN8I || COMPILE_TEST
clk: sunxi-ng: Add A33 CCU support This commit introduces the clocks found in the Allwinner A33 CCU. Since this SoC is very similar to the A23, and we share a significant share of the DTSI, the clock IDs that are going to be used will also be shared with the A23, hence the name of the various header files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-08-24 20:10:15 +08:00
clk: sunxi-ng: Add driver for A83T CCU The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Also, the MMC2 module clock supports switching to a "new timing" mode. This mode divides the clock output by half, and disables the CCU based clock delays. The MMC controller must be configure to the same mode, and then use its internal clock delays. This driver does not support runtime switching of the timing modes. Instead, the new timing mode is enforced at probe time. Consumers can check which mode is active by trying to get the current phase delay of the MMC2 phase clocks, which will return -ENOTSUPP if the new timing mode is active. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-19 15:06:09 +08:00
config SUN8I_A83T_CCU
bool "Support for the Allwinner A83T CCU"
default MACH_SUN8I
clk: sunxi-ng: Add machine dependency to A83T CCU The CCUs for all other 32-bit SoCs have a dependency on a specific MACH_SUNxI symbol. This effectively hides these drivers when building an ARCH=arm64 kernel. However, the A83T CCU still shows up because it is missing this dependency. Let's add it for consistency. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210902230200.29574-1-samuel@sholland.org
2021-09-03 07:02:00 +08:00
depends on MACH_SUN8I || COMPILE_TEST
clk: sunxi-ng: Add driver for A83T CCU The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Also, the MMC2 module clock supports switching to a "new timing" mode. This mode divides the clock output by half, and disables the CCU based clock delays. The MMC controller must be configure to the same mode, and then use its internal clock delays. This driver does not support runtime switching of the timing modes. Instead, the new timing mode is enforced at probe time. Consumers can check which mode is active by trying to get the current phase delay of the MMC2 phase clocks, which will return -ENOTSUPP if the new timing mode is active. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-19 15:06:09 +08:00
clk: sunxi-ng: Add H3 clocks Add the list of clocks and resets found in the H3 CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com
2016-06-30 03:05:34 +08:00
config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver Allwinner H5 is a SoC that features a design which keeps the peripheral compatible with H3, so that it have also a CCU like the one on H3 -- only one bus gate/reset is added, and the mmc sample/output phases are removed because of MMC controller update. Add its support in our existing H3 CCU driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-02 04:13:39 +08:00
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
clk: sunxi-ng: Add H3 clocks Add the list of clocks and resets found in the H3 CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com
2016-06-30 03:05:34 +08:00
clk: sunxi-ng: add support for V3s CCU V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-20 01:54:45 +08:00
config SUN8I_V3S_CCU
bool "Support for the Allwinner V3s CCU"
default MACH_SUN8I
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN8I || COMPILE_TEST
clk: sunxi-ng: add support for V3s CCU V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-20 01:54:45 +08:00
clk: sunxi-ng: add support for DE2 CCU The "Display Engine 2.0" in Allwinner newer SoCs contains a clock management unit for its subunits, like the DE CCU in A80. Add a sunxi-ng style driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-15 00:30:34 +08:00
config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them as default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-13 20:15:32 +08:00
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
clk: sunxi-ng: add support for DE2 CCU The "Display Engine 2.0" in Allwinner newer SoCs contains a clock management unit for its subunits, like the DE CCU in A80. Add a sunxi-ng style driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-15 00:30:34 +08:00
clk: sunxi-ng: support R40 SoC Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-15 13:55:29 +08:00
config SUN8I_R40_CCU
bool "Support for the Allwinner R40 CCU"
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
clk: sunxi-ng: Add A80 CCU Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-28 20:22:34 +08:00
config SUN9I_A80_CCU
bool "Support for the Allwinner A80 CCU"
default MACH_SUN9I
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-03 01:43:57 +08:00
depends on MACH_SUN9I || COMPILE_TEST
clk: sunxi-ng: Add A80 CCU Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-28 20:22:34 +08:00
clk: sunxi-ng: add support for PRCM CCUs SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04 17:50:57 +08:00
config SUN8I_R_CCU
bool "Support for Allwinner SoCs' PRCM CCUs"
default MACH_SUN8I || (ARCH_SUNXI && ARM64)
clk: sunxi-ng: Add A80 CCU Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-28 20:22:34 +08:00
clk: sunxi-ng: Add fractional lib Some clocks can be switched to a mode called fractional that have two fixed output rate you can choose from. Add a small library to deal with those clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-4-maxime.ripard@free-electrons.com
2016-06-30 03:05:24 +08:00
endif