2017-11-03 18:28:30 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2021-03-29 21:51:08 +08:00
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/*
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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* debugfs.c - DesignWare USB3 DRD Controller DebugFS file
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*
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2020-07-11 21:58:04 +08:00
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/ptrace.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/delay.h>
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2011-11-04 18:32:47 +08:00
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#include <linux/uaccess.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2012-01-03 00:38:30 +08:00
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#include <linux/usb/ch9.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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2011-11-04 18:40:05 +08:00
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#include "debug.h"
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2018-11-08 09:55:13 +08:00
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#define DWC3_LSP_MUX_UNSELECTED 0xfffff
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#define dump_register(nm) \
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{ \
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.name = __stringify(nm), \
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2016-04-12 21:53:39 +08:00
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.offset = DWC3_ ##nm, \
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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}
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2016-04-12 21:53:39 +08:00
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#define dump_ep_register_set(n) \
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{ \
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.name = "DEPCMDPAR2("__stringify(n)")", \
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMDPAR2, \
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}, \
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{ \
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.name = "DEPCMDPAR1("__stringify(n)")", \
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMDPAR1, \
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}, \
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{ \
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.name = "DEPCMDPAR0("__stringify(n)")", \
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMDPAR0, \
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}, \
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{ \
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.name = "DEPCMD("__stringify(n)")", \
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.offset = DWC3_DEP_BASE(n) + \
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DWC3_DEPCMD, \
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}
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2013-02-22 22:17:31 +08:00
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static const struct debugfs_reg32 dwc3_regs[] = {
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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dump_register(GSBUSCFG0),
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dump_register(GSBUSCFG1),
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dump_register(GTXTHRCFG),
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dump_register(GRXTHRCFG),
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dump_register(GCTL),
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dump_register(GEVTEN),
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dump_register(GSTS),
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2016-05-13 18:13:46 +08:00
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dump_register(GUCTL1),
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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dump_register(GSNPSID),
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dump_register(GGPIO),
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dump_register(GUID),
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dump_register(GUCTL),
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dump_register(GBUSERRADDR0),
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dump_register(GBUSERRADDR1),
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dump_register(GPRTBIMAP0),
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dump_register(GPRTBIMAP1),
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dump_register(GHWPARAMS0),
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dump_register(GHWPARAMS1),
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dump_register(GHWPARAMS2),
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dump_register(GHWPARAMS3),
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dump_register(GHWPARAMS4),
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dump_register(GHWPARAMS5),
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dump_register(GHWPARAMS6),
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dump_register(GHWPARAMS7),
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dump_register(GDBGFIFOSPACE),
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dump_register(GDBGLTSSM),
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2018-03-17 06:35:51 +08:00
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dump_register(GDBGBMU),
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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dump_register(GPRTBIMAP_HS0),
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dump_register(GPRTBIMAP_HS1),
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dump_register(GPRTBIMAP_FS0),
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dump_register(GPRTBIMAP_FS1),
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dump_register(GUSB2PHYCFG(0)),
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dump_register(GUSB2PHYCFG(1)),
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dump_register(GUSB2PHYCFG(2)),
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dump_register(GUSB2PHYCFG(3)),
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dump_register(GUSB2PHYCFG(4)),
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dump_register(GUSB2PHYCFG(5)),
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dump_register(GUSB2PHYCFG(6)),
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dump_register(GUSB2PHYCFG(7)),
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dump_register(GUSB2PHYCFG(8)),
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dump_register(GUSB2PHYCFG(9)),
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dump_register(GUSB2PHYCFG(10)),
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dump_register(GUSB2PHYCFG(11)),
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dump_register(GUSB2PHYCFG(12)),
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dump_register(GUSB2PHYCFG(13)),
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dump_register(GUSB2PHYCFG(14)),
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dump_register(GUSB2PHYCFG(15)),
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dump_register(GUSB2I2CCTL(0)),
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dump_register(GUSB2I2CCTL(1)),
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dump_register(GUSB2I2CCTL(2)),
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dump_register(GUSB2I2CCTL(3)),
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dump_register(GUSB2I2CCTL(4)),
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dump_register(GUSB2I2CCTL(5)),
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dump_register(GUSB2I2CCTL(6)),
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dump_register(GUSB2I2CCTL(7)),
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dump_register(GUSB2I2CCTL(8)),
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dump_register(GUSB2I2CCTL(9)),
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dump_register(GUSB2I2CCTL(10)),
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dump_register(GUSB2I2CCTL(11)),
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dump_register(GUSB2I2CCTL(12)),
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dump_register(GUSB2I2CCTL(13)),
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dump_register(GUSB2I2CCTL(14)),
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dump_register(GUSB2I2CCTL(15)),
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dump_register(GUSB2PHYACC(0)),
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dump_register(GUSB2PHYACC(1)),
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dump_register(GUSB2PHYACC(2)),
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dump_register(GUSB2PHYACC(3)),
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dump_register(GUSB2PHYACC(4)),
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dump_register(GUSB2PHYACC(5)),
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dump_register(GUSB2PHYACC(6)),
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dump_register(GUSB2PHYACC(7)),
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dump_register(GUSB2PHYACC(8)),
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dump_register(GUSB2PHYACC(9)),
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dump_register(GUSB2PHYACC(10)),
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dump_register(GUSB2PHYACC(11)),
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dump_register(GUSB2PHYACC(12)),
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dump_register(GUSB2PHYACC(13)),
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dump_register(GUSB2PHYACC(14)),
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dump_register(GUSB2PHYACC(15)),
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dump_register(GUSB3PIPECTL(0)),
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dump_register(GUSB3PIPECTL(1)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(2)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(3)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(4)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(5)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(6)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(7)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(8)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(9)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(10)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(11)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(12)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(13)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(14)),
|
|
|
|
|
dump_register(GUSB3PIPECTL(15)),
|
|
|
|
|
|
|
|
|
|
dump_register(GTXFIFOSIZ(0)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(1)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(2)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(3)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(4)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(5)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(6)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(7)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(8)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(9)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(10)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(11)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(12)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(13)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(14)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(15)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(16)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(17)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(18)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(19)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(20)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(21)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(22)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(23)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(24)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(25)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(26)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(27)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(28)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(29)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(30)),
|
|
|
|
|
dump_register(GTXFIFOSIZ(31)),
|
|
|
|
|
|
|
|
|
|
dump_register(GRXFIFOSIZ(0)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(1)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(2)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(3)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(4)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(5)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(6)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(7)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(8)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(9)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(10)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(11)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(12)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(13)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(14)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(15)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(16)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(17)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(18)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(19)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(20)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(21)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(22)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(23)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(24)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(25)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(26)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(27)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(28)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(29)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(30)),
|
|
|
|
|
dump_register(GRXFIFOSIZ(31)),
|
|
|
|
|
|
|
|
|
|
dump_register(GEVNTADRLO(0)),
|
|
|
|
|
dump_register(GEVNTADRHI(0)),
|
|
|
|
|
dump_register(GEVNTSIZ(0)),
|
|
|
|
|
dump_register(GEVNTCOUNT(0)),
|
|
|
|
|
|
|
|
|
|
dump_register(GHWPARAMS8),
|
|
|
|
|
dump_register(DCFG),
|
|
|
|
|
dump_register(DCTL),
|
|
|
|
|
dump_register(DEVTEN),
|
|
|
|
|
dump_register(DSTS),
|
|
|
|
|
dump_register(DGCMDPAR),
|
|
|
|
|
dump_register(DGCMD),
|
|
|
|
|
dump_register(DALEPENA),
|
|
|
|
|
|
2016-04-12 21:53:39 +08:00
|
|
|
dump_ep_register_set(0),
|
|
|
|
|
dump_ep_register_set(1),
|
|
|
|
|
dump_ep_register_set(2),
|
|
|
|
|
dump_ep_register_set(3),
|
|
|
|
|
dump_ep_register_set(4),
|
|
|
|
|
dump_ep_register_set(5),
|
|
|
|
|
dump_ep_register_set(6),
|
|
|
|
|
dump_ep_register_set(7),
|
|
|
|
|
dump_ep_register_set(8),
|
|
|
|
|
dump_ep_register_set(9),
|
|
|
|
|
dump_ep_register_set(10),
|
|
|
|
|
dump_ep_register_set(11),
|
|
|
|
|
dump_ep_register_set(12),
|
|
|
|
|
dump_ep_register_set(13),
|
|
|
|
|
dump_ep_register_set(14),
|
|
|
|
|
dump_ep_register_set(15),
|
|
|
|
|
dump_ep_register_set(16),
|
|
|
|
|
dump_ep_register_set(17),
|
|
|
|
|
dump_ep_register_set(18),
|
|
|
|
|
dump_ep_register_set(19),
|
|
|
|
|
dump_ep_register_set(20),
|
|
|
|
|
dump_ep_register_set(21),
|
|
|
|
|
dump_ep_register_set(22),
|
|
|
|
|
dump_ep_register_set(23),
|
|
|
|
|
dump_ep_register_set(24),
|
|
|
|
|
dump_ep_register_set(25),
|
|
|
|
|
dump_ep_register_set(26),
|
|
|
|
|
dump_ep_register_set(27),
|
|
|
|
|
dump_ep_register_set(28),
|
|
|
|
|
dump_ep_register_set(29),
|
|
|
|
|
dump_ep_register_set(30),
|
|
|
|
|
dump_ep_register_set(31),
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
|
dump_register(OCFG),
|
|
|
|
|
dump_register(OCTL),
|
2013-03-14 18:35:24 +08:00
|
|
|
dump_register(OEVT),
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dump_register(OEVTEN),
|
|
|
|
|
dump_register(OSTS),
|
|
|
|
|
};
|
|
|
|
|
|
2018-11-08 09:55:13 +08:00
|
|
|
static void dwc3_host_lsp(struct seq_file *s)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
bool dbc_enabled;
|
|
|
|
|
u32 sel;
|
|
|
|
|
u32 reg;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
dbc_enabled = !!(dwc->hwparams.hwparams1 & DWC3_GHWPARAMS1_ENDBC);
|
|
|
|
|
|
|
|
|
|
sel = dwc->dbg_lsp_select;
|
|
|
|
|
if (sel == DWC3_LSP_MUX_UNSELECTED) {
|
|
|
|
|
seq_puts(s, "Write LSP selection to print for host\n");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
reg = DWC3_GDBGLSPMUX_HOSTSELECT(sel);
|
|
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
|
|
|
|
|
val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
|
|
|
|
|
seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", sel, val);
|
|
|
|
|
|
|
|
|
|
if (dbc_enabled && sel < 256) {
|
|
|
|
|
reg |= DWC3_GDBGLSPMUX_ENDBC;
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
|
|
|
|
|
val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
|
|
|
|
|
seq_printf(s, "GDBGLSP_DBC[%d] = 0x%08x\n", sel, val);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dwc3_gadget_lsp(struct seq_file *s)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
int i;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
|
reg = DWC3_GDBGLSPMUX_DEVSELECT(i);
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
|
|
|
|
|
seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", i, reg);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_lsp_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned int current_mode;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
|
|
|
|
|
current_mode = DWC3_GSTS_CURMOD(reg);
|
|
|
|
|
|
|
|
|
|
switch (current_mode) {
|
|
|
|
|
case DWC3_GSTS_CURMOD_HOST:
|
|
|
|
|
dwc3_host_lsp(s);
|
|
|
|
|
break;
|
|
|
|
|
case DWC3_GSTS_CURMOD_DEVICE:
|
|
|
|
|
dwc3_gadget_lsp(s);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
seq_puts(s, "Mode is unknown, no LSP register printed\n");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_lsp_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_lsp_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_lsp_write(struct file *file, const char __user *ubuf,
|
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
char buf[32] = { 0 };
|
|
|
|
|
u32 sel;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
ret = kstrtouint(buf, 0, &sel);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
dwc->dbg_lsp_select = sel;
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_lsp_fops = {
|
|
|
|
|
.open = dwc3_lsp_open,
|
|
|
|
|
.write = dwc3_lsp_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2011-10-17 13:50:39 +08:00
|
|
|
static int dwc3_mode_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
switch (DWC3_GCTL_PRTCAP(reg)) {
|
|
|
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "host\n");
|
2011-10-17 13:50:39 +08:00
|
|
|
break;
|
|
|
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "device\n");
|
2011-10-17 13:50:39 +08:00
|
|
|
break;
|
|
|
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "otg\n");
|
2011-10-17 13:50:39 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
seq_printf(s, "UNKNOWN %08x\n", DWC3_GCTL_PRTCAP(reg));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_mode_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_mode_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_mode_write(struct file *file,
|
|
|
|
|
const char __user *ubuf, size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
2011-11-01 05:25:40 +08:00
|
|
|
u32 mode = 0;
|
2011-10-17 13:50:39 +08:00
|
|
|
char buf[32];
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
2020-07-22 17:02:55 +08:00
|
|
|
if (dwc->dr_mode != USB_DR_MODE_OTG)
|
|
|
|
|
return count;
|
|
|
|
|
|
2011-10-17 13:50:39 +08:00
|
|
|
if (!strncmp(buf, "host", 4))
|
2017-04-04 16:27:57 +08:00
|
|
|
mode = DWC3_GCTL_PRTCAP_HOST;
|
2011-10-17 13:50:39 +08:00
|
|
|
|
|
|
|
|
if (!strncmp(buf, "device", 6))
|
2017-04-04 16:27:57 +08:00
|
|
|
mode = DWC3_GCTL_PRTCAP_DEVICE;
|
2011-10-17 13:50:39 +08:00
|
|
|
|
|
|
|
|
if (!strncmp(buf, "otg", 3))
|
2017-04-04 16:27:57 +08:00
|
|
|
mode = DWC3_GCTL_PRTCAP_OTG;
|
2011-10-17 13:50:39 +08:00
|
|
|
|
2017-04-04 17:49:18 +08:00
|
|
|
dwc3_set_mode(dwc, mode);
|
|
|
|
|
|
2011-10-17 13:50:39 +08:00
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_mode_fops = {
|
|
|
|
|
.open = dwc3_mode_open,
|
|
|
|
|
.write = dwc3_mode_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2012-01-03 00:38:30 +08:00
|
|
|
static int dwc3_testmode_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
|
reg &= DWC3_DCTL_TSTCTRL_MASK;
|
|
|
|
|
reg >>= 1;
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
|
case 0:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "no test\n");
|
2012-01-03 00:38:30 +08:00
|
|
|
break;
|
2020-06-18 22:42:06 +08:00
|
|
|
case USB_TEST_J:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "test_j\n");
|
2012-01-03 00:38:30 +08:00
|
|
|
break;
|
2020-06-18 22:42:06 +08:00
|
|
|
case USB_TEST_K:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "test_k\n");
|
2012-01-03 00:38:30 +08:00
|
|
|
break;
|
2020-06-18 22:42:06 +08:00
|
|
|
case USB_TEST_SE0_NAK:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "test_se0_nak\n");
|
2012-01-03 00:38:30 +08:00
|
|
|
break;
|
2020-06-18 22:42:06 +08:00
|
|
|
case USB_TEST_PACKET:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "test_packet\n");
|
2012-01-03 00:38:30 +08:00
|
|
|
break;
|
2020-06-18 22:42:06 +08:00
|
|
|
case USB_TEST_FORCE_ENABLE:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "test_force_enable\n");
|
2012-01-03 00:38:30 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
seq_printf(s, "UNKNOWN %d\n", reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_testmode_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_testmode_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_testmode_write(struct file *file,
|
|
|
|
|
const char __user *ubuf, size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 testmode = 0;
|
|
|
|
|
char buf[32];
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
if (!strncmp(buf, "test_j", 6))
|
2020-06-18 22:42:06 +08:00
|
|
|
testmode = USB_TEST_J;
|
2012-01-03 00:38:30 +08:00
|
|
|
else if (!strncmp(buf, "test_k", 6))
|
2020-06-18 22:42:06 +08:00
|
|
|
testmode = USB_TEST_K;
|
2012-02-10 18:14:53 +08:00
|
|
|
else if (!strncmp(buf, "test_se0_nak", 12))
|
2020-06-18 22:42:06 +08:00
|
|
|
testmode = USB_TEST_SE0_NAK;
|
2012-02-10 18:14:53 +08:00
|
|
|
else if (!strncmp(buf, "test_packet", 11))
|
2020-06-18 22:42:06 +08:00
|
|
|
testmode = USB_TEST_PACKET;
|
2012-02-10 18:14:53 +08:00
|
|
|
else if (!strncmp(buf, "test_force_enable", 17))
|
2020-06-18 22:42:06 +08:00
|
|
|
testmode = USB_TEST_FORCE_ENABLE;
|
2012-01-03 00:38:30 +08:00
|
|
|
else
|
|
|
|
|
testmode = 0;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
dwc3_gadget_set_test_mode(dwc, testmode);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_testmode_fops = {
|
|
|
|
|
.open = dwc3_testmode_open,
|
|
|
|
|
.write = dwc3_testmode_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2012-01-03 01:25:16 +08:00
|
|
|
static int dwc3_link_state_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
enum dwc3_link_state state;
|
|
|
|
|
u32 reg;
|
2018-11-08 09:55:19 +08:00
|
|
|
u8 speed;
|
2012-01-03 01:25:16 +08:00
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2018-11-08 09:56:23 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
|
|
|
|
|
if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {
|
|
|
|
|
seq_puts(s, "Not available\n");
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-01-03 01:25:16 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
|
state = DWC3_DSTS_USBLNKST(reg);
|
2018-11-08 09:55:19 +08:00
|
|
|
speed = reg & DWC3_DSTS_CONNECTSPD;
|
2012-01-03 01:25:16 +08:00
|
|
|
|
2018-11-08 09:55:19 +08:00
|
|
|
seq_printf(s, "%s\n", (speed >= DWC3_DSTS_SUPERSPEED) ?
|
|
|
|
|
dwc3_gadget_link_string(state) :
|
|
|
|
|
dwc3_gadget_hs_link_string(state));
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2012-01-03 01:25:16 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_link_state_open(struct inode *inode, struct file *file)
|
|
|
|
|
{
|
|
|
|
|
return single_open(file, dwc3_link_state_show, inode->i_private);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t dwc3_link_state_write(struct file *file,
|
|
|
|
|
const char __user *ubuf, size_t count, loff_t *ppos)
|
|
|
|
|
{
|
|
|
|
|
struct seq_file *s = file->private_data;
|
|
|
|
|
struct dwc3 *dwc = s->private;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
enum dwc3_link_state state = 0;
|
|
|
|
|
char buf[32];
|
2018-11-08 09:55:19 +08:00
|
|
|
u32 reg;
|
|
|
|
|
u8 speed;
|
2012-01-03 01:25:16 +08:00
|
|
|
|
|
|
|
|
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
if (!strncmp(buf, "SS.Disabled", 11))
|
|
|
|
|
state = DWC3_LINK_STATE_SS_DIS;
|
|
|
|
|
else if (!strncmp(buf, "Rx.Detect", 9))
|
|
|
|
|
state = DWC3_LINK_STATE_RX_DET;
|
|
|
|
|
else if (!strncmp(buf, "SS.Inactive", 11))
|
|
|
|
|
state = DWC3_LINK_STATE_SS_INACT;
|
|
|
|
|
else if (!strncmp(buf, "Recovery", 8))
|
|
|
|
|
state = DWC3_LINK_STATE_RECOV;
|
|
|
|
|
else if (!strncmp(buf, "Compliance", 10))
|
|
|
|
|
state = DWC3_LINK_STATE_CMPLY;
|
|
|
|
|
else if (!strncmp(buf, "Loopback", 8))
|
|
|
|
|
state = DWC3_LINK_STATE_LPBK;
|
|
|
|
|
else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2018-11-08 09:56:23 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
|
|
|
|
|
if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-08 09:55:19 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
|
speed = reg & DWC3_DSTS_CONNECTSPD;
|
|
|
|
|
|
|
|
|
|
if (speed < DWC3_DSTS_SUPERSPEED &&
|
|
|
|
|
state != DWC3_LINK_STATE_RECOV) {
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2012-01-03 01:25:16 +08:00
|
|
|
dwc3_gadget_set_link_state(dwc, state);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations dwc3_link_state_fops = {
|
|
|
|
|
.open = dwc3_link_state_open,
|
|
|
|
|
.write = dwc3_link_state_write,
|
|
|
|
|
.read = seq_read,
|
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
|
.release = single_release,
|
|
|
|
|
};
|
|
|
|
|
|
2016-04-14 19:53:44 +08:00
|
|
|
struct dwc3_ep_file_map {
|
2018-02-15 19:03:38 +08:00
|
|
|
const char name[25];
|
|
|
|
|
const struct file_operations *const fops;
|
2016-04-14 19:53:44 +08:00
|
|
|
};
|
|
|
|
|
|
2018-11-08 09:55:00 +08:00
|
|
|
static int dwc3_tx_fifo_size_show(struct seq_file *s, void *unused)
|
2016-04-14 19:53:44 +08:00
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
2021-03-28 08:54:01 +08:00
|
|
|
u32 mdwidth;
|
2016-04-14 19:53:44 +08:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2018-11-08 09:55:00 +08:00
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_TXFIFO);
|
2018-11-08 09:55:06 +08:00
|
|
|
|
|
|
|
|
/* Convert to bytes */
|
2021-03-28 08:54:01 +08:00
|
|
|
mdwidth = dwc3_mdwidth(dwc);
|
2020-04-12 10:20:07 +08:00
|
|
|
|
|
|
|
|
val *= mdwidth;
|
2018-11-08 09:55:06 +08:00
|
|
|
val >>= 3;
|
2016-04-14 19:53:44 +08:00
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-08 09:55:00 +08:00
|
|
|
static int dwc3_rx_fifo_size_show(struct seq_file *s, void *unused)
|
2016-04-14 19:53:44 +08:00
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
2021-03-28 08:54:01 +08:00
|
|
|
u32 mdwidth;
|
2016-04-14 19:53:44 +08:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2018-11-08 09:55:00 +08:00
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_RXFIFO);
|
2018-11-08 09:55:06 +08:00
|
|
|
|
|
|
|
|
/* Convert to bytes */
|
2021-03-28 08:54:01 +08:00
|
|
|
mdwidth = dwc3_mdwidth(dwc);
|
2020-04-12 10:20:07 +08:00
|
|
|
|
|
|
|
|
val *= mdwidth;
|
2018-11-08 09:55:06 +08:00
|
|
|
val >>= 3;
|
2016-04-14 19:53:44 +08:00
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_tx_request_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_TXREQQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_rx_request_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_RXREQQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_rx_info_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_RXINFOQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_descriptor_fetch_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_DESCFETCHQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwc3_event_queue_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
val = dwc3_core_fifo_space(dep, DWC3_EVENTQ);
|
|
|
|
|
seq_printf(s, "%u\n", val);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-15 19:03:38 +08:00
|
|
|
static int dwc3_transfer_type_show(struct seq_file *s, void *unused)
|
2016-04-14 19:53:44 +08:00
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2020-08-13 14:22:34 +08:00
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED) || !dep->endpoint.desc) {
|
|
|
|
|
seq_puts(s, "--\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (usb_endpoint_type(dep->endpoint.desc)) {
|
|
|
|
|
case USB_ENDPOINT_XFER_CONTROL:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "control\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
break;
|
|
|
|
|
case USB_ENDPOINT_XFER_ISOC:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "isochronous\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
break;
|
|
|
|
|
case USB_ENDPOINT_XFER_BULK:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "bulk\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
break;
|
|
|
|
|
case USB_ENDPOINT_XFER_INT:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "interrupt\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "--\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-15 19:03:38 +08:00
|
|
|
static int dwc3_trb_ring_show(struct seq_file *s, void *unused)
|
2016-04-14 19:53:44 +08:00
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
if (dep->number <= 1) {
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "--\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
2020-08-13 14:22:34 +08:00
|
|
|
seq_puts(s, "buffer_addr,size,type,ioc,isp_imi,csp,chn,lst,hwo\n");
|
2016-04-14 19:53:44 +08:00
|
|
|
|
|
|
|
|
for (i = 0; i < DWC3_TRB_NUM; i++) {
|
|
|
|
|
struct dwc3_trb *trb = &dep->trb_pool[i];
|
2017-03-31 19:44:09 +08:00
|
|
|
unsigned int type = DWC3_TRBCTL_TYPE(trb->ctrl);
|
2016-04-14 19:53:44 +08:00
|
|
|
|
2017-04-20 20:21:27 +08:00
|
|
|
seq_printf(s, "%08x%08x,%d,%s,%d,%d,%d,%d,%d,%d %c%c\n",
|
2016-04-14 19:53:44 +08:00
|
|
|
trb->bph, trb->bpl, trb->size,
|
2017-03-31 19:44:09 +08:00
|
|
|
dwc3_trb_type_string(type),
|
2016-04-14 19:53:44 +08:00
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_IOC),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_ISP_IMI),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_CSP),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_CHN),
|
|
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_LST),
|
2017-04-20 20:21:27 +08:00
|
|
|
!!(trb->ctrl & DWC3_TRB_CTRL_HWO),
|
|
|
|
|
dep->trb_enqueue == i ? 'E' : ' ',
|
|
|
|
|
dep->trb_dequeue == i ? 'D' : ' ');
|
2016-04-14 19:53:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-08 09:55:13 +08:00
|
|
|
static int dwc3_ep_info_register_show(struct seq_file *s, void *unused)
|
|
|
|
|
{
|
|
|
|
|
struct dwc3_ep *dep = s->private;
|
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u64 ep_info;
|
|
|
|
|
u32 lower_32_bits;
|
|
|
|
|
u32 upper_32_bits;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
reg = DWC3_GDBGLSPMUX_EPSELECT(dep->number);
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
|
|
|
|
|
|
|
|
|
|
lower_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO0);
|
|
|
|
|
upper_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1);
|
|
|
|
|
|
|
|
|
|
ep_info = ((u64)upper_32_bits << 32) | lower_32_bits;
|
|
|
|
|
seq_printf(s, "0x%016llx\n", ep_info);
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-08 09:55:00 +08:00
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_tx_fifo_size);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_rx_fifo_size);
|
2018-02-15 19:03:38 +08:00
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_tx_request_queue);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_rx_request_queue);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_rx_info_queue);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_descriptor_fetch_queue);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_event_queue);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_transfer_type);
|
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_trb_ring);
|
2018-11-08 09:55:13 +08:00
|
|
|
DEFINE_SHOW_ATTRIBUTE(dwc3_ep_info_register);
|
2018-02-15 19:03:38 +08:00
|
|
|
|
|
|
|
|
static const struct dwc3_ep_file_map dwc3_ep_file_map[] = {
|
2018-11-08 09:55:00 +08:00
|
|
|
{ "tx_fifo_size", &dwc3_tx_fifo_size_fops, },
|
|
|
|
|
{ "rx_fifo_size", &dwc3_rx_fifo_size_fops, },
|
2018-02-15 19:03:38 +08:00
|
|
|
{ "tx_request_queue", &dwc3_tx_request_queue_fops, },
|
|
|
|
|
{ "rx_request_queue", &dwc3_rx_request_queue_fops, },
|
|
|
|
|
{ "rx_info_queue", &dwc3_rx_info_queue_fops, },
|
|
|
|
|
{ "descriptor_fetch_queue", &dwc3_descriptor_fetch_queue_fops, },
|
|
|
|
|
{ "event_queue", &dwc3_event_queue_fops, },
|
|
|
|
|
{ "transfer_type", &dwc3_transfer_type_fops, },
|
|
|
|
|
{ "trb_ring", &dwc3_trb_ring_fops, },
|
2018-11-08 09:55:13 +08:00
|
|
|
{ "GDBGEPINFO", &dwc3_ep_info_register_fops, },
|
2016-04-14 19:53:44 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void dwc3_debugfs_create_endpoint_files(struct dwc3_ep *dep,
|
|
|
|
|
struct dentry *parent)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
2018-02-15 19:03:38 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(dwc3_ep_file_map); i++) {
|
|
|
|
|
const struct file_operations *fops = dwc3_ep_file_map[i].fops;
|
|
|
|
|
const char *name = dwc3_ep_file_map[i].name;
|
|
|
|
|
|
2020-08-13 14:22:34 +08:00
|
|
|
debugfs_create_file(name, 0444, parent, dep, fops);
|
2018-02-15 19:03:38 +08:00
|
|
|
}
|
2016-04-14 19:53:44 +08:00
|
|
|
}
|
|
|
|
|
|
usb: dwc3: debugfs: Add and remove endpoint dirs dynamically
The DWC3 DebugFS directory and files are currently created once
during probe. This includes creation of subdirectories for each
of the gadget's endpoints. This works fine for peripheral-only
controllers, as dwc3_core_init_mode() calls dwc3_gadget_init()
just prior to calling dwc3_debugfs_init().
However, for dual-role controllers, dwc3_core_init_mode() will
instead call dwc3_drd_init() which is problematic in a few ways.
First, the initial state must be determined, then dwc3_set_mode()
will have to schedule drd_work and by then dwc3_debugfs_init()
could have already been invoked. Even if the initial mode is
peripheral, dwc3_gadget_init() happens after the DebugFS files
are created, and worse so if the initial state is host and the
controller switches to peripheral much later. And secondly,
even if the gadget endpoints' debug entries were successfully
created, if the controller exits peripheral mode, its dwc3_eps
are freed so the debug files would now hold stale references.
So it is best if the DebugFS endpoint entries are created and
removed dynamically at the same time the underlying dwc3_eps are.
Do this by calling dwc3_debugfs_create_endpoint_dir() as each
endpoint is created, and conversely remove the DebugFS entry when
the endpoint is freed.
Fixes: 41ce1456e1db ("usb: dwc3: core: make dwc3_set_mode() work properly")
Reviewed-by: Peter Chen <peter.chen@kernel.org>
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Link: https://lore.kernel.org/r/20210529192932.22912-1-jackp@codeaurora.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-30 03:29:32 +08:00
|
|
|
void dwc3_debugfs_create_endpoint_dir(struct dwc3_ep *dep)
|
2016-04-14 19:53:44 +08:00
|
|
|
{
|
|
|
|
|
struct dentry *dir;
|
2021-06-09 17:39:24 +08:00
|
|
|
struct dentry *root;
|
2016-04-14 19:53:44 +08:00
|
|
|
|
2021-06-09 17:39:24 +08:00
|
|
|
root = debugfs_lookup(dev_name(dep->dwc->dev), usb_debug_root);
|
|
|
|
|
dir = debugfs_create_dir(dep->name, root);
|
2016-04-14 19:53:44 +08:00
|
|
|
dwc3_debugfs_create_endpoint_files(dep, dir);
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-12 19:10:18 +08:00
|
|
|
void dwc3_debugfs_init(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
|
struct dentry *root;
|
|
|
|
|
|
2013-01-18 16:21:34 +08:00
|
|
|
dwc->regset = kzalloc(sizeof(*dwc->regset), GFP_KERNEL);
|
2018-05-29 23:31:01 +08:00
|
|
|
if (!dwc->regset)
|
2016-04-12 19:10:18 +08:00
|
|
|
return;
|
2013-01-18 16:21:34 +08:00
|
|
|
|
2018-11-08 09:55:13 +08:00
|
|
|
dwc->dbg_lsp_select = DWC3_LSP_MUX_UNSELECTED;
|
|
|
|
|
|
2013-01-18 16:21:34 +08:00
|
|
|
dwc->regset->regs = dwc3_regs;
|
|
|
|
|
dwc->regset->nregs = ARRAY_SIZE(dwc3_regs);
|
2016-04-12 21:53:39 +08:00
|
|
|
dwc->regset->base = dwc->regs - DWC3_GLOBALS_REGS_START;
|
2013-01-18 16:21:34 +08:00
|
|
|
|
2019-11-12 14:51:50 +08:00
|
|
|
root = debugfs_create_dir(dev_name(dwc->dev), usb_debug_root);
|
2020-08-13 14:22:34 +08:00
|
|
|
debugfs_create_regset32("regdump", 0444, root, dwc->regset);
|
|
|
|
|
debugfs_create_file("lsp_dump", 0644, root, dwc, &dwc3_lsp_fops);
|
2011-10-17 13:50:39 +08:00
|
|
|
|
2020-08-13 14:22:34 +08:00
|
|
|
if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE))
|
|
|
|
|
debugfs_create_file("mode", 0644, root, dwc,
|
2018-05-29 23:31:01 +08:00
|
|
|
&dwc3_mode_fops);
|
2011-10-17 13:50:39 +08:00
|
|
|
|
2013-02-22 22:24:49 +08:00
|
|
|
if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) ||
|
|
|
|
|
IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
|
2020-08-13 14:22:34 +08:00
|
|
|
debugfs_create_file("testmode", 0644, root, dwc,
|
|
|
|
|
&dwc3_testmode_fops);
|
|
|
|
|
debugfs_create_file("link_state", 0644, root, dwc,
|
2018-05-29 23:31:01 +08:00
|
|
|
&dwc3_link_state_fops);
|
2016-04-12 19:10:18 +08:00
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
2012-11-20 02:26:20 +08:00
|
|
|
void dwc3_debugfs_exit(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2021-06-09 17:39:24 +08:00
|
|
|
debugfs_remove(debugfs_lookup(dev_name(dwc->dev), usb_debug_root));
|
2016-04-12 16:24:34 +08:00
|
|
|
kfree(dwc->regset);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|