License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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# SPDX-License-Identifier: GPL-2.0
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2012-08-22 16:40:02 +08:00
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#
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# Bus Devices
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#
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menu "Bus devices"
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2015-02-05 18:11:24 +08:00
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config ARM_CCI
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2015-04-04 04:38:43 +08:00
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bool
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config ARM_CCI400_COMMON
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bool
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select ARM_CCI
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config ARM_CCI400_PORT_CTRL
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bool
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2015-02-05 18:11:24 +08:00
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depends on ARM && OF && CPU_V7
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2015-04-04 04:38:43 +08:00
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select ARM_CCI400_COMMON
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2015-02-05 18:11:24 +08:00
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help
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2015-04-04 04:38:43 +08:00
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Low level power management driver for CCI400 cache coherent
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interconnect for ARM platforms.
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2015-02-05 18:11:24 +08:00
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2020-02-13 20:41:23 +08:00
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config ARM_INTEGRATOR_LM
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bool "ARM Integrator Logic Module bus"
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depends on HAS_IOMEM
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depends on ARCH_INTEGRATOR || COMPILE_TEST
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default ARCH_INTEGRATOR
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help
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Say y here to enable support for the ARM Logic Module bus
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found on the ARM Integrator AP (Application Platform)
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2014-05-20 04:05:59 +08:00
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config BRCMSTB_GISB_ARB
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2021-09-25 03:10:34 +08:00
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tristate "Broadcom STB GISB bus arbiter"
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2017-03-30 08:29:13 +08:00
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depends on ARM || ARM64 || MIPS
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2016-04-17 04:46:14 +08:00
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default ARCH_BRCMSTB || BMIPS_GENERIC
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2014-05-20 04:05:59 +08:00
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help
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Driver for the Broadcom Set Top Box System-on-a-chip internal bus
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arbiter. This driver provides timeout and target abort error handling
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and internal bus master decoding.
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2020-05-26 20:59:27 +08:00
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config BT1_APB
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2020-05-29 03:31:12 +08:00
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bool "Baikal-T1 APB-bus driver"
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2020-05-26 20:59:27 +08:00
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depends on MIPS_BAIKAL_T1 || COMPILE_TEST
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select REGMAP_MMIO
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help
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Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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IO requests are routed to this bus by means of the DW AMBA 3 AXI
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Interconnect. In case of any APB protocol collisions, slave device
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not responding on timeout an IRQ is raised with an erroneous address
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reported to the APB terminator (APB Errors Handler Block). This
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driver provides the interrupt handler to detect the erroneous
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address, prints an error message about the address fault, updates an
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errors counter. The counter and the APB-bus operations timeout can be
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accessed via corresponding sysfs nodes.
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2020-05-26 20:59:26 +08:00
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config BT1_AXI
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2020-05-29 03:31:13 +08:00
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bool "Baikal-T1 AXI-bus driver"
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2020-05-26 20:59:26 +08:00
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depends on MIPS_BAIKAL_T1 || COMPILE_TEST
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select MFD_SYSCON
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help
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AXI3-bus is the main communication bus connecting all high-speed
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peripheral IP-cores with RAM controller and with MIPS P5600 cores on
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Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
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Interconnect (so called AXI Main Interconnect) routing IO requests
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from one SoC block to another. This driver provides a way to detect
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any bus protocol errors and device not responding situations by
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means of an embedded on top of the interconnect errors handler
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block (EHB). AXI Interconnect QoS arbitration tuning is currently
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unsupported.
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bus: Add support for Moxtet bus
On the Turris Mox router different modules can be connected to the main
CPU board: currently a module with a SFP cage, a module with MiniPCIe
connector, a PCIe pass-through MiniPCIe connector module, a 4-port
switch module, an 8-port switch module, and a 4-port USB3 module.
For example:
[CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]
Each of this modules has an input and output shift register, and these
are connected via SPI to the CPU board.
Via SPI we are able to discover which modules are connected, in which
order, and we can also read some information about the modules (eg.
their interrupt status), and configure them.
From each module 8 bits can be read (of which low 4 bits identify the
module) and 8 bits can be written.
For example from the module with a SFP cage we can read the LOS,
TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and
RATE-SELECT signals.
This driver creates a new bus type, called "moxtet". For each Mox module
it finds via SPI, it creates a new device on the moxtet bus so that
drivers can be written for them.
It also implements a virtual interrupt controller for the modules which
send their interrupt status over the SPI shift register. These modules
do this in addition to sending their interrupt status via the shared
interrupt line. When the shared interrupt is triggered, we read from the
shift register and handle IRQs for all devices which are in interrupt.
The topology of how Mox modules are connected can then be read by
listing /sys/bus/moxtet/devices.
Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.cz
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-13 00:11:14 +08:00
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config MOXTET
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tristate "CZ.NIC Turris Mox module configuration bus"
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depends on SPI_MASTER && OF
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help
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Say yes here to add support for the module configuration bus found
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on CZ.NIC's Turris Mox. This is needed for the ability to discover
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the order in which the modules are connected and to get/set some of
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their settings. For example the GPIOs on Mox SFP module are
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configured through this bus.
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2018-03-22 06:23:02 +08:00
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config HISILICON_LPC
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bool "Support for ISA I/O space on HiSilicon Hip06/7"
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2021-01-18 19:45:46 +08:00
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depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC)
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2019-11-05 01:22:18 +08:00
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depends on HAS_IOMEM
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select INDIRECT_PIO if ARM64
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2018-03-22 06:23:02 +08:00
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help
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Driver to enable I/O access to devices attached to the Low Pin
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Count bus on the HiSilicon Hip06/7 SoC.
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2013-05-28 14:20:07 +08:00
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config IMX_WEIM
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bool "Freescale EIM DRIVER"
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depends on ARCH_MXC
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help
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2013-06-29 12:27:54 +08:00
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Driver for i.MX WEIM controller.
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2013-05-28 14:20:07 +08:00
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The WEIM(Wireless External Interface Module) works like a bus.
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You can attach many different devices on it, such as NOR, onenand.
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2021-07-16 07:53:34 +08:00
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config INTEL_IXP4XX_EB
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bool "Intel IXP4xx expansion bus interface driver"
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depends on HAS_IOMEM
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depends on ARCH_IXP4XX || COMPILE_TEST
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default ARCH_IXP4XX
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select MFD_SYSCON
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help
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Driver for the Intel IXP4xx expansion bus interface. The driver is
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needed to set up various chip select configuration parameters before
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devices on the expansion bus can be discovered.
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2015-03-25 23:39:50 +08:00
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config MIPS_CDMM
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bool "MIPS Common Device Memory Map (CDMM) Driver"
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2020-07-14 20:57:51 +08:00
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depends on CPU_MIPSR2 || CPU_MIPSR5
|
2015-03-25 23:39:50 +08:00
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help
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Driver needed for the MIPS Common Device Memory Map bus in MIPS
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cores. This bus is for per-CPU tightly coupled devices such as the
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Fast Debug Channel (FDC).
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For this to work, either your bootloader needs to enable the CDMM
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region at an unused physical address on the boot CPU, or else your
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platform code needs to implement mips_cdmm_phys_base() (see
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asm/cdmm.h).
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bus: introduce an Marvell EBU MBus driver
The Marvell EBU SoCs have a configurable physical address space
layout: the physical ranges of memory used to address PCI(e)
interfaces, NOR flashes, SRAM and various other types of memory are
configurable by software, through a mechanism of so-called 'address
decoding windows'.
This new driver mvebu-mbus consolidates the existing code to address
the configuration of these memory ranges, which is spread into
mach-mvebu, mach-orion5x, mach-mv78xx0, mach-dove and mach-kirkwood.
Following patches convert each Marvell EBU SoC family to use this
driver, therefore removing the old code that was configuring the
address decoding windows.
It is worth mentioning that the MVEBU_MBUS Kconfig option is
intentionally added as a blind option. The new driver implements and
exports the mv_mbus_dram_info() function, which is used by various
Marvell drivers throughout the tree to get access to window
configuration parameters that they require. This function is also
implemented in arch/arm/plat-orion/addr-map.c, which ultimately gets
removed at the end of this patch series. So, in order to preserve
bisectability, we want to ensure that *either* this new driver, *or*
the legacy code in plat-orion/addr-map.c gets compiled in.
By making MVEBU_MBUS a blind option, we are sure that only a platform
that does 'select MVEBU_MBUS' will get this new driver compiled
in. Therefore, throughout the next patches that convert the Marvell
sub-architectures one after the other to this new driver, we add the
'select MVEBU_MBUS' and also ensure to remove plat-orion/addr-map.c
from the build for this specific sub-architecture. This ensures that
bisectability is preserved.
Ealier versions of this driver had a DT binding, but since those were
not yet agreed upon, they were removed. The driver still uses
of_device_id to find the SoC specific details according to the string
passed to mvebu_mbus_init(). The plan is to re-introduce a proper DT
binding as a followup set of patches.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-03-22 00:59:14 +08:00
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config MVEBU_MBUS
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bool
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depends on PLAT_ORION
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help
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Driver needed for the MBus configuration on Marvell EBU SoCs
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(Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
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2012-09-14 17:20:34 +08:00
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config OMAP_INTERCONNECT
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tristate "OMAP INTERCONNECT DRIVER"
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depends on ARCH_OMAP2PLUS
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help
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Driver to enable OMAP interconnect error handling driver.
|
2012-07-13 22:55:52 +08:00
|
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|
2015-02-05 18:11:24 +08:00
|
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config OMAP_OCP2SCP
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tristate "OMAP OCP2SCP DRIVER"
|
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depends on ARCH_OMAP2PLUS
|
2012-07-13 22:55:52 +08:00
|
|
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help
|
2015-02-05 18:11:24 +08:00
|
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Driver to enable ocp2scp module which transforms ocp interface
|
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protocol to scp protocol. In OMAP4, USB PHY is connected via
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OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
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OCP2SCP.
|
mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-04-30 23:46:29 +08:00
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|
2016-07-08 06:11:02 +08:00
|
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config QCOM_EBI2
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|
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bool "Qualcomm External Bus Interface 2 (EBI2)"
|
2016-10-03 05:53:59 +08:00
|
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depends on HAS_IOMEM
|
2016-10-04 19:56:19 +08:00
|
|
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depends on ARCH_QCOM || COMPILE_TEST
|
2017-01-12 15:08:55 +08:00
|
|
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default ARCH_QCOM
|
2016-07-08 06:11:02 +08:00
|
|
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help
|
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Say y here to enable support for the Qualcomm External Bus
|
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Interface 2, which can be used to connect things like NAND Flash,
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SRAM, ethernet adapters, FPGAs and LCD displays.
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bus: add driver for initializing the SSC bus on (some) qcom SoCs
Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core)
block in the global address space. This bus (and the SSC block itself) is
present on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to Linux, and the resources
on this bus are indirectly accessed by communicating with a hexagon CPU
core residing in the SSC block. In this configuration, the hypervisor is
the one performing the bus initialization for the purposes of bringing
the hexagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
driver will initialize the bus.
In combination with drivers for resources on the SSC bus, this driver can
aid in debugging, and for example with a TLMM driver can be used to
directly access SSC-dedicated GPIO pins, removing the need to commit
to a particular usecase during hw design.
Finally, until open firmware for the hexagon core is available, this
approach allows for using sensors hooked up to SSC-dedicated GPIO pins
on mainline Linux simply by utilizing the existing in-tree drivers for
these sensors.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411072156.24451-5-michael.srba@seznam.cz
2022-04-11 15:21:55 +08:00
|
|
|
config QCOM_SSC_BLOCK_BUS
|
|
|
|
|
bool "Qualcomm SSC Block Bus Init Driver"
|
|
|
|
|
depends on ARCH_QCOM
|
|
|
|
|
help
|
|
|
|
|
Say y here to enable support for initializing the bus that connects
|
|
|
|
|
the SSC block's internal bus to the cNoC (configurantion NoC) on
|
|
|
|
|
(some) qcom SoCs.
|
|
|
|
|
The SSC (Snapdragon Sensor Core) block contains a gpio controller,
|
|
|
|
|
i2c/spi/uart controllers, a hexagon core, and a clock controller
|
|
|
|
|
which provides clocks for the above.
|
|
|
|
|
|
2018-06-22 20:45:36 +08:00
|
|
|
config SUN50I_DE2_BUS
|
|
|
|
|
bool "Allwinner A64 DE2 Bus Driver"
|
|
|
|
|
default ARM64
|
|
|
|
|
depends on ARCH_SUNXI
|
|
|
|
|
select SUNXI_SRAM
|
|
|
|
|
help
|
|
|
|
|
Say y here to enable support for Allwinner A64 DE2 bus driver. It's
|
|
|
|
|
mostly transparent, but a SRAM region needs to be claimed in the SRAM
|
|
|
|
|
controller to make the all blocks in the DE2 part accessible.
|
|
|
|
|
|
2015-10-24 02:41:31 +08:00
|
|
|
config SUNXI_RSB
|
|
|
|
|
tristate "Allwinner sunXi Reduced Serial Bus Driver"
|
2017-08-12 13:40:41 +08:00
|
|
|
default MACH_SUN8I || MACH_SUN9I || ARM64
|
2015-10-24 02:41:31 +08:00
|
|
|
depends on ARCH_SUNXI
|
|
|
|
|
select REGMAP
|
|
|
|
|
help
|
|
|
|
|
Say y here to enable support for Allwinner's Reduced Serial Bus
|
|
|
|
|
(RSB) support. This controller is responsible for communicating
|
|
|
|
|
with various RSB based devices, such as AXP223, AXP8XX PMICs,
|
|
|
|
|
and AC100/AC200 ICs.
|
|
|
|
|
|
2016-06-17 20:40:32 +08:00
|
|
|
config TEGRA_ACONNECT
|
2016-06-30 23:07:05 +08:00
|
|
|
tristate "Tegra ACONNECT Bus Driver"
|
2016-06-17 20:40:32 +08:00
|
|
|
depends on ARCH_TEGRA_210_SOC
|
|
|
|
|
depends on OF && PM
|
|
|
|
|
help
|
|
|
|
|
Driver for the Tegra ACONNECT bus which is used to interface with
|
|
|
|
|
the devices inside the Audio Processing Engine (APE) for Tegra210.
|
|
|
|
|
|
2016-11-07 16:30:05 +08:00
|
|
|
config TEGRA_GMI
|
|
|
|
|
tristate "Tegra Generic Memory Interface bus driver"
|
|
|
|
|
depends on ARCH_TEGRA
|
|
|
|
|
help
|
|
|
|
|
Driver for the Tegra Generic Memory Interface bus which can be used
|
|
|
|
|
to attach devices such as NOR, UART, FPGA and more.
|
|
|
|
|
|
2019-09-02 06:58:22 +08:00
|
|
|
config TI_PWMSS
|
|
|
|
|
bool
|
2019-09-02 06:58:24 +08:00
|
|
|
default y if (ARCH_OMAP2PLUS) && (PWM_TIECAP || PWM_TIEHRPWM || TI_EQEP)
|
2019-09-02 06:58:22 +08:00
|
|
|
help
|
|
|
|
|
PWM Subsystem driver support for AM33xx SOC.
|
|
|
|
|
|
|
|
|
|
PWM submodules require PWM config space access from submodule
|
|
|
|
|
drivers and require common parent driver support.
|
|
|
|
|
|
2017-10-11 05:23:43 +08:00
|
|
|
config TI_SYSC
|
|
|
|
|
bool "TI sysc interconnect target module driver"
|
|
|
|
|
depends on ARCH_OMAP2PLUS
|
|
|
|
|
help
|
|
|
|
|
Generic driver for Texas Instruments interconnect target module
|
|
|
|
|
found on many TI SoCs.
|
|
|
|
|
|
2017-11-02 01:14:33 +08:00
|
|
|
config TS_NBUS
|
|
|
|
|
tristate "Technologic Systems NBUS Driver"
|
|
|
|
|
depends on SOC_IMX28
|
|
|
|
|
depends on OF_GPIO && PWM
|
|
|
|
|
help
|
|
|
|
|
Driver for the Technologic Systems NBUS which is used to interface
|
|
|
|
|
with the peripherals in the FPGA of the TS-4600 SoM.
|
|
|
|
|
|
2015-12-09 14:52:59 +08:00
|
|
|
config UNIPHIER_SYSTEM_BUS
|
2016-01-23 22:06:28 +08:00
|
|
|
tristate "UniPhier System Bus driver"
|
2015-12-09 14:52:59 +08:00
|
|
|
depends on ARCH_UNIPHIER && OF
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Support for UniPhier System Bus, a simple external bus. This is
|
|
|
|
|
needed to use on-board devices connected to UniPhier SoCs.
|
|
|
|
|
|
mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-04-30 23:46:29 +08:00
|
|
|
config VEXPRESS_CONFIG
|
2020-04-30 04:58:24 +08:00
|
|
|
tristate "Versatile Express configuration bus"
|
mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-04-30 23:46:29 +08:00
|
|
|
default y if ARCH_VEXPRESS
|
|
|
|
|
depends on ARM || ARM64
|
2014-05-26 23:25:22 +08:00
|
|
|
depends on OF
|
mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-04-30 23:46:29 +08:00
|
|
|
select REGMAP
|
|
|
|
|
help
|
|
|
|
|
Platform configuration infrastructure for the ARM Ltd.
|
|
|
|
|
Versatile Express.
|
2016-10-31 22:45:35 +08:00
|
|
|
|
|
|
|
|
config DA8XX_MSTPRI
|
|
|
|
|
bool "TI da8xx master peripheral priority driver"
|
|
|
|
|
depends on ARCH_DAVINCI_DA8XX
|
|
|
|
|
help
|
|
|
|
|
Driver for Texas Instruments da8xx master peripheral priority
|
|
|
|
|
configuration. Allows to adjust the priorities of all master
|
|
|
|
|
peripherals.
|
|
|
|
|
|
2018-02-05 22:07:42 +08:00
|
|
|
source "drivers/bus/fsl-mc/Kconfig"
|
2020-02-20 17:58:40 +08:00
|
|
|
source "drivers/bus/mhi/Kconfig"
|
2018-02-05 22:07:42 +08:00
|
|
|
|
2012-08-22 16:40:02 +08:00
|
|
|
endmenu
|