2019-05-29 22:18:02 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-07-18 00:33:40 +08:00
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/*
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* intel_pt_decoder.h: Intel Processor Trace support
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* Copyright (c) 2013-2014, Intel Corporation.
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*/
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#ifndef INCLUDE__INTEL_PT_DECODER_H__
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#define INCLUDE__INTEL_PT_DECODER_H__
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include "intel-pt-insn-decoder.h"
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#define INTEL_PT_IN_TX (1 << 0)
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#define INTEL_PT_ABORT_TX (1 << 1)
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#define INTEL_PT_ASYNC (1 << 2)
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2017-05-26 16:17:14 +08:00
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#define INTEL_PT_FUP_IP (1 << 3)
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2015-07-18 00:33:40 +08:00
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enum intel_pt_sample_type {
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INTEL_PT_BRANCH = 1 << 0,
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INTEL_PT_INSTRUCTION = 1 << 1,
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INTEL_PT_TRANSACTION = 1 << 2,
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2017-05-26 16:17:14 +08:00
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INTEL_PT_PTW = 1 << 3,
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INTEL_PT_MWAIT_OP = 1 << 4,
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INTEL_PT_PWR_ENTRY = 1 << 5,
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INTEL_PT_EX_STOP = 1 << 6,
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INTEL_PT_PWR_EXIT = 1 << 7,
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2017-05-26 16:17:16 +08:00
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INTEL_PT_CBR_CHG = 1 << 8,
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2018-09-20 21:00:47 +08:00
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INTEL_PT_TRACE_BEGIN = 1 << 9,
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INTEL_PT_TRACE_END = 1 << 10,
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2019-06-10 15:27:55 +08:00
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INTEL_PT_BLK_ITEMS = 1 << 11,
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2015-07-18 00:33:40 +08:00
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};
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enum intel_pt_period_type {
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INTEL_PT_PERIOD_NONE,
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INTEL_PT_PERIOD_INSTRUCTIONS,
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INTEL_PT_PERIOD_TICKS,
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2015-07-18 00:33:55 +08:00
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INTEL_PT_PERIOD_MTC,
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2015-07-18 00:33:40 +08:00
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};
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enum {
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INTEL_PT_ERR_NOMEM = 1,
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INTEL_PT_ERR_INTERN,
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INTEL_PT_ERR_BADPKT,
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INTEL_PT_ERR_NODATA,
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INTEL_PT_ERR_NOINSN,
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INTEL_PT_ERR_MISMAT,
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INTEL_PT_ERR_OVR,
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INTEL_PT_ERR_LOST,
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INTEL_PT_ERR_UNK,
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INTEL_PT_ERR_NELOOP,
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INTEL_PT_ERR_MAX,
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};
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2018-05-31 18:23:45 +08:00
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enum intel_pt_param_flags {
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/*
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* FUP packet can contain next linear instruction pointer instead of
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* current linear instruction pointer.
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*/
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INTEL_PT_FUP_WITH_NLIP = 1 << 0,
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};
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2019-06-10 15:27:55 +08:00
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enum intel_pt_blk_type {
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INTEL_PT_GP_REGS = 1,
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INTEL_PT_PEBS_BASIC = 4,
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INTEL_PT_PEBS_MEM = 5,
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INTEL_PT_LBR_0 = 8,
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INTEL_PT_LBR_1 = 9,
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INTEL_PT_LBR_2 = 10,
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INTEL_PT_XMM = 16,
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INTEL_PT_BLK_TYPE_MAX
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};
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/*
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* The block type numbers are not sequential but here they are given sequential
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* positions to avoid wasting space for array placement.
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*/
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enum intel_pt_blk_type_pos {
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INTEL_PT_GP_REGS_POS,
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INTEL_PT_PEBS_BASIC_POS,
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INTEL_PT_PEBS_MEM_POS,
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INTEL_PT_LBR_0_POS,
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INTEL_PT_LBR_1_POS,
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INTEL_PT_LBR_2_POS,
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INTEL_PT_XMM_POS,
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INTEL_PT_BLK_TYPE_CNT
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};
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/* Get the array position for a block type */
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static inline int intel_pt_blk_type_pos(enum intel_pt_blk_type blk_type)
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{
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#define BLK_TYPE(bt) [INTEL_PT_##bt] = INTEL_PT_##bt##_POS + 1
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const int map[INTEL_PT_BLK_TYPE_MAX] = {
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BLK_TYPE(GP_REGS),
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BLK_TYPE(PEBS_BASIC),
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BLK_TYPE(PEBS_MEM),
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BLK_TYPE(LBR_0),
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BLK_TYPE(LBR_1),
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BLK_TYPE(LBR_2),
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BLK_TYPE(XMM),
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};
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#undef BLK_TYPE
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return blk_type < INTEL_PT_BLK_TYPE_MAX ? map[blk_type] - 1 : -1;
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}
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#define INTEL_PT_BLK_ITEM_ID_CNT 32
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/*
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* Use unions so that the block items can be accessed by name or by array index.
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* There is an array of 32-bit masks for each block type, which indicate which
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* values are present. Then arrays of 32 64-bit values for each block type.
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*/
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struct intel_pt_blk_items {
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union {
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uint32_t mask[INTEL_PT_BLK_TYPE_CNT];
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struct {
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uint32_t has_rflags:1;
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uint32_t has_rip:1;
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uint32_t has_rax:1;
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uint32_t has_rcx:1;
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uint32_t has_rdx:1;
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uint32_t has_rbx:1;
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uint32_t has_rsp:1;
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uint32_t has_rbp:1;
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uint32_t has_rsi:1;
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uint32_t has_rdi:1;
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uint32_t has_r8:1;
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uint32_t has_r9:1;
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uint32_t has_r10:1;
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uint32_t has_r11:1;
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uint32_t has_r12:1;
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uint32_t has_r13:1;
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uint32_t has_r14:1;
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uint32_t has_r15:1;
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uint32_t has_unused_0:14;
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uint32_t has_ip:1;
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uint32_t has_applicable_counters:1;
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uint32_t has_timestamp:1;
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uint32_t has_unused_1:29;
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uint32_t has_mem_access_address:1;
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uint32_t has_mem_aux_info:1;
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uint32_t has_mem_access_latency:1;
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uint32_t has_tsx_aux_info:1;
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uint32_t has_unused_2:28;
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uint32_t has_lbr_0;
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uint32_t has_lbr_1;
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uint32_t has_lbr_2;
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uint32_t has_xmm;
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};
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};
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union {
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uint64_t val[INTEL_PT_BLK_TYPE_CNT][INTEL_PT_BLK_ITEM_ID_CNT];
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struct {
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struct {
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uint64_t rflags;
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uint64_t rip;
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uint64_t rax;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rbx;
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uint64_t rsp;
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uint64_t rbp;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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uint64_t unused_0[INTEL_PT_BLK_ITEM_ID_CNT - 18];
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};
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struct {
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uint64_t ip;
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uint64_t applicable_counters;
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uint64_t timestamp;
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uint64_t unused_1[INTEL_PT_BLK_ITEM_ID_CNT - 3];
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};
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struct {
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uint64_t mem_access_address;
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uint64_t mem_aux_info;
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uint64_t mem_access_latency;
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uint64_t tsx_aux_info;
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uint64_t unused_2[INTEL_PT_BLK_ITEM_ID_CNT - 4];
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};
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uint64_t lbr_0[INTEL_PT_BLK_ITEM_ID_CNT];
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uint64_t lbr_1[INTEL_PT_BLK_ITEM_ID_CNT];
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uint64_t lbr_2[INTEL_PT_BLK_ITEM_ID_CNT];
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uint64_t xmm[INTEL_PT_BLK_ITEM_ID_CNT];
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};
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};
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bool is_32_bit;
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};
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2015-07-18 00:33:40 +08:00
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struct intel_pt_state {
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enum intel_pt_sample_type type;
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int err;
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uint64_t from_ip;
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uint64_t to_ip;
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uint64_t cr3;
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2015-07-18 00:33:48 +08:00
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uint64_t tot_insn_cnt;
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2019-05-20 19:37:11 +08:00
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uint64_t tot_cyc_cnt;
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2015-07-18 00:33:40 +08:00
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uint64_t timestamp;
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uint64_t est_timestamp;
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uint64_t trace_nr;
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2017-05-26 16:17:14 +08:00
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uint64_t ptw_payload;
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uint64_t mwait_payload;
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uint64_t pwre_payload;
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uint64_t pwrx_payload;
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2017-05-26 16:17:16 +08:00
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uint64_t cbr_payload;
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2019-06-22 17:32:44 +08:00
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uint32_t cbr;
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2015-07-18 00:33:40 +08:00
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uint32_t flags;
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enum intel_pt_insn_op insn_op;
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int insn_len;
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2016-10-07 21:42:26 +08:00
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char insn[INTEL_PT_INSN_BUF_SZ];
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2019-06-10 15:27:55 +08:00
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struct intel_pt_blk_items items;
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2015-07-18 00:33:40 +08:00
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};
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struct intel_pt_insn;
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struct intel_pt_buffer {
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const unsigned char *buf;
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size_t len;
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bool consecutive;
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uint64_t ref_timestamp;
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uint64_t trace_nr;
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};
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2019-06-04 21:00:02 +08:00
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typedef int (*intel_pt_lookahead_cb_t)(struct intel_pt_buffer *, void *);
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2015-07-18 00:33:40 +08:00
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struct intel_pt_params {
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int (*get_trace)(struct intel_pt_buffer *buffer, void *data);
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int (*walk_insn)(struct intel_pt_insn *intel_pt_insn,
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uint64_t *insn_cnt_ptr, uint64_t *ip, uint64_t to_ip,
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uint64_t max_insn_cnt, void *data);
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2016-09-23 22:38:47 +08:00
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bool (*pgd_ip)(uint64_t ip, void *data);
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2019-06-04 21:00:02 +08:00
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int (*lookahead)(void *data, intel_pt_lookahead_cb_t cb, void *cb_data);
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2015-07-18 00:33:40 +08:00
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void *data;
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bool return_compression;
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2017-05-26 16:17:11 +08:00
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bool branch_enable;
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2015-07-18 00:33:40 +08:00
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uint64_t period;
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enum intel_pt_period_type period_type;
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unsigned max_non_turbo_ratio;
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2015-07-18 00:33:54 +08:00
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unsigned int mtc_period;
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uint32_t tsc_ctc_ratio_n;
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uint32_t tsc_ctc_ratio_d;
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2018-05-31 18:23:45 +08:00
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enum intel_pt_param_flags flags;
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2015-07-18 00:33:40 +08:00
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};
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struct intel_pt_decoder;
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struct intel_pt_decoder *intel_pt_decoder_new(struct intel_pt_params *params);
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void intel_pt_decoder_free(struct intel_pt_decoder *decoder);
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const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder);
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2019-06-04 21:00:06 +08:00
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int intel_pt_fast_forward(struct intel_pt_decoder *decoder, uint64_t timestamp);
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2015-07-18 00:33:40 +08:00
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unsigned char *intel_pt_find_overlap(unsigned char *buf_a, size_t len_a,
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unsigned char *buf_b, size_t len_b,
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2018-03-07 22:02:21 +08:00
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bool have_tsc, bool *consecutive);
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2015-07-18 00:33:40 +08:00
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int intel_pt__strerror(int code, char *buf, size_t buflen);
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#endif
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