2017-10-16 04:51:52 +08:00
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/*
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* ddbridge-ci.c: Digital Devices bridge CI (DuoFlex, CI Bridge) support
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*
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* Copyright (C) 2010-2017 Digital Devices GmbH
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* Marcus Metzler <mocm@metzlerbros.de>
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* Ralph Metzler <rjkm@metzlerbros.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* To obtain the license, point your browser to
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ddbridge.h"
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#include "ddbridge-regs.h"
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2017-12-12 01:18:46 +08:00
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#include "ddbridge-ci.h"
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2017-10-16 04:51:52 +08:00
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#include "ddbridge-io.h"
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#include "ddbridge-i2c.h"
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#include "cxd2099.h"
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/* Octopus CI internal CI interface */
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static int wait_ci_ready(struct ddb_ci *ci)
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{
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u32 count = 10;
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ndelay(500);
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do {
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if (ddbreadl(ci->port->dev,
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CI_CONTROL(ci->nr)) & CI_READY)
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break;
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usleep_range(1, 2);
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if ((--count) == 0)
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return -1;
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} while (1);
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return 0;
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}
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static int read_attribute_mem(struct dvb_ca_en50221 *ca,
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int slot, int address)
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{
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struct ddb_ci *ci = ca->data;
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u32 val, off = (address >> 1) & (CI_BUFFER_SIZE - 1);
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if (address > CI_BUFFER_SIZE)
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return -1;
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ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address,
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CI_DO_READ_ATTRIBUTES(ci->nr));
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wait_ci_ready(ci);
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val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off);
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return val;
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}
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static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
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int address, u8 value)
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{
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
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CI_DO_ATTRIBUTE_RW(ci->nr));
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wait_ci_ready(ci);
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return 0;
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}
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static int read_cam_control(struct dvb_ca_en50221 *ca,
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int slot, u8 address)
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{
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u32 count = 100;
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struct ddb_ci *ci = ca->data;
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u32 res;
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ddbwritel(ci->port->dev, CI_READ_CMD | address,
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CI_DO_IO_RW(ci->nr));
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ndelay(500);
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do {
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res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr));
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if (res & CI_READY)
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break;
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usleep_range(1, 2);
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if ((--count) == 0)
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return -1;
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} while (1);
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return 0xff & res;
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}
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static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
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u8 address, u8 value)
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{
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
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CI_DO_IO_RW(ci->nr));
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wait_ci_ready(ci);
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return 0;
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}
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static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, CI_POWER_ON,
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CI_CONTROL(ci->nr));
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msleep(100);
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ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM,
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CI_CONTROL(ci->nr));
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ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM,
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CI_CONTROL(ci->nr));
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usleep_range(20, 25);
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ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON,
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CI_CONTROL(ci->nr));
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return 0;
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}
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static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr));
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msleep(300);
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return 0;
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}
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static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
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ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE,
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CI_CONTROL(ci->nr));
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return 0;
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}
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static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
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{
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struct ddb_ci *ci = ca->data;
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u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
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int stat = 0;
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if (val & CI_CAM_DETECT)
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stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
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if (val & CI_CAM_READY)
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stat |= DVB_CA_EN50221_POLL_CAM_READY;
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return stat;
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}
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static struct dvb_ca_en50221 en_templ = {
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.read_attribute_mem = read_attribute_mem,
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.write_attribute_mem = write_attribute_mem,
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.read_cam_control = read_cam_control,
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.write_cam_control = write_cam_control,
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.slot_reset = slot_reset,
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.slot_shutdown = slot_shutdown,
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.slot_ts_enable = slot_ts_enable,
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.poll_slot_status = poll_slot_status,
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};
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static void ci_attach(struct ddb_port *port)
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{
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struct ddb_ci *ci = NULL;
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ci = kzalloc(sizeof(*ci), GFP_KERNEL);
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if (!ci)
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return;
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memcpy(&ci->en, &en_templ, sizeof(en_templ));
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ci->en.data = ci;
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port->en = &ci->en;
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2018-03-07 00:39:10 +08:00
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port->en_freedata = 1;
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2017-10-16 04:51:52 +08:00
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ci->port = port;
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ci->nr = port->nr - 2;
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}
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/* DuoFlex Dual CI support */
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static int write_creg(struct ddb_ci *ci, u8 data, u8 mask)
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{
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struct i2c_adapter *i2c = &ci->port->i2c->adap;
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u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
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ci->port->creg = (ci->port->creg & ~mask) | data;
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return i2c_write_reg(i2c, adr, 0x02, ci->port->creg);
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}
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static int read_attribute_mem_xo2(struct dvb_ca_en50221 *ca,
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int slot, int address)
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{
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struct ddb_ci *ci = ca->data;
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struct i2c_adapter *i2c = &ci->port->i2c->adap;
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u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
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int res;
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u8 val;
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res = i2c_read_reg16(i2c, adr, 0x8000 | address, &val);
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return res ? res : val;
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}
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static int write_attribute_mem_xo2(struct dvb_ca_en50221 *ca, int slot,
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int address, u8 value)
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{
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struct ddb_ci *ci = ca->data;
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struct i2c_adapter *i2c = &ci->port->i2c->adap;
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u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
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return i2c_write_reg16(i2c, adr, 0x8000 | address, value);
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}
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static int read_cam_control_xo2(struct dvb_ca_en50221 *ca,
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int slot, u8 address)
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{
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struct ddb_ci *ci = ca->data;
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struct i2c_adapter *i2c = &ci->port->i2c->adap;
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u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
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u8 val;
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int res;
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res = i2c_read_reg(i2c, adr, 0x20 | (address & 3), &val);
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return res ? res : val;
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}
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static int write_cam_control_xo2(struct dvb_ca_en50221 *ca, int slot,
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u8 address, u8 value)
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{
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struct ddb_ci *ci = ca->data;
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struct i2c_adapter *i2c = &ci->port->i2c->adap;
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u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
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return i2c_write_reg(i2c, adr, 0x20 | (address & 3), value);
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}
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static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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dev_dbg(ci->port->dev->dev, "%s\n", __func__);
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write_creg(ci, 0x01, 0x01);
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write_creg(ci, 0x04, 0x04);
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msleep(20);
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write_creg(ci, 0x02, 0x02);
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write_creg(ci, 0x00, 0x04);
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write_creg(ci, 0x18, 0x18);
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return 0;
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}
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static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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dev_dbg(ci->port->dev->dev, "%s\n", __func__);
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write_creg(ci, 0x10, 0xff);
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write_creg(ci, 0x08, 0x08);
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return 0;
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}
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static int slot_ts_enable_xo2(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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2017-10-16 04:51:53 +08:00
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dev_dbg(ci->port->dev->dev, "%s\n", __func__);
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2017-10-16 04:51:52 +08:00
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write_creg(ci, 0x00, 0x10);
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return 0;
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}
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static int poll_slot_status_xo2(struct dvb_ca_en50221 *ca, int slot, int open)
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{
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struct ddb_ci *ci = ca->data;
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struct i2c_adapter *i2c = &ci->port->i2c->adap;
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u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
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u8 val = 0;
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int stat = 0;
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i2c_read_reg(i2c, adr, 0x01, &val);
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if (val & 2)
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stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
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if (val & 1)
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stat |= DVB_CA_EN50221_POLL_CAM_READY;
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return stat;
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}
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static struct dvb_ca_en50221 en_xo2_templ = {
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.read_attribute_mem = read_attribute_mem_xo2,
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.write_attribute_mem = write_attribute_mem_xo2,
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.read_cam_control = read_cam_control_xo2,
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.write_cam_control = write_cam_control_xo2,
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.slot_reset = slot_reset_xo2,
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.slot_shutdown = slot_shutdown_xo2,
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.slot_ts_enable = slot_ts_enable_xo2,
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.poll_slot_status = poll_slot_status_xo2,
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};
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static void ci_xo2_attach(struct ddb_port *port)
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{
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struct ddb_ci *ci;
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ci = kzalloc(sizeof(*ci), GFP_KERNEL);
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if (!ci)
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return;
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memcpy(&ci->en, &en_xo2_templ, sizeof(en_xo2_templ));
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ci->en.data = ci;
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port->en = &ci->en;
|
2018-03-07 00:39:10 +08:00
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port->en_freedata = 1;
|
2017-10-16 04:51:52 +08:00
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ci->port = port;
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ci->nr = port->nr - 2;
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ci->port->creg = 0;
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write_creg(ci, 0x10, 0xff);
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write_creg(ci, 0x08, 0x08);
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}
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|
2018-03-07 00:39:10 +08:00
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static const struct cxd2099_cfg cxd_cfgtmpl = {
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2017-10-16 04:51:52 +08:00
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.bitrate = 72000,
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.polarity = 1,
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.clock_mode = 1,
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.max_i2c = 512,
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};
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|
2018-03-07 00:39:10 +08:00
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static int ci_cxd2099_attach(struct ddb_port *port, u32 bitrate)
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{
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struct cxd2099_cfg cxd_cfg = cxd_cfgtmpl;
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struct i2c_client *client;
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cxd_cfg.bitrate = bitrate;
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cxd_cfg.en = &port->en;
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2018-03-08 04:07:55 +08:00
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client = dvb_module_probe("cxd2099", NULL, &port->i2c->adap,
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0x40, &cxd_cfg);
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if (!client)
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goto err;
|
2018-03-07 00:39:10 +08:00
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port->dvb[0].i2c_client[0] = client;
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port->en_freedata = 0;
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return 0;
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2018-03-08 04:07:55 +08:00
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err:
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2018-03-07 00:39:10 +08:00
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|
dev_err(port->dev->dev, "CXD2099AR attach failed\n");
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return -ENODEV;
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|
|
|
}
|
|
|
|
|
2017-10-16 04:51:52 +08:00
|
|
|
int ddb_ci_attach(struct ddb_port *port, u32 bitrate)
|
|
|
|
{
|
2018-03-07 00:39:10 +08:00
|
|
|
int ret;
|
|
|
|
|
2017-10-16 04:51:52 +08:00
|
|
|
switch (port->type) {
|
|
|
|
case DDB_CI_EXTERNAL_SONY:
|
2018-03-07 00:39:10 +08:00
|
|
|
ret = ci_cxd2099_attach(port, bitrate);
|
|
|
|
if (ret)
|
|
|
|
return -ENODEV;
|
2017-10-16 04:51:52 +08:00
|
|
|
break;
|
|
|
|
case DDB_CI_EXTERNAL_XO2:
|
|
|
|
case DDB_CI_EXTERNAL_XO2_B:
|
|
|
|
ci_xo2_attach(port);
|
|
|
|
break;
|
|
|
|
case DDB_CI_INTERNAL:
|
|
|
|
ci_attach(port);
|
|
|
|
break;
|
2018-02-09 03:53:12 +08:00
|
|
|
default:
|
|
|
|
return -ENODEV;
|
2017-10-16 04:51:52 +08:00
|
|
|
}
|
2017-12-17 23:40:44 +08:00
|
|
|
|
2018-02-09 03:53:12 +08:00
|
|
|
if (!port->en)
|
|
|
|
return -ENODEV;
|
2017-12-17 23:40:44 +08:00
|
|
|
dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1);
|
2017-10-16 04:51:52 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-12-17 23:40:45 +08:00
|
|
|
|
|
|
|
void ddb_ci_detach(struct ddb_port *port)
|
|
|
|
{
|
|
|
|
if (port->dvb[0].dev)
|
|
|
|
dvb_unregister_device(port->dvb[0].dev);
|
|
|
|
if (port->en) {
|
|
|
|
dvb_ca_en50221_release(port->en);
|
2018-03-07 00:39:10 +08:00
|
|
|
|
2018-03-08 04:07:55 +08:00
|
|
|
dvb_module_release(port->dvb[0].i2c_client[0]);
|
|
|
|
port->dvb[0].i2c_client[0] = NULL;
|
2018-03-07 00:39:10 +08:00
|
|
|
|
|
|
|
/* free alloc'ed memory if needed */
|
|
|
|
if (port->en_freedata)
|
|
|
|
kfree(port->en->data);
|
|
|
|
|
2017-12-17 23:40:45 +08:00
|
|
|
port->en = NULL;
|
|
|
|
}
|
|
|
|
}
|