2007-05-09 09:00:38 +08:00
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/*
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* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_QP_H
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#define MLX4_QP_H
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#include <linux/types.h>
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2013-08-02 07:17:48 +08:00
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#include <linux/if_ether.h>
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2007-05-09 09:00:38 +08:00
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#include <linux/mlx4/device.h>
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#define MLX4_INVALID_LKEY 0x100
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enum mlx4_qp_optpar {
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MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
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MLX4_QP_OPTPAR_RRE = 1 << 1,
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MLX4_QP_OPTPAR_RAE = 1 << 2,
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MLX4_QP_OPTPAR_RWE = 1 << 3,
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MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
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MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
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MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
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MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
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MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
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MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
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MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
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MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
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MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
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MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
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2011-06-15 22:49:57 +08:00
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MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
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2014-09-10 21:41:56 +08:00
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MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20,
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MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21,
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2007-05-09 09:00:38 +08:00
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};
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enum mlx4_qp_state {
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MLX4_QP_STATE_RST = 0,
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MLX4_QP_STATE_INIT = 1,
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MLX4_QP_STATE_RTR = 2,
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MLX4_QP_STATE_RTS = 3,
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MLX4_QP_STATE_SQER = 4,
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MLX4_QP_STATE_SQD = 5,
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MLX4_QP_STATE_ERR = 6,
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MLX4_QP_STATE_SQ_DRAINING = 7,
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MLX4_QP_NUM_STATE
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};
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enum {
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MLX4_QP_ST_RC = 0x0,
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MLX4_QP_ST_UC = 0x1,
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MLX4_QP_ST_RD = 0x2,
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MLX4_QP_ST_UD = 0x3,
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2011-06-03 02:32:15 +08:00
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MLX4_QP_ST_XRC = 0x6,
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2007-05-09 09:00:38 +08:00
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MLX4_QP_ST_MLX = 0x7
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};
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enum {
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MLX4_QP_PM_MIGRATED = 0x3,
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MLX4_QP_PM_ARMED = 0x0,
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MLX4_QP_PM_REARM = 0x1
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};
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enum {
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/* params1 */
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MLX4_QP_BIT_SRE = 1 << 15,
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MLX4_QP_BIT_SWE = 1 << 14,
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MLX4_QP_BIT_SAE = 1 << 13,
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/* params2 */
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MLX4_QP_BIT_RRE = 1 << 15,
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MLX4_QP_BIT_RWE = 1 << 14,
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MLX4_QP_BIT_RAE = 1 << 13,
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2015-02-03 22:48:32 +08:00
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MLX4_QP_BIT_FPP = 1 << 3,
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2007-05-09 09:00:38 +08:00
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MLX4_QP_BIT_RIC = 1 << 4,
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};
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2011-11-27 03:54:58 +08:00
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enum {
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MLX4_RSS_HASH_XOR = 0,
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MLX4_RSS_HASH_TOP = 1,
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MLX4_RSS_UDP_IPV6 = 1 << 0,
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MLX4_RSS_UDP_IPV4 = 1 << 1,
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MLX4_RSS_TCP_IPV6 = 1 << 2,
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MLX4_RSS_IPV6 = 1 << 3,
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MLX4_RSS_TCP_IPV4 = 1 << 4,
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MLX4_RSS_IPV4 = 1 << 5,
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2013-12-23 22:09:43 +08:00
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MLX4_RSS_BY_OUTER_HEADERS = 0 << 6,
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MLX4_RSS_BY_INNER_HEADERS = 2 << 6,
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MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6,
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2011-11-27 03:54:58 +08:00
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/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
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MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
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/* offset of being RSS indirection QP within mlx4_qp_context.flags */
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MLX4_RSS_QPC_FLAG_OFFSET = 13,
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};
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2014-11-16 22:23:16 +08:00
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#define MLX4_EN_RSS_KEY_SIZE 40
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2011-11-27 03:54:58 +08:00
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struct mlx4_rss_context {
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__be32 base_qpn;
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__be32 default_qpn;
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u16 reserved;
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u8 hash_fn;
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u8 flags;
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2014-11-16 22:23:16 +08:00
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__be32 rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
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2011-11-27 03:54:58 +08:00
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__be32 base_qpn_udp;
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};
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2007-05-09 09:00:38 +08:00
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struct mlx4_qp_path {
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u8 fl;
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2013-05-09 06:22:35 +08:00
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u8 vlan_control;
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2012-08-03 16:40:40 +08:00
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u8 disable_pkey_check;
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2007-05-09 09:00:38 +08:00
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u8 pkey_index;
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2011-06-15 22:43:43 +08:00
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u8 counter_index;
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2007-05-09 09:00:38 +08:00
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u8 grh_mylmc;
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__be16 rlid;
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u8 ackto;
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u8 mgid_index;
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u8 static_rate;
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u8 hop_limit;
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__be32 tclass_flowlabel;
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u8 rgid[16];
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u8 sched_queue;
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2010-08-26 22:19:22 +08:00
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u8 vlan_index;
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2012-04-05 05:33:24 +08:00
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u8 feup;
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2013-05-09 06:22:35 +08:00
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u8 fvl_rx;
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2011-06-15 22:43:43 +08:00
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u8 reserved4[2];
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2013-08-02 07:17:48 +08:00
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u8 dmac[ETH_ALEN];
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2007-05-09 09:00:38 +08:00
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};
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2013-05-09 06:22:35 +08:00
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enum { /* fl */
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MLX4_FL_CV = 1 << 6,
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MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2
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};
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enum { /* vlan_control */
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MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
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2013-06-28 00:05:22 +08:00
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MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
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MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4,
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2013-05-09 06:22:35 +08:00
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MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
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MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
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MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
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};
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enum { /* feup */
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MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
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MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
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MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
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};
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enum { /* fvl_rx */
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MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
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};
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2007-05-09 09:00:38 +08:00
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struct mlx4_qp_context {
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__be32 flags;
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__be32 pd;
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u8 mtu_msgmax;
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u8 rq_size_stride;
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u8 sq_size_stride;
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u8 rlkey;
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__be32 usr_page;
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__be32 local_qpn;
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__be32 remote_qpn;
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struct mlx4_qp_path pri_path;
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struct mlx4_qp_path alt_path;
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__be32 params1;
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u32 reserved1;
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__be32 next_send_psn;
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__be32 cqn_send;
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u32 reserved2[2];
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__be32 last_acked_psn;
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__be32 ssn;
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__be32 params2;
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__be32 rnr_nextrecvpsn;
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2011-06-03 02:32:15 +08:00
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__be32 xrcd;
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2007-05-09 09:00:38 +08:00
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__be32 cqn_recv;
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__be64 db_rec_addr;
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__be32 qkey;
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__be32 srqn;
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__be32 msn;
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__be16 rq_wqe_counter;
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__be16 sq_wqe_counter;
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2015-03-18 20:57:34 +08:00
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u32 reserved3;
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__be16 rate_limit_params;
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__be16 reserved4;
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2007-05-09 09:00:38 +08:00
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__be32 param3;
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__be32 nummmcpeers_basemkey;
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u8 log_page_size;
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2015-03-18 20:57:34 +08:00
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u8 reserved5[2];
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2007-05-09 09:00:38 +08:00
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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2015-03-18 20:57:34 +08:00
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u32 reserved6[10];
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2007-05-09 09:00:38 +08:00
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};
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2013-06-28 00:05:21 +08:00
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struct mlx4_update_qp_context {
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__be64 qp_mask;
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__be64 primary_addr_path_mask;
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__be64 secondary_addr_path_mask;
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u64 reserved1;
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struct mlx4_qp_context qp_context;
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u64 reserved2[58];
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};
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enum {
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MLX4_UPD_QP_MASK_PM_STATE = 32,
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MLX4_UPD_QP_MASK_VSD = 33,
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2015-03-18 20:57:34 +08:00
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MLX4_UPD_QP_MASK_RATE_LIMIT = 35,
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2013-06-28 00:05:21 +08:00
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};
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enum {
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MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
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MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
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MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
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MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
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MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
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MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
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MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
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MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
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MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
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MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
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};
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2013-05-09 06:22:35 +08:00
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enum { /* param3 */
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MLX4_STRIP_VLAN = 1 << 30
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};
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IB/mlx4: Use multiple WQ blocks to post smaller send WQEs
ConnectX HCA supports shrinking WQEs, so that a single work request
can be made of multiple units of wqe_shift. This way, WRs can differ
in size, and do not have to be a power of 2 in size, saving memory and
speeding up send WR posting. Unfortunately, if we do this then the
wqe_index field in CQEs can't be used to look up the WR ID anymore, so
our implementation does this only if selective signaling is off.
Further, on 32-bit platforms, we can't use vmap() to make the QP
buffer virtually contigious. Thus we have to use constant-sized WRs to
make sure a WR is always fully within a single page-sized chunk.
Finally, we use WRs with the NOP opcode to avoid wrapping around the
queue buffer in the middle of posting a WR, and we set the
NoErrorCompletion bit to avoid getting completions with error for NOP
WRs. However, NEC is only supported starting with firmware 2.2.232,
so we use constant-sized WRs for older firmware. And, since MLX QPs
only support SEND, we use constant-sized WRs in this case.
When stamping during NOP posting, do stamping following setting of the
NOP WQE valid bit.
Signed-off-by: Michael S. Tsirkin <mst@dev.mellanox.co.il>
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
2008-01-28 16:40:59 +08:00
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/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
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#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
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2007-05-09 09:00:38 +08:00
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enum {
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2008-04-17 12:01:10 +08:00
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MLX4_WQE_CTRL_NEC = 1 << 29,
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2013-12-23 22:09:43 +08:00
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MLX4_WQE_CTRL_IIP = 1 << 28,
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MLX4_WQE_CTRL_ILP = 1 << 27,
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2008-04-17 12:01:10 +08:00
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MLX4_WQE_CTRL_FENCE = 1 << 6,
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MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
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MLX4_WQE_CTRL_SOLICITED = 1 << 1,
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MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
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MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
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2008-07-26 01:30:06 +08:00
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MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
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2009-06-06 01:36:24 +08:00
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MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
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2010-10-21 12:57:02 +08:00
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MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
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2007-05-09 09:00:38 +08:00
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};
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struct mlx4_wqe_ctrl_seg {
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__be32 owner_opcode;
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2014-03-02 16:25:04 +08:00
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union {
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struct {
|
|
|
|
__be16 vlan_tag;
|
|
|
|
u8 ins_vlan;
|
|
|
|
u8 fence_size;
|
|
|
|
};
|
|
|
|
__be32 bf_qpn;
|
|
|
|
};
|
2007-05-09 09:00:38 +08:00
|
|
|
/*
|
|
|
|
* High 24 bits are SRC remote buffer; low 8 bits are flags:
|
|
|
|
* [7] SO (strong ordering)
|
|
|
|
* [5] TCP/UDP checksum
|
|
|
|
* [4] IP checksum
|
|
|
|
* [3:2] C (generate completion queue entry)
|
|
|
|
* [1] SE (solicited event)
|
2011-11-27 03:55:19 +08:00
|
|
|
* [0] FL (force loopback)
|
2007-05-09 09:00:38 +08:00
|
|
|
*/
|
2012-02-25 08:51:05 +08:00
|
|
|
union {
|
|
|
|
__be32 srcrb_flags;
|
|
|
|
__be16 srcrb_flags16[2];
|
|
|
|
};
|
2007-05-09 09:00:38 +08:00
|
|
|
/*
|
|
|
|
* imm is immediate data for send/RDMA write w/ immediate;
|
|
|
|
* also invalidation key for send with invalidate; input
|
|
|
|
* modifier for WQEs on CCQs.
|
|
|
|
*/
|
|
|
|
__be32 imm;
|
|
|
|
};
|
|
|
|
|
|
|
|
enum {
|
|
|
|
MLX4_WQE_MLX_VL15 = 1 << 17,
|
|
|
|
MLX4_WQE_MLX_SLR = 1 << 16
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_wqe_mlx_seg {
|
|
|
|
u8 owner;
|
|
|
|
u8 reserved1[2];
|
|
|
|
u8 opcode;
|
2012-04-29 22:04:24 +08:00
|
|
|
__be16 sched_prio;
|
|
|
|
u8 reserved2;
|
2007-05-09 09:00:38 +08:00
|
|
|
u8 size;
|
|
|
|
/*
|
|
|
|
* [17] VL15
|
|
|
|
* [16] SLR
|
|
|
|
* [15:12] static rate
|
|
|
|
* [11:8] SL
|
|
|
|
* [4] ICRC
|
|
|
|
* [3:2] C
|
|
|
|
* [0] FL (force loopback)
|
|
|
|
*/
|
|
|
|
__be32 flags;
|
|
|
|
__be16 rlid;
|
|
|
|
u16 reserved3;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_wqe_datagram_seg {
|
|
|
|
__be32 av[8];
|
|
|
|
__be32 dqpn;
|
|
|
|
__be32 qkey;
|
2010-10-21 12:57:02 +08:00
|
|
|
__be16 vlan;
|
2013-08-02 07:17:48 +08:00
|
|
|
u8 mac[ETH_ALEN];
|
2007-05-09 09:00:38 +08:00
|
|
|
};
|
|
|
|
|
2008-07-23 05:19:39 +08:00
|
|
|
struct mlx4_wqe_lso_seg {
|
2008-04-17 12:09:27 +08:00
|
|
|
__be32 mss_hdr_size;
|
|
|
|
__be32 header[0];
|
|
|
|
};
|
|
|
|
|
2013-02-07 00:19:15 +08:00
|
|
|
enum mlx4_wqe_bind_seg_flags2 {
|
|
|
|
MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
|
|
|
|
MLX4_WQE_BIND_TYPE_2 = (1 << 31),
|
|
|
|
};
|
|
|
|
|
2007-05-09 09:00:38 +08:00
|
|
|
struct mlx4_wqe_bind_seg {
|
|
|
|
__be32 flags1;
|
|
|
|
__be32 flags2;
|
|
|
|
__be32 new_rkey;
|
|
|
|
__be32 lkey;
|
|
|
|
__be64 addr;
|
|
|
|
__be64 length;
|
|
|
|
};
|
|
|
|
|
2008-07-23 23:12:26 +08:00
|
|
|
enum {
|
|
|
|
MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
|
|
|
|
MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
|
2013-02-07 00:19:15 +08:00
|
|
|
MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
|
|
|
|
MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
|
|
|
|
MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
|
2008-07-23 23:12:26 +08:00
|
|
|
};
|
|
|
|
|
2007-05-09 09:00:38 +08:00
|
|
|
struct mlx4_wqe_fmr_seg {
|
|
|
|
__be32 flags;
|
|
|
|
__be32 mem_key;
|
|
|
|
__be64 buf_list;
|
|
|
|
__be64 start_addr;
|
|
|
|
__be64 reg_len;
|
|
|
|
__be32 offset;
|
|
|
|
__be32 page_size;
|
|
|
|
u32 reserved[2];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_wqe_fmr_ext_seg {
|
|
|
|
u8 flags;
|
|
|
|
u8 reserved;
|
|
|
|
__be16 app_mask;
|
|
|
|
__be16 wire_app_tag;
|
|
|
|
__be16 mem_app_tag;
|
|
|
|
__be32 wire_ref_tag_base;
|
|
|
|
__be32 mem_ref_tag_base;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_wqe_local_inval_seg {
|
2013-02-07 00:19:07 +08:00
|
|
|
u64 reserved1;
|
2007-05-09 09:00:38 +08:00
|
|
|
__be32 mem_key;
|
2013-02-07 00:19:07 +08:00
|
|
|
u32 reserved2;
|
|
|
|
u64 reserved3[2];
|
2007-05-09 09:00:38 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_wqe_raddr_seg {
|
|
|
|
__be64 raddr;
|
|
|
|
__be32 rkey;
|
|
|
|
u32 reserved;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_wqe_atomic_seg {
|
|
|
|
__be64 swap_add;
|
|
|
|
__be64 compare;
|
|
|
|
};
|
|
|
|
|
2010-04-14 22:23:39 +08:00
|
|
|
struct mlx4_wqe_masked_atomic_seg {
|
|
|
|
__be64 swap_add;
|
|
|
|
__be64 compare;
|
|
|
|
__be64 swap_add_mask;
|
|
|
|
__be64 compare_mask;
|
|
|
|
};
|
|
|
|
|
2007-05-09 09:00:38 +08:00
|
|
|
struct mlx4_wqe_data_seg {
|
|
|
|
__be32 byte_count;
|
|
|
|
__be32 lkey;
|
|
|
|
__be64 addr;
|
|
|
|
};
|
|
|
|
|
2007-06-19 00:23:47 +08:00
|
|
|
enum {
|
|
|
|
MLX4_INLINE_ALIGN = 64,
|
2011-03-23 06:38:41 +08:00
|
|
|
MLX4_INLINE_SEG = 1 << 31,
|
2007-06-19 00:23:47 +08:00
|
|
|
};
|
|
|
|
|
2007-05-09 09:00:38 +08:00
|
|
|
struct mlx4_wqe_inline_seg {
|
|
|
|
__be32 byte_count;
|
|
|
|
};
|
|
|
|
|
2014-05-15 20:29:27 +08:00
|
|
|
enum mlx4_update_qp_attr {
|
|
|
|
MLX4_UPDATE_QP_SMAC = 1 << 0,
|
2015-03-03 00:22:15 +08:00
|
|
|
MLX4_UPDATE_QP_VSD = 1 << 1,
|
2015-03-18 20:57:34 +08:00
|
|
|
MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2,
|
|
|
|
MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 3) - 1
|
2014-09-10 21:41:56 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
enum mlx4_update_qp_params_flags {
|
|
|
|
MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 0,
|
2014-05-15 20:29:27 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct mlx4_update_qp_params {
|
|
|
|
u8 smac_index;
|
2014-09-10 21:41:56 +08:00
|
|
|
u32 flags;
|
2015-03-18 20:57:34 +08:00
|
|
|
u16 rate_unit;
|
|
|
|
u16 rate_val;
|
2014-05-15 20:29:27 +08:00
|
|
|
};
|
|
|
|
|
2014-09-10 21:41:56 +08:00
|
|
|
int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
|
2014-05-15 20:29:27 +08:00
|
|
|
enum mlx4_update_qp_attr attr,
|
|
|
|
struct mlx4_update_qp_params *params);
|
2007-05-09 09:00:38 +08:00
|
|
|
int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
|
|
|
enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
|
|
|
|
struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
|
|
|
|
int sqd_event, struct mlx4_qp *qp);
|
|
|
|
|
2007-06-21 17:27:47 +08:00
|
|
|
int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
|
|
|
|
struct mlx4_qp_context *context);
|
|
|
|
|
2008-04-26 05:52:32 +08:00
|
|
|
int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
|
|
|
struct mlx4_qp_context *context,
|
|
|
|
struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
|
|
|
|
|
2007-05-09 09:00:38 +08:00
|
|
|
static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
|
|
|
|
{
|
|
|
|
return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
|
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
|
|
|
|
|
|
|
|
#endif /* MLX4_QP_H */
|