130 lines
4.5 KiB
C
130 lines
4.5 KiB
C
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/**
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* @section LICENSE
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* Copyright (c) 2014 Redpine Signals Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef __RSI_SDIO_INTF__
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#define __RSI_SDIO_INTF__
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#include <linux/mmc/card.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sdio_func.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio_ids.h>
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#include "rsi_main.h"
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enum sdio_interrupt_type {
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BUFFER_FULL = 0x0,
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BUFFER_AVAILABLE = 0x1,
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FIRMWARE_ASSERT_IND = 0x3,
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MSDU_PACKET_PENDING = 0x4,
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UNKNOWN_INT = 0XE
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};
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/* Buffer status register related info */
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#define PKT_BUFF_SEMI_FULL 0
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#define PKT_BUFF_FULL 1
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#define PKT_MGMT_BUFF_FULL 2
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#define MSDU_PKT_PENDING 3
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/* Interrupt Bit Related Macros */
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#define PKT_BUFF_AVAILABLE 0
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#define FW_ASSERT_IND 2
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#define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3
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#define RSI_FN1_INT_REGISTER 0xf9
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#define RSI_SD_REQUEST_MASTER 0x10000
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/* FOR SD CARD ONLY */
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#define SDIO_RX_NUM_BLOCKS_REG 0x000F1
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#define SDIO_FW_STATUS_REG 0x000F2
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#define SDIO_NXT_RD_DELAY2 0x000F5
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#define SDIO_MASTER_ACCESS_MSBYTE 0x000FA
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#define SDIO_MASTER_ACCESS_LSBYTE 0x000FB
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#define SDIO_READ_START_LVL 0x000FC
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#define SDIO_READ_FIFO_CTL 0x000FD
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#define SDIO_WRITE_FIFO_CTL 0x000FE
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#define SDIO_FUN1_INTR_CLR_REG 0x0008
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#define SDIO_REG_HIGH_SPEED 0x0013
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#define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE) \
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{ \
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TYPE = \
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(_I & (1 << PKT_BUFF_AVAILABLE)) ? \
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BUFFER_AVAILABLE : \
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(_I & (1 << MSDU_PKT_PENDING)) ? \
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MSDU_PACKET_PENDING : \
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(_I & (1 << FW_ASSERT_IND)) ? \
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FIRMWARE_ASSERT_IND : UNKNOWN_INT; \
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}
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/* common registers in SDIO function1 */
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#define TA_SOFT_RESET_REG 0x0004
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#define TA_TH0_PC_REG 0x0400
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#define TA_HOLD_THREAD_REG 0x0844
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#define TA_RELEASE_THREAD_REG 0x0848
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#define TA_SOFT_RST_CLR 0
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#define TA_SOFT_RST_SET BIT(0)
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#define TA_PC_ZERO 0
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#define TA_HOLD_THREAD_VALUE cpu_to_le32(0xF)
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#define TA_RELEASE_THREAD_VALUE cpu_to_le32(0xF)
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#define TA_BASE_ADDR 0x2200
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#define MISC_CFG_BASE_ADDR 0x4150
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struct receive_info {
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bool buffer_full;
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bool semi_buffer_full;
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bool mgmt_buffer_full;
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u32 mgmt_buf_full_counter;
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u32 buf_semi_full_counter;
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u8 watch_bufferfull_count;
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u32 sdio_intr_status_zero;
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u32 sdio_int_counter;
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u32 total_sdio_msdu_pending_intr;
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u32 total_sdio_unknown_intr;
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u32 buf_full_counter;
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u32 buf_avilable_counter;
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};
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struct rsi_91x_sdiodev {
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struct sdio_func *pfunction;
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struct task_struct *in_sdio_litefi_irq;
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struct receive_info rx_info;
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u32 next_read_delay;
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u32 sdio_high_speed_enable;
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u8 sdio_clock_speed;
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u32 cardcapability;
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u8 prev_desc[16];
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u32 tx_blk_size;
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u8 write_fail;
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};
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void rsi_interrupt_handler(struct rsi_hw *adapter);
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int rsi_init_sdio_slave_regs(struct rsi_hw *adapter);
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int rsi_sdio_device_init(struct rsi_common *common);
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int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data);
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int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length);
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int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function,
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u32 addr, u8 *data);
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int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr,
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u8 *data, u32 count);
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void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit);
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int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter);
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int rsi_sdio_read_buffer_status_register(struct rsi_hw *adapter, u8 q_num);
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#endif
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