2018-09-07 15:01:18 +08:00
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "nitrox_dev.h"
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#include "nitrox_hal.h"
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#include "nitrox_common.h"
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2018-09-29 16:19:10 +08:00
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#include "nitrox_isr.h"
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2018-12-04 20:55:54 +08:00
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#include "nitrox_mbx.h"
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2018-09-07 15:01:18 +08:00
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2018-11-21 17:52:24 +08:00
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/**
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* num_vfs_valid - validate VF count
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* @num_vfs: number of VF(s)
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*/
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2018-09-07 15:01:18 +08:00
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static inline bool num_vfs_valid(int num_vfs)
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{
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bool valid = false;
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switch (num_vfs) {
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case 16:
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case 32:
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case 64:
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case 128:
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valid = true;
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break;
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}
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return valid;
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}
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static inline enum vf_mode num_vfs_to_mode(int num_vfs)
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{
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enum vf_mode mode = 0;
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switch (num_vfs) {
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case 0:
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mode = __NDEV_MODE_PF;
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break;
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case 16:
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mode = __NDEV_MODE_VF16;
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break;
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case 32:
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mode = __NDEV_MODE_VF32;
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break;
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case 64:
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mode = __NDEV_MODE_VF64;
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break;
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case 128:
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mode = __NDEV_MODE_VF128;
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break;
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}
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return mode;
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}
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2018-12-04 20:55:54 +08:00
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static inline int vf_mode_to_nr_queues(enum vf_mode mode)
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{
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int nr_queues = 0;
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switch (mode) {
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case __NDEV_MODE_PF:
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nr_queues = MAX_PF_QUEUES;
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break;
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case __NDEV_MODE_VF16:
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nr_queues = 8;
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break;
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case __NDEV_MODE_VF32:
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nr_queues = 4;
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break;
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case __NDEV_MODE_VF64:
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nr_queues = 2;
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break;
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case __NDEV_MODE_VF128:
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nr_queues = 1;
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break;
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}
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return nr_queues;
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}
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2018-11-21 17:52:24 +08:00
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static void nitrox_pf_cleanup(struct nitrox_device *ndev)
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2018-09-07 15:01:18 +08:00
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{
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/* PF has no queues in SR-IOV mode */
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atomic_set(&ndev->state, __NDEV_NOT_READY);
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/* unregister crypto algorithms */
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nitrox_crypto_unregister();
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/* cleanup PF resources */
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2018-09-29 16:19:10 +08:00
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nitrox_unregister_interrupts(ndev);
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2018-09-07 15:01:18 +08:00
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nitrox_common_sw_cleanup(ndev);
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}
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2018-11-21 17:52:24 +08:00
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/**
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* nitrox_pf_reinit - re-initialize PF resources once SR-IOV is disabled
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* @ndev: NITROX device
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*/
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static int nitrox_pf_reinit(struct nitrox_device *ndev)
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2018-09-07 15:01:18 +08:00
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{
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int err;
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/* allocate resources for PF */
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err = nitrox_common_sw_init(ndev);
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if (err)
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return err;
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2018-09-29 16:19:10 +08:00
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err = nitrox_register_interrupts(ndev);
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2018-09-07 15:01:18 +08:00
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if (err) {
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nitrox_common_sw_cleanup(ndev);
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return err;
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}
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2019-08-08 20:17:39 +08:00
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/* configure the AQM queues */
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nitrox_config_aqm_rings(ndev);
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2018-09-07 15:01:18 +08:00
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/* configure the packet queues */
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nitrox_config_pkt_input_rings(ndev);
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nitrox_config_pkt_solicit_ports(ndev);
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/* set device to ready state */
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atomic_set(&ndev->state, __NDEV_READY);
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/* register crypto algorithms */
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return nitrox_crypto_register();
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}
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2018-11-21 17:52:24 +08:00
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static void nitrox_sriov_cleanup(struct nitrox_device *ndev)
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{
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/* unregister interrupts for PF in SR-IOV */
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nitrox_sriov_unregister_interrupts(ndev);
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2018-12-04 20:55:54 +08:00
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nitrox_mbox_cleanup(ndev);
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}
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static int nitrox_sriov_init(struct nitrox_device *ndev)
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{
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int ret;
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/* register interrupts for PF in SR-IOV */
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ret = nitrox_sriov_register_interupts(ndev);
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if (ret)
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return ret;
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ret = nitrox_mbox_init(ndev);
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if (ret)
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goto sriov_init_fail;
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return 0;
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sriov_init_fail:
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nitrox_sriov_cleanup(ndev);
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return ret;
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2018-11-21 17:52:24 +08:00
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}
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2018-09-07 15:01:18 +08:00
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static int nitrox_sriov_enable(struct pci_dev *pdev, int num_vfs)
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{
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struct nitrox_device *ndev = pci_get_drvdata(pdev);
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int err;
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if (!num_vfs_valid(num_vfs)) {
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dev_err(DEV(ndev), "Invalid num_vfs %d\n", num_vfs);
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return -EINVAL;
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}
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if (pci_num_vf(pdev) == num_vfs)
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return num_vfs;
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err = pci_enable_sriov(pdev, num_vfs);
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if (err) {
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dev_err(DEV(ndev), "failed to enable PCI sriov %d\n", err);
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return err;
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}
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dev_info(DEV(ndev), "Enabled VF(s) %d\n", num_vfs);
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ndev->mode = num_vfs_to_mode(num_vfs);
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2018-12-04 20:55:54 +08:00
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ndev->iov.num_vfs = num_vfs;
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ndev->iov.max_vf_queues = vf_mode_to_nr_queues(ndev->mode);
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2018-09-07 15:01:18 +08:00
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/* set bit in flags */
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set_bit(__NDEV_SRIOV_BIT, &ndev->flags);
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/* cleanup PF resources */
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2018-11-21 17:52:24 +08:00
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nitrox_pf_cleanup(ndev);
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2018-09-07 15:01:18 +08:00
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2018-11-21 17:52:24 +08:00
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/* PF SR-IOV mode initialization */
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err = nitrox_sriov_init(ndev);
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if (err)
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goto iov_fail;
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2018-09-07 15:01:18 +08:00
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2018-11-21 17:52:24 +08:00
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config_nps_core_vfcfg_mode(ndev, ndev->mode);
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2018-09-07 15:01:18 +08:00
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return num_vfs;
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2018-11-21 17:52:24 +08:00
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iov_fail:
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pci_disable_sriov(pdev);
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/* clear bit in flags */
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clear_bit(__NDEV_SRIOV_BIT, &ndev->flags);
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ndev->iov.num_vfs = 0;
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ndev->mode = __NDEV_MODE_PF;
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/* reset back to working mode in PF */
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nitrox_pf_reinit(ndev);
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return err;
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2018-09-07 15:01:18 +08:00
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}
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static int nitrox_sriov_disable(struct pci_dev *pdev)
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{
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struct nitrox_device *ndev = pci_get_drvdata(pdev);
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if (!test_bit(__NDEV_SRIOV_BIT, &ndev->flags))
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return 0;
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if (pci_vfs_assigned(pdev)) {
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dev_warn(DEV(ndev), "VFs are attached to VM. Can't disable SR-IOV\n");
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return -EPERM;
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}
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pci_disable_sriov(pdev);
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/* clear bit in flags */
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clear_bit(__NDEV_SRIOV_BIT, &ndev->flags);
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2018-11-21 17:52:24 +08:00
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ndev->iov.num_vfs = 0;
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2018-12-04 20:55:54 +08:00
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ndev->iov.max_vf_queues = 0;
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2018-09-07 15:01:18 +08:00
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ndev->mode = __NDEV_MODE_PF;
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2018-11-21 17:52:24 +08:00
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/* cleanup PF SR-IOV resources */
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nitrox_sriov_cleanup(ndev);
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2018-09-07 15:01:18 +08:00
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config_nps_core_vfcfg_mode(ndev, ndev->mode);
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2018-11-21 17:52:24 +08:00
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return nitrox_pf_reinit(ndev);
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2018-09-07 15:01:18 +08:00
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}
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int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs)
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{
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if (!num_vfs)
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return nitrox_sriov_disable(pdev);
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return nitrox_sriov_enable(pdev, num_vfs);
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}
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