powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
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/*
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* This file contains the routines for initializing the MMU
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* on the 8xx series of chips.
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* -- christophe
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*
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* Derived from arch/powerpc/mm/40x_mmu.c:
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/memblock.h>
|
2016-05-17 15:02:45 +08:00
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|
#include <asm/fixmap.h>
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|
#include <asm/code-patching.h>
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
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#include "mmu_decl.h"
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|
2016-05-17 15:02:45 +08:00
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|
#define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT)
|
|
|
|
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
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extern int __map_without_ltlbs;
|
2016-05-17 15:02:45 +08:00
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/*
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* Return PA for this VA if it is in IMMR area, or 0
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*/
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phys_addr_t v_block_mapped(unsigned long va)
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|
|
{
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unsigned long p = PHYS_IMMR_BASE;
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if (__map_without_ltlbs)
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return 0;
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if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE)
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return p + va - VIRT_IMMR_BASE;
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return 0;
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|
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}
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/*
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* Return VA for a given PA or 0 if not mapped
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*/
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unsigned long p_block_mapped(phys_addr_t pa)
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{
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unsigned long p = PHYS_IMMR_BASE;
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if (__map_without_ltlbs)
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return 0;
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if (pa >= p && pa < p + IMMR_SIZE)
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return VIRT_IMMR_BASE + pa - p;
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return 0;
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}
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|
|
|
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
|
|
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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/* Nothing to do for the time being but keep it similar to other PPC */
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}
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#define LARGE_PAGE_SIZE_4M (1<<22)
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#define LARGE_PAGE_SIZE_8M (1<<23)
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#define LARGE_PAGE_SIZE_64M (1<<26)
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|
2016-05-17 15:02:45 +08:00
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static void mmu_mapin_immr(void)
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|
|
{
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unsigned long p = PHYS_IMMR_BASE;
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unsigned long v = VIRT_IMMR_BASE;
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unsigned long f = pgprot_val(PAGE_KERNEL_NCG);
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int offset;
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for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE)
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map_page(v + offset, p + offset, f);
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|
}
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/* Address of instructions to patch */
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#ifndef CONFIG_PIN_TLB
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|
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extern unsigned int DTLBMiss_jmp;
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#endif
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|
|
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
|
|
|
unsigned long __init mmu_mapin_ram(unsigned long top)
|
|
|
|
{
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|
unsigned long v, s, mapped;
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|
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phys_addr_t p;
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v = KERNELBASE;
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p = 0;
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s = top;
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|
2016-05-17 15:02:45 +08:00
|
|
|
if (__map_without_ltlbs) {
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mmu_mapin_immr();
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#ifndef CONFIG_PIN_TLB
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patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP);
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|
|
#endif
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
|
|
|
return 0;
|
2016-05-17 15:02:45 +08:00
|
|
|
}
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_4K_PAGES
|
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|
|
while (s >= LARGE_PAGE_SIZE_8M) {
|
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|
|
pmd_t *pmdp;
|
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|
|
unsigned long val = p | MD_PS8MEG;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
|
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|
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*pmdp++ = __pmd(val);
|
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|
|
*pmdp++ = __pmd(val + LARGE_PAGE_SIZE_4M);
|
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|
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v += LARGE_PAGE_SIZE_8M;
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|
|
p += LARGE_PAGE_SIZE_8M;
|
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|
|
s -= LARGE_PAGE_SIZE_8M;
|
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|
|
}
|
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|
|
#else /* CONFIG_PPC_16K_PAGES */
|
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|
|
while (s >= LARGE_PAGE_SIZE_64M) {
|
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|
|
pmd_t *pmdp;
|
|
|
|
unsigned long val = p | MD_PS8MEG;
|
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|
pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
|
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|
|
*pmdp++ = __pmd(val);
|
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|
|
v += LARGE_PAGE_SIZE_64M;
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|
|
p += LARGE_PAGE_SIZE_64M;
|
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|
|
s -= LARGE_PAGE_SIZE_64M;
|
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|
|
}
|
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|
|
#endif
|
|
|
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|
|
|
|
mapped = top - s;
|
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|
|
|
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|
|
/* If the size of RAM is not an exact power of two, we may not
|
|
|
|
* have covered RAM in its entirety with 8 MiB
|
|
|
|
* pages. Consequently, restrict the top end of RAM currently
|
|
|
|
* allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
|
|
|
|
* coverage with normal-sized pages (or other reasons) do not
|
|
|
|
* attempt to allocate outside the allowed range.
|
|
|
|
*/
|
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|
|
memblock_set_current_limit(mapped);
|
|
|
|
|
|
|
|
return mapped;
|
|
|
|
}
|
2016-02-10 00:07:54 +08:00
|
|
|
|
|
|
|
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
|
|
|
phys_addr_t first_memblock_size)
|
|
|
|
{
|
|
|
|
/* We don't currently support the first MEMBLOCK not mapping 0
|
|
|
|
* physical on those processors
|
|
|
|
*/
|
|
|
|
BUG_ON(first_memblock_base != 0);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PIN_TLB
|
|
|
|
/* 8xx can only access 24MB at the moment */
|
|
|
|
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
|
|
|
|
#else
|
|
|
|
/* 8xx can only access 8MB at the moment */
|
|
|
|
memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
|
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|
|
#endif
|
|
|
|
}
|
2016-02-10 00:08:18 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up to use a given MMU context.
|
|
|
|
* id is context number, pgd is PGD pointer.
|
|
|
|
*
|
|
|
|
* We place the physical address of the new task page directory loaded
|
|
|
|
* into the MMU base register, and set the ASID compare register with
|
|
|
|
* the new "context."
|
|
|
|
*/
|
|
|
|
void set_context(unsigned long id, pgd_t *pgd)
|
|
|
|
{
|
|
|
|
s16 offset = (s16)(__pa(swapper_pg_dir));
|
|
|
|
|
|
|
|
#ifdef CONFIG_BDI_SWITCH
|
|
|
|
pgd_t **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
|
|
|
|
|
|
|
|
/* Context switch the PTE pointer for the Abatron BDI2000.
|
|
|
|
* The PGDIR is passed as second argument.
|
|
|
|
*/
|
|
|
|
*(ptr + 1) = pgd;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Register M_TW will contain base address of level 1 table minus the
|
|
|
|
* lower part of the kernel PGDIR base address, so that all accesses to
|
|
|
|
* level 1 table are done relative to lower part of kernel PGDIR base
|
|
|
|
* address.
|
|
|
|
*/
|
|
|
|
mtspr(SPRN_M_TW, __pa(pgd) - offset);
|
|
|
|
|
|
|
|
/* Update context */
|
|
|
|
mtspr(SPRN_M_CASID, id);
|
|
|
|
/* sync */
|
|
|
|
mb();
|
|
|
|
}
|
2016-02-10 00:08:21 +08:00
|
|
|
|
|
|
|
void flush_instruction_cache(void)
|
|
|
|
{
|
|
|
|
isync();
|
|
|
|
mtspr(SPRN_IC_CST, IDC_INVALL);
|
|
|
|
isync();
|
|
|
|
}
|