OpenCloudOS-Kernel/drivers/clk/bcm/Makefile

obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC)	+= clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
obj-$(CONFIG_ARCH_BCM_CYGNUS)	+= clk-cygnus.o
clk: bcm281xx: add initial clock framework support Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org> 2014-02-15 02:29:18 +08:00			`obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o`
			`obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o`
			`obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o`
clk: bcm21664: use common clock framework Define the set of CCUs and provided clocks sufficient to satisfy the needs of all the existing clock references for BCM21664. Replace the "fake" fixed-rate clocks used previously with "real" ones. Note that only the minimal set of these clocks and CCUs is defined here. More clock definitions will need to be added as required by the addition of additional drivers. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-04-22 05:26:26 +08:00			`obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o`
clk: iproc: add initial common clock support This adds basic and generic support for various iProc PLLs and clocks including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks. SoCs under the iProc architecture can define their specific register offsets and clock parameters for their PLL and clock controllers. These parameters can be passed as arugments into the generic iProc PLL and clock setup functions Derived from code originally provided by Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2015-05-06 02:13:19 +08:00			`obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o`
clk: cygnus: add clock support for Broadcom Cygnus The Broadcom Cygnus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied from an onboard crystal. Cygnus also has various ASIU clocks that are derived directly from the onboard crystal. Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2015-05-06 02:13:21 +08:00			`obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o`