2016-07-13 23:03:40 +08:00
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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2017-10-09 19:02:57 +08:00
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#include <drm/drm_print.h>
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2016-07-13 23:03:40 +08:00
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#include "i915_drv.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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2017-04-28 15:53:36 +08:00
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/* Haswell does have the CXT_SIZE register however it does not appear to be
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* valid. Now, docs explain in dwords what is in the context object. The full
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* size is 70720 bytes, however, the power context and execlist context will
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* never be saved (power context is stored elsewhere, and execlists don't work
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* on HSW) - so the final size, including the extra state required for the
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* Resource Streamer, is 66944 bytes, which rounds to 17 pages.
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*/
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#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
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2018-01-12 06:55:06 +08:00
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#define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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2017-04-28 15:53:36 +08:00
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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2017-10-04 23:39:52 +08:00
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#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
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2018-01-12 06:55:07 +08:00
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#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
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2017-04-28 15:53:36 +08:00
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#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
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2017-04-10 22:34:32 +08:00
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struct engine_class_info {
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2016-07-13 23:03:40 +08:00
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const char *name;
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2017-04-10 22:34:32 +08:00
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int (*init_legacy)(struct intel_engine_cs *engine);
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int (*init_execlists)(struct intel_engine_cs *engine);
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2017-11-10 22:26:27 +08:00
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u8 uabi_class;
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2017-04-10 22:34:32 +08:00
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};
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static const struct engine_class_info intel_engine_classes[] = {
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[RENDER_CLASS] = {
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.name = "rcs",
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.init_execlists = logical_render_ring_init,
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.init_legacy = intel_init_render_ring_buffer,
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2017-11-10 22:26:27 +08:00
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.uabi_class = I915_ENGINE_CLASS_RENDER,
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2017-04-10 22:34:32 +08:00
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},
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[COPY_ENGINE_CLASS] = {
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.name = "bcs",
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_blt_ring_buffer,
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2017-11-10 22:26:27 +08:00
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.uabi_class = I915_ENGINE_CLASS_COPY,
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2017-04-10 22:34:32 +08:00
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},
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[VIDEO_DECODE_CLASS] = {
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.name = "vcs",
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_bsd_ring_buffer,
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2017-11-10 22:26:27 +08:00
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.uabi_class = I915_ENGINE_CLASS_VIDEO,
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2017-04-10 22:34:32 +08:00
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},
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[VIDEO_ENHANCEMENT_CLASS] = {
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.name = "vecs",
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_vebox_ring_buffer,
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2017-11-10 22:26:27 +08:00
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.uabi_class = I915_ENGINE_CLASS_VIDEO_ENHANCE,
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2017-04-10 22:34:32 +08:00
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},
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};
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2018-03-15 02:26:50 +08:00
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#define MAX_MMIO_BASES 3
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2017-04-10 22:34:32 +08:00
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struct engine_info {
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2017-03-02 04:26:15 +08:00
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unsigned int hw_id;
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2017-04-11 20:43:06 +08:00
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unsigned int uabi_id;
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2017-04-10 22:34:29 +08:00
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u8 class;
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u8 instance;
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2018-03-15 02:26:50 +08:00
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/* mmio bases table *must* be sorted in reverse gen order */
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struct engine_mmio_base {
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u32 gen : 8;
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u32 base : 24;
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} mmio_bases[MAX_MMIO_BASES];
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2017-04-10 22:34:32 +08:00
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};
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static const struct engine_info intel_engines[] = {
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2016-07-13 23:03:40 +08:00
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[RCS] = {
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2016-08-17 00:04:20 +08:00
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.hw_id = RCS_HW,
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2017-04-11 20:43:06 +08:00
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.uabi_id = I915_EXEC_RENDER,
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2017-04-10 22:34:29 +08:00
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.class = RENDER_CLASS,
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.instance = 0,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 1, .base = RENDER_RING_BASE }
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},
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2016-07-13 23:03:40 +08:00
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},
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[BCS] = {
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2016-08-17 00:04:20 +08:00
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.hw_id = BCS_HW,
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2017-04-11 20:43:06 +08:00
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.uabi_id = I915_EXEC_BLT,
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2017-04-10 22:34:29 +08:00
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.class = COPY_ENGINE_CLASS,
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.instance = 0,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 6, .base = BLT_RING_BASE }
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},
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2016-07-13 23:03:40 +08:00
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},
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[VCS] = {
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2016-08-17 00:04:20 +08:00
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.hw_id = VCS_HW,
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2017-04-11 20:43:06 +08:00
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.uabi_id = I915_EXEC_BSD,
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2017-04-10 22:34:29 +08:00
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.class = VIDEO_DECODE_CLASS,
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.instance = 0,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD_RING_BASE },
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{ .gen = 6, .base = GEN6_BSD_RING_BASE },
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{ .gen = 4, .base = BSD_RING_BASE }
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},
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2016-07-13 23:03:40 +08:00
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},
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[VCS2] = {
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2016-08-17 00:04:20 +08:00
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.hw_id = VCS2_HW,
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2017-04-11 20:43:06 +08:00
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.uabi_id = I915_EXEC_BSD,
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2017-04-10 22:34:29 +08:00
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.class = VIDEO_DECODE_CLASS,
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.instance = 1,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD2_RING_BASE },
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{ .gen = 8, .base = GEN8_BSD2_RING_BASE }
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},
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2016-07-13 23:03:40 +08:00
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},
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2018-03-03 00:14:57 +08:00
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[VCS3] = {
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.hw_id = VCS3_HW,
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.uabi_id = I915_EXEC_BSD,
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.class = VIDEO_DECODE_CLASS,
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.instance = 2,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD3_RING_BASE }
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},
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2018-03-03 00:14:57 +08:00
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},
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[VCS4] = {
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.hw_id = VCS4_HW,
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.uabi_id = I915_EXEC_BSD,
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.class = VIDEO_DECODE_CLASS,
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.instance = 3,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD4_RING_BASE }
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},
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2018-03-03 00:14:57 +08:00
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},
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2016-07-13 23:03:40 +08:00
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[VECS] = {
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2016-08-17 00:04:20 +08:00
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.hw_id = VECS_HW,
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2017-04-11 20:43:06 +08:00
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.uabi_id = I915_EXEC_VEBOX,
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2017-04-10 22:34:29 +08:00
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.class = VIDEO_ENHANCEMENT_CLASS,
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.instance = 0,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },
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{ .gen = 7, .base = VEBOX_RING_BASE }
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},
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2016-07-13 23:03:40 +08:00
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},
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2018-03-03 00:14:57 +08:00
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[VECS2] = {
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.hw_id = VECS2_HW,
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.uabi_id = I915_EXEC_VEBOX,
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.class = VIDEO_ENHANCEMENT_CLASS,
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.instance = 1,
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2018-03-15 02:26:50 +08:00
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
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},
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2018-03-03 00:14:57 +08:00
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},
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2016-07-13 23:03:40 +08:00
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};
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2017-04-28 15:53:36 +08:00
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/**
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* ___intel_engine_context_size() - return the size of the context for an engine
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* @dev_priv: i915 device private
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* @class: engine class
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*
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* Each engine class may require a different amount of space for a context
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* image.
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*
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* Return: size (in bytes) of an engine class specific context image
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*
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* Note: this size includes the HWSP, which is part of the context image
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* in LRC mode, but does not include the "shared data page" used with
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* GuC submission. The caller should account for this if using the GuC.
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*/
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static u32
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__intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
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{
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u32 cxt_size;
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BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
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switch (class) {
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case RENDER_CLASS:
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switch (INTEL_GEN(dev_priv)) {
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default:
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MISSING_CASE(INTEL_GEN(dev_priv));
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2018-01-12 06:55:06 +08:00
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return DEFAULT_LR_CONTEXT_RENDER_SIZE;
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2018-01-12 06:55:07 +08:00
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case 11:
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return GEN11_LR_CONTEXT_RENDER_SIZE;
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2017-07-07 05:06:24 +08:00
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case 10:
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2017-09-22 07:19:49 +08:00
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return GEN10_LR_CONTEXT_RENDER_SIZE;
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2017-04-28 15:53:36 +08:00
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case 9:
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return GEN9_LR_CONTEXT_RENDER_SIZE;
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case 8:
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2017-11-21 04:55:00 +08:00
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return GEN8_LR_CONTEXT_RENDER_SIZE;
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2017-04-28 15:53:36 +08:00
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case 7:
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if (IS_HASWELL(dev_priv))
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return HSW_CXT_TOTAL_SIZE;
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cxt_size = I915_READ(GEN7_CXT_SIZE);
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return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
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PAGE_SIZE);
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case 6:
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cxt_size = I915_READ(CXT_SIZE);
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return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
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PAGE_SIZE);
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case 5:
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case 4:
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case 3:
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case 2:
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/* For the special day when i810 gets merged. */
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case 1:
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return 0;
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}
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break;
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default:
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MISSING_CASE(class);
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2018-06-29 06:35:41 +08:00
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/* fall through */
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2017-04-28 15:53:36 +08:00
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case VIDEO_DECODE_CLASS:
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case VIDEO_ENHANCEMENT_CLASS:
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case COPY_ENGINE_CLASS:
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if (INTEL_GEN(dev_priv) < 8)
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return 0;
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return GEN8_LR_CONTEXT_OTHER_SIZE;
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}
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}
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2018-03-15 02:26:50 +08:00
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static u32 __engine_mmio_base(struct drm_i915_private *i915,
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const struct engine_mmio_base *bases)
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{
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int i;
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for (i = 0; i < MAX_MMIO_BASES; i++)
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if (INTEL_GEN(i915) >= bases[i].gen)
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break;
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GEM_BUG_ON(i == MAX_MMIO_BASES);
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GEM_BUG_ON(!bases[i].base);
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return bases[i].base;
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}
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2018-03-15 02:26:51 +08:00
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static void __sprint_engine_name(char *name, const struct engine_info *info)
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{
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WARN_ON(snprintf(name, INTEL_ENGINE_CS_MAX_NAME, "%s%u",
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intel_engine_classes[info->class].name,
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info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
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}
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drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
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static int
|
2016-07-13 23:03:40 +08:00
|
|
|
intel_engine_setup(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_engine_id id)
|
|
|
|
{
|
|
|
|
const struct engine_info *info = &intel_engines[id];
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
|
2017-04-10 22:34:32 +08:00
|
|
|
GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
|
|
|
|
|
2018-03-03 00:14:58 +08:00
|
|
|
BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
|
|
|
|
BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
|
|
|
|
|
drm/i915/pmu: Expose a PMU interface for perf queries
From: Chris Wilson <chris@chris-wilson.co.uk>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
From: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system, but also
runs the risk of hanging the machine.) As an alternative we can use the
perf event counter interface to sample the ring registers periodically
and send those results to userspace.
Functionality we are exporting to userspace is via the existing perf PMU
API and can be exercised via the existing tools. For example:
perf stat -a -e i915/rcs0-busy/ -I 1000
Will print the render engine busynnes once per second. All the performance
counters can be enumerated (perf list) and have their unit of measure
correctly reported in sysfs.
v1-v2 (Chris Wilson):
v2: Use a common timer for the ring sampling.
v3: (Tvrtko Ursulin)
* Decouple uAPI from i915 engine ids.
* Complete uAPI defines.
* Refactor some code to helpers for clarity.
* Skip sampling disabled engines.
* Expose counters in sysfs.
* Pass in fake regs to avoid null ptr deref in perf core.
* Convert to class/instance uAPI.
* Use shared driver code for rc6 residency, power and frequency.
v4: (Dmitry Rogozhkin)
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)
* Introduce refcounting of event subscriptions.
* Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.
* Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.
* Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.
* End result is that only global events are supported and perf stat
works correctly.
* Deny perf driver level sampling - it is prohibited for uncore PMU.
v5: (Tvrtko Ursulin)
* Don't hardcode number of engine samplers.
* Rewrite event ref-counting for correctness and simplicity.
* Store initial counter value when starting already enabled events
to correctly report values to all listeners.
* Fix RC6 residency readout.
* Comments, GPL header.
v6:
* Add missing entry to v4 changelog.
* Fix accounting in CPU hotplug case by copying the approach from
arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin)
v7:
* Log failure message only on failure.
* Remove CPU hotplug notification state on unregister.
v8:
* Fix error unwind on failed registration.
* Checkpatch cleanup.
v9:
* Drop the energy metric, it is available via intel_rapl_perf.
(Ville Syrjälä)
* Use HAS_RC6(p). (Chris Wilson)
* Handle unsupported non-engine events. (Dmitry Rogozhkin)
* Rebase for intel_rc6_residency_ns needing caller managed
runtime pm.
* Drop HAS_RC6 checks from the read callback since creating those
events will be rejected at init time already.
* Add counter units to sysfs so perf stat output is nicer.
* Cleanup the attribute tables for brevity and readability.
v10:
* Fixed queued accounting.
v11:
* Move intel_engine_lookup_user to intel_engine_cs.c
* Commit update. (Joonas Lahtinen)
v12:
* More accurate sampling. (Chris Wilson)
* Store and report frequency in MHz for better usability from
perf stat.
* Removed metrics: queued, interrupts, rc6 counters.
* Sample engine busyness based on seqno difference only
for less MMIO (and forcewake) on all platforms. (Chris Wilson)
v13:
* Comment spelling, use mul_u32_u32 to work around potential GCC
issue and somne code alignment changes. (Chris Wilson)
v14:
* Rebase.
v15:
* Rebase for RPS refactoring.
v16:
* Use the dynamic slot in the CPU hotplug state machine so that we are
free to setup our state as multi-instance. Previously we were re-using
the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as
multi-instance, nor owned by our driver to start with.
* Register the CPU hotplug handlers after the PMU, otherwise the callback
will get called before the PMU is initialized which can end up in
perf_pmu_migrate_context with an un-initialized base.
* Added workaround for a probable bug in cpuhp core.
v17:
* Remove workaround for the cpuhp bug.
v18:
* Rebase for drm_i915_gem_engine_class getting upstream before us.
v19:
* Rebase. (trivial)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com
2017-11-22 02:18:45 +08:00
|
|
|
if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (GEM_WARN_ON(dev_priv->engine_class[info->class][info->instance]))
|
|
|
|
return -EINVAL;
|
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
|
|
|
GEM_BUG_ON(dev_priv->engine[id]);
|
|
|
|
engine = kzalloc(sizeof(*engine), GFP_KERNEL);
|
|
|
|
if (!engine)
|
|
|
|
return -ENOMEM;
|
2016-07-13 23:03:40 +08:00
|
|
|
|
|
|
|
engine->id = id;
|
|
|
|
engine->i915 = dev_priv;
|
2018-03-15 02:26:51 +08:00
|
|
|
__sprint_engine_name(engine->name, info);
|
2016-08-17 00:04:20 +08:00
|
|
|
engine->hw_id = engine->guc_id = info->hw_id;
|
2018-03-15 02:26:50 +08:00
|
|
|
engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);
|
2017-04-10 22:34:29 +08:00
|
|
|
engine->class = info->class;
|
|
|
|
engine->instance = info->instance;
|
2016-07-13 23:03:40 +08:00
|
|
|
|
2017-11-10 22:26:27 +08:00
|
|
|
engine->uabi_id = info->uabi_id;
|
2018-03-15 02:26:51 +08:00
|
|
|
engine->uabi_class = intel_engine_classes[info->class].uabi_class;
|
2017-11-10 22:26:27 +08:00
|
|
|
|
2017-04-28 15:53:36 +08:00
|
|
|
engine->context_size = __intel_engine_context_size(dev_priv,
|
|
|
|
engine->class);
|
|
|
|
if (WARN_ON(engine->context_size > BIT(20)))
|
|
|
|
engine->context_size = 0;
|
2018-07-06 18:14:41 +08:00
|
|
|
if (engine->context_size)
|
|
|
|
DRIVER_CAPS(dev_priv)->has_logical_contexts = true;
|
2017-04-28 15:53:36 +08:00
|
|
|
|
2016-11-15 04:41:01 +08:00
|
|
|
/* Nothing to do here, execute in order of dependencies */
|
|
|
|
engine->schedule = NULL;
|
|
|
|
|
2018-04-26 15:47:16 +08:00
|
|
|
seqlock_init(&engine->stats.lock);
|
2017-11-22 02:18:48 +08:00
|
|
|
|
2017-03-13 10:47:11 +08:00
|
|
|
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
|
|
|
|
|
drm/i915/pmu: Expose a PMU interface for perf queries
From: Chris Wilson <chris@chris-wilson.co.uk>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
From: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system, but also
runs the risk of hanging the machine.) As an alternative we can use the
perf event counter interface to sample the ring registers periodically
and send those results to userspace.
Functionality we are exporting to userspace is via the existing perf PMU
API and can be exercised via the existing tools. For example:
perf stat -a -e i915/rcs0-busy/ -I 1000
Will print the render engine busynnes once per second. All the performance
counters can be enumerated (perf list) and have their unit of measure
correctly reported in sysfs.
v1-v2 (Chris Wilson):
v2: Use a common timer for the ring sampling.
v3: (Tvrtko Ursulin)
* Decouple uAPI from i915 engine ids.
* Complete uAPI defines.
* Refactor some code to helpers for clarity.
* Skip sampling disabled engines.
* Expose counters in sysfs.
* Pass in fake regs to avoid null ptr deref in perf core.
* Convert to class/instance uAPI.
* Use shared driver code for rc6 residency, power and frequency.
v4: (Dmitry Rogozhkin)
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)
* Introduce refcounting of event subscriptions.
* Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.
* Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.
* Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.
* End result is that only global events are supported and perf stat
works correctly.
* Deny perf driver level sampling - it is prohibited for uncore PMU.
v5: (Tvrtko Ursulin)
* Don't hardcode number of engine samplers.
* Rewrite event ref-counting for correctness and simplicity.
* Store initial counter value when starting already enabled events
to correctly report values to all listeners.
* Fix RC6 residency readout.
* Comments, GPL header.
v6:
* Add missing entry to v4 changelog.
* Fix accounting in CPU hotplug case by copying the approach from
arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin)
v7:
* Log failure message only on failure.
* Remove CPU hotplug notification state on unregister.
v8:
* Fix error unwind on failed registration.
* Checkpatch cleanup.
v9:
* Drop the energy metric, it is available via intel_rapl_perf.
(Ville Syrjälä)
* Use HAS_RC6(p). (Chris Wilson)
* Handle unsupported non-engine events. (Dmitry Rogozhkin)
* Rebase for intel_rc6_residency_ns needing caller managed
runtime pm.
* Drop HAS_RC6 checks from the read callback since creating those
events will be rejected at init time already.
* Add counter units to sysfs so perf stat output is nicer.
* Cleanup the attribute tables for brevity and readability.
v10:
* Fixed queued accounting.
v11:
* Move intel_engine_lookup_user to intel_engine_cs.c
* Commit update. (Joonas Lahtinen)
v12:
* More accurate sampling. (Chris Wilson)
* Store and report frequency in MHz for better usability from
perf stat.
* Removed metrics: queued, interrupts, rc6 counters.
* Sample engine busyness based on seqno difference only
for less MMIO (and forcewake) on all platforms. (Chris Wilson)
v13:
* Comment spelling, use mul_u32_u32 to work around potential GCC
issue and somne code alignment changes. (Chris Wilson)
v14:
* Rebase.
v15:
* Rebase for RPS refactoring.
v16:
* Use the dynamic slot in the CPU hotplug state machine so that we are
free to setup our state as multi-instance. Previously we were re-using
the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as
multi-instance, nor owned by our driver to start with.
* Register the CPU hotplug handlers after the PMU, otherwise the callback
will get called before the PMU is initialized which can end up in
perf_pmu_migrate_context with an un-initialized base.
* Added workaround for a probable bug in cpuhp core.
v17:
* Remove workaround for the cpuhp bug.
v18:
* Rebase for drm_i915_gem_engine_class getting upstream before us.
v19:
* Rebase. (trivial)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com
2017-11-22 02:18:45 +08:00
|
|
|
dev_priv->engine_class[info->class][info->instance] = engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
|
|
|
dev_priv->engine[id] = engine;
|
|
|
|
return 0;
|
2016-07-13 23:03:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2017-04-28 15:53:36 +08:00
|
|
|
* intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
|
2016-12-01 22:16:38 +08:00
|
|
|
* @dev_priv: i915 device private
|
2016-07-13 23:03:40 +08:00
|
|
|
*
|
|
|
|
* Return: non-zero if the initialization failed.
|
|
|
|
*/
|
2017-04-28 15:53:36 +08:00
|
|
|
int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
|
2016-07-13 23:03:40 +08:00
|
|
|
{
|
2016-08-10 23:22:10 +08:00
|
|
|
struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
|
2017-04-12 00:56:58 +08:00
|
|
|
const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
2017-04-12 00:56:58 +08:00
|
|
|
unsigned int mask = 0;
|
2016-07-13 23:03:40 +08:00
|
|
|
unsigned int i;
|
2017-01-24 19:01:34 +08:00
|
|
|
int err;
|
2016-07-13 23:03:40 +08:00
|
|
|
|
2016-10-13 18:02:56 +08:00
|
|
|
WARN_ON(ring_mask == 0);
|
|
|
|
WARN_ON(ring_mask &
|
2018-09-26 18:47:07 +08:00
|
|
|
GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
|
2016-07-13 23:03:40 +08:00
|
|
|
|
2018-10-11 21:00:08 +08:00
|
|
|
if (i915_inject_load_failure())
|
|
|
|
return -ENODEV;
|
|
|
|
|
2016-07-13 23:03:40 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
|
|
|
|
if (!HAS_ENGINE(dev_priv, i))
|
|
|
|
continue;
|
|
|
|
|
2017-01-24 19:01:34 +08:00
|
|
|
err = intel_engine_setup(dev_priv, i);
|
|
|
|
if (err)
|
|
|
|
goto cleanup;
|
|
|
|
|
|
|
|
mask |= ENGINE_MASK(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Catch failures to update intel_engines table when the new engines
|
|
|
|
* are added to the driver by a warning and disabling the forgotten
|
|
|
|
* engines.
|
|
|
|
*/
|
|
|
|
if (WARN_ON(mask != ring_mask))
|
|
|
|
device_info->ring_mask = mask;
|
|
|
|
|
2017-04-12 00:56:58 +08:00
|
|
|
/* We always presume we have at least RCS available for later probing */
|
|
|
|
if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
|
|
|
|
err = -ENODEV;
|
|
|
|
goto cleanup;
|
|
|
|
}
|
|
|
|
|
2017-01-24 19:01:34 +08:00
|
|
|
device_info->num_rings = hweight32(mask);
|
|
|
|
|
2017-11-11 08:44:47 +08:00
|
|
|
i915_check_and_clear_faults(dev_priv);
|
|
|
|
|
2017-01-24 19:01:34 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
cleanup:
|
|
|
|
for_each_engine(engine, dev_priv, id)
|
|
|
|
kfree(engine);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2017-04-28 15:53:36 +08:00
|
|
|
* intel_engines_init() - init the Engine Command Streamers
|
2017-01-24 19:01:34 +08:00
|
|
|
* @dev_priv: i915 device private
|
|
|
|
*
|
|
|
|
* Return: non-zero if the initialization failed.
|
|
|
|
*/
|
|
|
|
int intel_engines_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id, err_id;
|
2017-06-16 21:03:38 +08:00
|
|
|
int err;
|
2017-01-24 19:01:34 +08:00
|
|
|
|
|
|
|
for_each_engine(engine, dev_priv, id) {
|
2017-04-10 22:34:32 +08:00
|
|
|
const struct engine_class_info *class_info =
|
|
|
|
&intel_engine_classes[engine->class];
|
2017-01-24 19:01:34 +08:00
|
|
|
int (*init)(struct intel_engine_cs *engine);
|
|
|
|
|
2017-11-21 04:55:00 +08:00
|
|
|
if (HAS_EXECLISTS(dev_priv))
|
2017-04-10 22:34:32 +08:00
|
|
|
init = class_info->init_execlists;
|
2016-07-13 23:03:40 +08:00
|
|
|
else
|
2017-04-10 22:34:32 +08:00
|
|
|
init = class_info->init_legacy;
|
2017-06-16 21:03:38 +08:00
|
|
|
|
|
|
|
err = -EINVAL;
|
|
|
|
err_id = id;
|
|
|
|
|
|
|
|
if (GEM_WARN_ON(!init))
|
|
|
|
goto cleanup;
|
2016-07-13 23:03:40 +08:00
|
|
|
|
2017-01-24 19:01:34 +08:00
|
|
|
err = init(engine);
|
2017-06-16 21:03:38 +08:00
|
|
|
if (err)
|
2016-07-13 23:03:40 +08:00
|
|
|
goto cleanup;
|
|
|
|
|
2017-03-17 01:13:03 +08:00
|
|
|
GEM_BUG_ON(!engine->submit_request);
|
2016-07-13 23:03:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cleanup:
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
|
|
|
for_each_engine(engine, dev_priv, id) {
|
2017-06-16 21:03:38 +08:00
|
|
|
if (id >= err_id) {
|
2017-01-24 19:01:34 +08:00
|
|
|
kfree(engine);
|
2017-06-16 21:03:38 +08:00
|
|
|
dev_priv->engine[id] = NULL;
|
|
|
|
} else {
|
2017-02-16 20:23:22 +08:00
|
|
|
dev_priv->gt.cleanup_engine(engine);
|
2017-06-16 21:03:38 +08:00
|
|
|
}
|
2016-07-13 23:03:40 +08:00
|
|
|
}
|
2017-01-24 19:01:34 +08:00
|
|
|
return err;
|
2016-07-13 23:03:40 +08:00
|
|
|
}
|
|
|
|
|
2016-10-28 20:58:46 +08:00
|
|
|
void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
|
2016-08-15 17:49:00 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
|
|
|
|
/* Our semaphore implementation is strictly monotonic (i.e. we proceed
|
|
|
|
* so long as the semaphore value in the register/page is greater
|
|
|
|
* than the sync value), so whenever we reset the seqno,
|
|
|
|
* so long as we reset the tracking semaphore value to 0, it will
|
|
|
|
* always be before the next request's seqno. If we don't reset
|
|
|
|
* the semaphore value, then when the seqno moves backwards all
|
|
|
|
* future waits will complete instantly (causing rendering corruption).
|
|
|
|
*/
|
|
|
|
if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
|
|
|
|
I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
|
|
|
|
I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
|
|
|
|
if (HAS_VEBOX(dev_priv))
|
|
|
|
I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
|
2017-03-14 19:14:52 +08:00
|
|
|
clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
|
2016-10-28 20:58:46 +08:00
|
|
|
|
2016-08-15 17:49:00 +08:00
|
|
|
/* After manually advancing the seqno, fake the interrupt in case
|
|
|
|
* there are any waiters for that seqno.
|
|
|
|
*/
|
|
|
|
intel_engine_wakeup(engine);
|
2017-04-05 23:30:54 +08:00
|
|
|
|
|
|
|
GEM_BUG_ON(intel_engine_get_seqno(engine) != seqno);
|
2016-08-15 17:49:00 +08:00
|
|
|
}
|
|
|
|
|
2018-03-08 17:50:35 +08:00
|
|
|
static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
i915_gem_batch_pool_init(&engine->batch_pool, engine);
|
|
|
|
}
|
|
|
|
|
2017-09-22 20:43:04 +08:00
|
|
|
static void intel_engine_init_execlist(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct intel_engine_execlists * const execlists = &engine->execlists;
|
|
|
|
|
2017-09-22 20:43:07 +08:00
|
|
|
execlists->port_mask = 1;
|
2018-10-16 20:29:38 +08:00
|
|
|
GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
|
2017-09-22 20:43:07 +08:00
|
|
|
GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
|
|
|
|
|
2018-02-22 22:22:29 +08:00
|
|
|
execlists->queue_priority = INT_MIN;
|
2018-06-29 15:53:20 +08:00
|
|
|
execlists->queue = RB_ROOT_CACHED;
|
2017-09-22 20:43:04 +08:00
|
|
|
}
|
|
|
|
|
2016-07-13 23:03:41 +08:00
|
|
|
/**
|
|
|
|
* intel_engines_setup_common - setup engine state not requiring hw access
|
|
|
|
* @engine: Engine to setup.
|
|
|
|
*
|
|
|
|
* Initializes @engine@ structure members shared between legacy and execlists
|
|
|
|
* submission modes which do not require hardware access.
|
|
|
|
*
|
|
|
|
* Typically done early in the submission mode specific engine setup stage.
|
|
|
|
*/
|
|
|
|
void intel_engine_setup_common(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-05-03 00:38:39 +08:00
|
|
|
i915_timeline_init(engine->i915, &engine->timeline, engine->name);
|
2018-07-07 05:07:10 +08:00
|
|
|
lockdep_set_subclass(&engine->timeline.lock, TIMELINE_ENGINE);
|
2018-05-03 00:38:39 +08:00
|
|
|
|
2017-09-22 20:43:04 +08:00
|
|
|
intel_engine_init_execlist(engine);
|
2016-07-13 23:03:41 +08:00
|
|
|
intel_engine_init_hangcheck(engine);
|
2018-03-08 17:50:35 +08:00
|
|
|
intel_engine_init_batch_pool(engine);
|
2016-08-19 00:17:10 +08:00
|
|
|
intel_engine_init_cmd_parser(engine);
|
2016-07-13 23:03:41 +08:00
|
|
|
}
|
|
|
|
|
2018-06-12 01:18:25 +08:00
|
|
|
int intel_engine_create_scratch(struct intel_engine_cs *engine,
|
|
|
|
unsigned int size)
|
2016-08-15 17:48:59 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct i915_vma *vma;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
WARN_ON(engine->scratch);
|
|
|
|
|
2016-12-01 22:16:36 +08:00
|
|
|
obj = i915_gem_object_create_stolen(engine->i915, size);
|
2016-08-15 17:48:59 +08:00
|
|
|
if (!obj)
|
2016-10-28 20:58:30 +08:00
|
|
|
obj = i915_gem_object_create_internal(engine->i915, size);
|
2016-08-15 17:48:59 +08:00
|
|
|
if (IS_ERR(obj)) {
|
|
|
|
DRM_ERROR("Failed to allocate scratch page\n");
|
|
|
|
return PTR_ERR(obj);
|
|
|
|
}
|
|
|
|
|
2018-06-05 23:37:58 +08:00
|
|
|
vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
|
2016-08-15 17:48:59 +08:00
|
|
|
if (IS_ERR(vma)) {
|
|
|
|
ret = PTR_ERR(vma);
|
|
|
|
goto err_unref;
|
|
|
|
}
|
|
|
|
|
2018-07-27 17:18:55 +08:00
|
|
|
ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
|
2016-08-15 17:48:59 +08:00
|
|
|
if (ret)
|
|
|
|
goto err_unref;
|
|
|
|
|
|
|
|
engine->scratch = vma;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unref:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-06-12 01:18:25 +08:00
|
|
|
void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
|
2016-08-15 17:48:59 +08:00
|
|
|
{
|
2018-07-21 20:50:37 +08:00
|
|
|
i915_vma_unpin_and_release(&engine->scratch, 0);
|
2016-08-15 17:48:59 +08:00
|
|
|
}
|
|
|
|
|
2018-09-03 23:23:03 +08:00
|
|
|
static void cleanup_status_page(struct intel_engine_cs *engine)
|
2017-09-13 16:56:02 +08:00
|
|
|
{
|
2018-09-03 23:23:04 +08:00
|
|
|
if (HWS_NEEDS_PHYSICAL(engine->i915)) {
|
|
|
|
void *addr = fetch_and_zero(&engine->status_page.page_addr);
|
2017-09-13 16:56:02 +08:00
|
|
|
|
2018-09-03 23:23:04 +08:00
|
|
|
__free_page(virt_to_page(addr));
|
|
|
|
}
|
2017-09-13 16:56:02 +08:00
|
|
|
|
2018-07-21 20:50:37 +08:00
|
|
|
i915_vma_unpin_and_release(&engine->status_page.vma,
|
|
|
|
I915_VMA_RELEASE_MAP);
|
2017-09-13 16:56:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int init_status_page(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct i915_vma *vma;
|
|
|
|
unsigned int flags;
|
|
|
|
void *vaddr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
|
|
|
|
if (IS_ERR(obj)) {
|
|
|
|
DRM_ERROR("Failed to allocate status page\n");
|
|
|
|
return PTR_ERR(obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
2018-06-05 23:37:58 +08:00
|
|
|
vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
|
2017-09-13 16:56:02 +08:00
|
|
|
if (IS_ERR(vma)) {
|
|
|
|
ret = PTR_ERR(vma);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
flags = PIN_GLOBAL;
|
|
|
|
if (!HAS_LLC(engine->i915))
|
|
|
|
/* On g33, we cannot place HWS above 256MiB, so
|
|
|
|
* restrict its pinning to the low mappable arena.
|
|
|
|
* Though this restriction is not documented for
|
|
|
|
* gen4, gen5, or byt, they also behave similarly
|
|
|
|
* and hang if the HWS is placed at the top of the
|
|
|
|
* GTT. To generalise, it appears that all !llc
|
|
|
|
* platforms have issues with us placing the HWS
|
|
|
|
* above the mappable region (even though we never
|
|
|
|
* actually map it).
|
|
|
|
*/
|
|
|
|
flags |= PIN_MAPPABLE;
|
2017-09-13 16:56:03 +08:00
|
|
|
else
|
|
|
|
flags |= PIN_HIGH;
|
2018-07-27 17:18:55 +08:00
|
|
|
ret = i915_vma_pin(vma, 0, 0, flags);
|
2017-09-13 16:56:02 +08:00
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
|
|
|
|
if (IS_ERR(vaddr)) {
|
|
|
|
ret = PTR_ERR(vaddr);
|
|
|
|
goto err_unpin;
|
|
|
|
}
|
|
|
|
|
|
|
|
engine->status_page.vma = vma;
|
|
|
|
engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
|
|
|
|
engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unpin:
|
|
|
|
i915_vma_unpin(vma);
|
|
|
|
err:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int init_phys_status_page(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-09-03 23:23:04 +08:00
|
|
|
struct page *page;
|
2017-09-13 16:56:02 +08:00
|
|
|
|
2018-09-03 23:23:04 +08:00
|
|
|
/*
|
|
|
|
* Though the HWS register does support 36bit addresses, historically
|
|
|
|
* we have had hangs and corruption reported due to wild writes if
|
|
|
|
* the HWS is placed above 4G.
|
|
|
|
*/
|
|
|
|
page = alloc_page(GFP_KERNEL | __GFP_DMA32 | __GFP_ZERO);
|
|
|
|
if (!page)
|
2017-09-13 16:56:02 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2018-09-03 23:23:04 +08:00
|
|
|
engine->status_page.page_addr = page_address(page);
|
2017-09-13 16:56:02 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-05-18 05:26:32 +08:00
|
|
|
static void __intel_context_unpin(struct i915_gem_context *ctx,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
intel_context_unpin(to_intel_context(ctx, engine));
|
|
|
|
}
|
|
|
|
|
2016-07-13 23:03:41 +08:00
|
|
|
/**
|
|
|
|
* intel_engines_init_common - initialize cengine state which might require hw access
|
|
|
|
* @engine: Engine to initialize.
|
|
|
|
*
|
|
|
|
* Initializes @engine@ structure members shared between legacy and execlists
|
|
|
|
* submission modes which do require hardware access.
|
|
|
|
*
|
|
|
|
* Typcally done at later stages of submission mode specific engine setup.
|
|
|
|
*
|
|
|
|
* Returns zero on success or an error code on failure.
|
|
|
|
*/
|
|
|
|
int intel_engine_init_common(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-05-18 05:26:32 +08:00
|
|
|
struct drm_i915_private *i915 = engine->i915;
|
|
|
|
struct intel_context *ce;
|
2016-07-13 23:03:41 +08:00
|
|
|
int ret;
|
|
|
|
|
2017-03-17 01:13:03 +08:00
|
|
|
engine->set_default_submission(engine);
|
|
|
|
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 23:37:20 +08:00
|
|
|
/* We may need to do things with the shrinker which
|
|
|
|
* require us to immediately switch back to the default
|
|
|
|
* context. This can cause a problem as pinning the
|
|
|
|
* default context also requires GTT space which may not
|
|
|
|
* be available. To avoid this we always pin the default
|
|
|
|
* context.
|
|
|
|
*/
|
2018-05-18 05:26:32 +08:00
|
|
|
ce = intel_context_pin(i915->kernel_context, engine);
|
|
|
|
if (IS_ERR(ce))
|
|
|
|
return PTR_ERR(ce);
|
2016-07-13 23:03:41 +08:00
|
|
|
|
2017-10-04 04:34:48 +08:00
|
|
|
/*
|
|
|
|
* Similarly the preempt context must always be available so that
|
|
|
|
* we can interrupt the engine at any time.
|
|
|
|
*/
|
2018-05-18 05:26:32 +08:00
|
|
|
if (i915->preempt_context) {
|
|
|
|
ce = intel_context_pin(i915->preempt_context, engine);
|
|
|
|
if (IS_ERR(ce)) {
|
|
|
|
ret = PTR_ERR(ce);
|
2017-10-04 04:34:48 +08:00
|
|
|
goto err_unpin_kernel;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 23:37:20 +08:00
|
|
|
ret = intel_engine_init_breadcrumbs(engine);
|
|
|
|
if (ret)
|
2017-10-04 04:34:48 +08:00
|
|
|
goto err_unpin_preempt;
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 23:37:20 +08:00
|
|
|
|
2018-05-18 05:26:32 +08:00
|
|
|
if (HWS_NEEDS_PHYSICAL(i915))
|
2017-09-13 16:56:02 +08:00
|
|
|
ret = init_phys_status_page(engine);
|
|
|
|
else
|
|
|
|
ret = init_status_page(engine);
|
|
|
|
if (ret)
|
2017-11-10 22:26:34 +08:00
|
|
|
goto err_breadcrumbs;
|
2016-10-28 20:58:31 +08:00
|
|
|
|
2016-08-19 00:17:10 +08:00
|
|
|
return 0;
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 23:37:20 +08:00
|
|
|
|
2017-09-13 16:56:02 +08:00
|
|
|
err_breadcrumbs:
|
|
|
|
intel_engine_fini_breadcrumbs(engine);
|
2017-10-04 04:34:48 +08:00
|
|
|
err_unpin_preempt:
|
2018-05-18 05:26:32 +08:00
|
|
|
if (i915->preempt_context)
|
|
|
|
__intel_context_unpin(i915->preempt_context, engine);
|
|
|
|
|
2017-10-04 04:34:48 +08:00
|
|
|
err_unpin_kernel:
|
2018-05-18 05:26:32 +08:00
|
|
|
__intel_context_unpin(i915->kernel_context, engine);
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 23:37:20 +08:00
|
|
|
return ret;
|
2016-07-13 23:03:41 +08:00
|
|
|
}
|
2016-08-03 20:19:16 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_engines_cleanup_common - cleans up the engine state created by
|
|
|
|
* the common initiailizers.
|
|
|
|
* @engine: Engine to cleanup.
|
|
|
|
*
|
|
|
|
* This cleans up everything created by the common helpers.
|
|
|
|
*/
|
|
|
|
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-05-18 05:26:32 +08:00
|
|
|
struct drm_i915_private *i915 = engine->i915;
|
|
|
|
|
2016-08-15 17:48:59 +08:00
|
|
|
intel_engine_cleanup_scratch(engine);
|
|
|
|
|
2018-09-03 23:23:03 +08:00
|
|
|
cleanup_status_page(engine);
|
2017-09-13 16:56:02 +08:00
|
|
|
|
2016-08-03 20:19:16 +08:00
|
|
|
intel_engine_fini_breadcrumbs(engine);
|
2016-08-19 00:17:10 +08:00
|
|
|
intel_engine_cleanup_cmd_parser(engine);
|
2016-08-03 20:19:16 +08:00
|
|
|
i915_gem_batch_pool_fini(&engine->batch_pool);
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 23:37:20 +08:00
|
|
|
|
2017-11-10 22:26:33 +08:00
|
|
|
if (engine->default_state)
|
|
|
|
i915_gem_object_put(engine->default_state);
|
|
|
|
|
2018-05-18 05:26:32 +08:00
|
|
|
if (i915->preempt_context)
|
|
|
|
__intel_context_unpin(i915->preempt_context, engine);
|
|
|
|
__intel_context_unpin(i915->kernel_context, engine);
|
2018-05-03 00:38:39 +08:00
|
|
|
|
|
|
|
i915_timeline_fini(&engine->timeline);
|
2016-08-03 20:19:16 +08:00
|
|
|
}
|
2016-10-05 04:11:31 +08:00
|
|
|
|
2018-02-12 18:24:15 +08:00
|
|
|
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
|
2016-10-05 04:11:31 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
u64 acthd;
|
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
|
|
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
|
|
|
|
RING_ACTHD_UDW(engine->mmio_base));
|
|
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
|
|
|
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
|
|
|
|
else
|
|
|
|
acthd = I915_READ(ACTHD);
|
|
|
|
|
|
|
|
return acthd;
|
|
|
|
}
|
|
|
|
|
2018-02-12 18:24:15 +08:00
|
|
|
u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
|
2016-10-05 04:11:31 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
u64 bbaddr;
|
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
|
|
bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
|
|
|
|
RING_BBADDR_UDW(engine->mmio_base));
|
|
|
|
else
|
|
|
|
bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
|
|
|
|
|
|
|
|
return bbaddr;
|
|
|
|
}
|
2016-10-12 17:05:17 +08:00
|
|
|
|
2018-05-17 02:33:55 +08:00
|
|
|
int intel_engine_stop_cs(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
const u32 base = engine->mmio_base;
|
|
|
|
const i915_reg_t mode = RING_MI_MODE(base);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) < 3)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
GEM_TRACE("%s\n", engine->name);
|
|
|
|
|
|
|
|
I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
|
|
|
|
|
|
|
|
err = 0;
|
|
|
|
if (__intel_wait_for_register_fw(dev_priv,
|
|
|
|
mode, MODE_IDLE, MODE_IDLE,
|
|
|
|
1000, 0,
|
|
|
|
NULL)) {
|
|
|
|
GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
|
|
|
|
err = -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* A final mmio read to let GPU writes be hopefully flushed to memory */
|
|
|
|
POSTING_READ_FW(mode);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2018-08-15 01:18:57 +08:00
|
|
|
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
|
|
|
|
GEM_TRACE("%s\n", engine->name);
|
|
|
|
|
|
|
|
I915_WRITE_FW(RING_MI_MODE(engine->mmio_base),
|
|
|
|
_MASKED_BIT_DISABLE(STOP_RING));
|
|
|
|
}
|
|
|
|
|
2016-10-12 17:05:17 +08:00
|
|
|
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case I915_CACHE_NONE: return " uncached";
|
|
|
|
case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
|
|
|
|
case I915_CACHE_L3_LLC: return " L3+LLC";
|
|
|
|
case I915_CACHE_WT: return " WT";
|
|
|
|
default: return "";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-19 06:39:57 +08:00
|
|
|
u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
|
|
|
|
u32 mcr_s_ss_select;
|
|
|
|
u32 slice = fls(sseu->slice_mask);
|
|
|
|
u32 subslice = fls(sseu->subslice_mask[slice]);
|
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) == 10)
|
|
|
|
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
|
|
|
|
GEN8_MCR_SUBSLICE(subslice);
|
2018-05-19 06:40:32 +08:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 11)
|
|
|
|
mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
|
|
|
|
GEN11_MCR_SUBSLICE(subslice);
|
2018-05-19 06:39:57 +08:00
|
|
|
else
|
|
|
|
mcr_s_ss_select = 0;
|
|
|
|
|
|
|
|
return mcr_s_ss_select;
|
|
|
|
}
|
|
|
|
|
2016-10-12 17:05:17 +08:00
|
|
|
static inline uint32_t
|
|
|
|
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
|
|
|
|
int subslice, i915_reg_t reg)
|
|
|
|
{
|
2018-03-16 20:14:51 +08:00
|
|
|
uint32_t mcr_slice_subslice_mask;
|
|
|
|
uint32_t mcr_slice_subslice_select;
|
2018-05-19 06:39:57 +08:00
|
|
|
uint32_t default_mcr_s_ss_select;
|
2016-10-12 17:05:17 +08:00
|
|
|
uint32_t mcr;
|
|
|
|
uint32_t ret;
|
|
|
|
enum forcewake_domains fw_domains;
|
|
|
|
|
2018-03-16 20:14:51 +08:00
|
|
|
if (INTEL_GEN(dev_priv) >= 11) {
|
|
|
|
mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
|
|
|
|
GEN11_MCR_SUBSLICE_MASK;
|
|
|
|
mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
|
|
|
|
GEN11_MCR_SUBSLICE(subslice);
|
|
|
|
} else {
|
|
|
|
mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
|
|
|
|
GEN8_MCR_SUBSLICE_MASK;
|
|
|
|
mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
|
|
|
|
GEN8_MCR_SUBSLICE(subslice);
|
|
|
|
}
|
|
|
|
|
2018-05-19 06:39:57 +08:00
|
|
|
default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(dev_priv);
|
|
|
|
|
2016-10-12 17:05:17 +08:00
|
|
|
fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
|
|
|
|
FW_REG_READ);
|
|
|
|
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
|
|
|
|
GEN8_MCR_SELECTOR,
|
|
|
|
FW_REG_READ | FW_REG_WRITE);
|
|
|
|
|
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
|
|
|
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
|
|
|
|
|
|
|
|
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
|
2018-05-19 06:39:57 +08:00
|
|
|
|
|
|
|
WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
|
|
|
|
default_mcr_s_ss_select);
|
|
|
|
|
2018-03-16 20:14:51 +08:00
|
|
|
mcr &= ~mcr_slice_subslice_mask;
|
|
|
|
mcr |= mcr_slice_subslice_select;
|
2016-10-12 17:05:17 +08:00
|
|
|
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
|
|
|
|
|
|
|
|
ret = I915_READ_FW(reg);
|
|
|
|
|
2018-03-16 20:14:51 +08:00
|
|
|
mcr &= ~mcr_slice_subslice_mask;
|
2018-05-19 06:39:57 +08:00
|
|
|
mcr |= default_mcr_s_ss_select;
|
|
|
|
|
2016-10-12 17:05:17 +08:00
|
|
|
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
|
|
|
|
|
|
|
|
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
|
|
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NB: please notice the memset */
|
|
|
|
void intel_engine_get_instdone(struct intel_engine_cs *engine,
|
|
|
|
struct intel_instdone *instdone)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
u32 mmio_base = engine->mmio_base;
|
|
|
|
int slice;
|
|
|
|
int subslice;
|
|
|
|
|
|
|
|
memset(instdone, 0, sizeof(*instdone));
|
|
|
|
|
|
|
|
switch (INTEL_GEN(dev_priv)) {
|
|
|
|
default:
|
|
|
|
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
|
|
|
|
|
|
|
|
if (engine->id != RCS)
|
|
|
|
break;
|
|
|
|
|
|
|
|
instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
|
|
|
|
for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
|
|
|
|
instdone->sampler[slice][subslice] =
|
|
|
|
read_subslice_reg(dev_priv, slice, subslice,
|
|
|
|
GEN7_SAMPLER_INSTDONE);
|
|
|
|
instdone->row[slice][subslice] =
|
|
|
|
read_subslice_reg(dev_priv, slice, subslice,
|
|
|
|
GEN7_ROW_INSTDONE);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
|
|
|
|
|
|
|
|
if (engine->id != RCS)
|
|
|
|
break;
|
|
|
|
|
|
|
|
instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
|
|
|
|
instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
|
|
|
|
instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
|
|
|
|
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
case 5:
|
|
|
|
case 4:
|
|
|
|
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
|
|
|
|
|
|
|
|
if (engine->id == RCS)
|
|
|
|
/* HACK: Using the wrong struct member */
|
|
|
|
instdone->slice_common = I915_READ(GEN4_INSTDONE1);
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
case 2:
|
|
|
|
instdone->instdone = I915_READ(GEN2_INSTDONE);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-02-14 01:15:14 +08:00
|
|
|
|
2017-05-30 20:13:33 +08:00
|
|
|
static bool ring_is_idle(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
bool idle = true;
|
|
|
|
|
2018-02-12 17:39:28 +08:00
|
|
|
/* If the whole device is asleep, the engine must be idle */
|
|
|
|
if (!intel_runtime_pm_get_if_in_use(dev_priv))
|
|
|
|
return true;
|
2017-05-30 20:13:33 +08:00
|
|
|
|
2017-05-30 20:13:34 +08:00
|
|
|
/* First check that no commands are left in the ring */
|
|
|
|
if ((I915_READ_HEAD(engine) & HEAD_ADDR) !=
|
|
|
|
(I915_READ_TAIL(engine) & TAIL_ADDR))
|
|
|
|
idle = false;
|
|
|
|
|
2017-05-30 20:13:33 +08:00
|
|
|
/* No bit for gen2, so assume the CS parser is idle */
|
|
|
|
if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
|
|
|
|
idle = false;
|
|
|
|
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
|
|
|
return idle;
|
|
|
|
}
|
|
|
|
|
2017-03-03 20:19:46 +08:00
|
|
|
/**
|
|
|
|
* intel_engine_is_idle() - Report if the engine has finished process all work
|
|
|
|
* @engine: the intel_engine_cs
|
|
|
|
*
|
|
|
|
* Return true if there are no requests pending, nothing left to be submitted
|
|
|
|
* to hardware, and that the engine is idle.
|
|
|
|
*/
|
|
|
|
bool intel_engine_is_idle(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
|
|
|
2017-04-12 03:00:42 +08:00
|
|
|
/* More white lies, if wedged, hw state is inconsistent */
|
|
|
|
if (i915_terminally_wedged(&dev_priv->gpu_error))
|
|
|
|
return true;
|
|
|
|
|
2017-03-03 20:19:46 +08:00
|
|
|
/* Any inflight/incomplete requests? */
|
2018-08-06 19:26:05 +08:00
|
|
|
if (!intel_engine_signaled(engine, intel_engine_last_submit(engine)))
|
2017-03-03 20:19:46 +08:00
|
|
|
return false;
|
|
|
|
|
2017-04-12 07:44:26 +08:00
|
|
|
if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock))
|
|
|
|
return true;
|
|
|
|
|
2017-10-24 05:32:36 +08:00
|
|
|
/* Waiting to drain ELSP? */
|
2018-05-07 01:13:28 +08:00
|
|
|
if (READ_ONCE(engine->execlists.active)) {
|
2018-07-14 04:35:28 +08:00
|
|
|
struct tasklet_struct *t = &engine->execlists.tasklet;
|
2018-05-07 01:13:28 +08:00
|
|
|
|
2018-06-20 21:59:29 +08:00
|
|
|
local_bh_disable();
|
2018-07-14 04:35:28 +08:00
|
|
|
if (tasklet_trylock(t)) {
|
|
|
|
/* Must wait for any GPU reset in progress. */
|
|
|
|
if (__tasklet_is_enabled(t))
|
|
|
|
t->func(t->data);
|
|
|
|
tasklet_unlock(t);
|
2018-05-07 01:13:28 +08:00
|
|
|
}
|
2018-06-20 21:59:29 +08:00
|
|
|
local_bh_enable();
|
2018-05-07 01:13:28 +08:00
|
|
|
|
2018-09-14 16:00:16 +08:00
|
|
|
/* Otherwise flush the tasklet if it was on another cpu */
|
|
|
|
tasklet_unlock_wait(t);
|
|
|
|
|
2018-07-14 04:35:28 +08:00
|
|
|
if (READ_ONCE(engine->execlists.active))
|
2018-05-07 01:13:28 +08:00
|
|
|
return false;
|
|
|
|
}
|
2017-03-03 20:19:46 +08:00
|
|
|
|
2018-05-07 01:13:28 +08:00
|
|
|
/* ELSP is empty, but there are ready requests? E.g. after reset */
|
2018-06-29 15:53:20 +08:00
|
|
|
if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
|
2017-07-21 20:32:24 +08:00
|
|
|
return false;
|
|
|
|
|
2017-03-03 20:19:46 +08:00
|
|
|
/* Ring stopped? */
|
2017-05-30 20:13:33 +08:00
|
|
|
if (!ring_is_idle(engine))
|
2017-03-03 20:19:46 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-03-03 20:19:47 +08:00
|
|
|
bool intel_engines_are_idle(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
|
|
|
|
2017-12-12 21:21:48 +08:00
|
|
|
/*
|
|
|
|
* If the driver is wedged, HW state may be very inconsistent and
|
2017-03-30 22:50:37 +08:00
|
|
|
* report that it is still busy, even though we have stopped using it.
|
|
|
|
*/
|
|
|
|
if (i915_terminally_wedged(&dev_priv->gpu_error))
|
|
|
|
return true;
|
|
|
|
|
2017-03-03 20:19:47 +08:00
|
|
|
for_each_engine(engine, dev_priv, id) {
|
|
|
|
if (!intel_engine_is_idle(engine))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-11-10 22:26:28 +08:00
|
|
|
/**
|
|
|
|
* intel_engine_has_kernel_context:
|
|
|
|
* @engine: the engine
|
|
|
|
*
|
|
|
|
* Returns true if the last context to be executed on this engine, or has been
|
|
|
|
* executed if the engine is already idle, is the kernel context
|
|
|
|
* (#i915.kernel_context).
|
|
|
|
*/
|
2017-10-25 06:08:55 +08:00
|
|
|
bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-05-18 05:26:32 +08:00
|
|
|
const struct intel_context *kernel_context =
|
|
|
|
to_intel_context(engine->i915->kernel_context, engine);
|
2018-02-21 17:56:36 +08:00
|
|
|
struct i915_request *rq;
|
2017-11-10 22:26:28 +08:00
|
|
|
|
|
|
|
lockdep_assert_held(&engine->i915->drm.struct_mutex);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check the last context seen by the engine. If active, it will be
|
|
|
|
* the last request that remains in the timeline. When idle, it is
|
|
|
|
* the last executed context as tracked by retirement.
|
|
|
|
*/
|
2018-05-03 00:38:39 +08:00
|
|
|
rq = __i915_gem_active_peek(&engine->timeline.last_request);
|
2017-11-10 22:26:28 +08:00
|
|
|
if (rq)
|
2018-05-18 05:26:32 +08:00
|
|
|
return rq->hw_context == kernel_context;
|
2017-11-10 22:26:28 +08:00
|
|
|
else
|
|
|
|
return engine->last_retired_context == kernel_context;
|
2017-10-25 06:08:55 +08:00
|
|
|
}
|
|
|
|
|
2017-03-17 01:13:03 +08:00
|
|
|
void intel_engines_reset_default_submission(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
|
|
|
|
|
|
|
for_each_engine(engine, i915, id)
|
|
|
|
engine->set_default_submission(engine);
|
|
|
|
}
|
|
|
|
|
2018-06-17 04:25:34 +08:00
|
|
|
/**
|
|
|
|
* intel_engines_sanitize: called after the GPU has lost power
|
|
|
|
* @i915: the i915 device
|
|
|
|
*
|
|
|
|
* Anytime we reset the GPU, either with an explicit GPU reset or through a
|
|
|
|
* PCI power cycle, the GPU loses state and we must reset our state tracking
|
|
|
|
* to match. Note that calling intel_engines_sanitize() if the GPU has not
|
|
|
|
* been reset results in much confusion!
|
|
|
|
*/
|
|
|
|
void intel_engines_sanitize(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
|
|
|
|
|
|
|
GEM_TRACE("\n");
|
|
|
|
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
|
|
if (engine->reset.reset)
|
|
|
|
engine->reset.reset(engine, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-25 22:39:41 +08:00
|
|
|
/**
|
|
|
|
* intel_engines_park: called when the GT is transitioning from busy->idle
|
|
|
|
* @i915: the i915 device
|
|
|
|
*
|
|
|
|
* The GT is now idle and about to go to sleep (maybe never to wake again?).
|
|
|
|
* Time for us to tidy and put away our toys (release resources back to the
|
|
|
|
* system).
|
|
|
|
*/
|
|
|
|
void intel_engines_park(struct drm_i915_private *i915)
|
drm/i915: Split execlist priority queue into rbtree + linked list
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list within a level. If we move the requests at one priority into a list,
we can then reduce the rbtree to the set of priorities. This should keep
the height of the rbtree small, as the number of active priorities can not
exceed the number of active requests and should be typically only a few.
Currently, we have ~2k possible different priority levels, that may
increase to allow even more fine grained selection. Allocating those in
advance seems a waste (and may be impossible), so we opt for allocating
upon first use, and freeing after its requests are depleted. To avoid
the possibility of an allocation failure causing us to lose a request,
we preallocate the default priority (0) and bump any request to that
priority if we fail to allocate it the appropriate plist. Having a
request (that is ready to run, so not leading to corruption) execute
out-of-order is better than leaking the request (and its dependency
tree) entirely.
There should be a benefit to reducing execlists_dequeue() to principally
using a simple list (and reducing the frequency of both rbtree iteration
and balancing on erase) but for typical workloads, request coalescing
should be small enough that we don't notice any change. The main gain is
from improving PI calls to schedule, and the explicit list within a
level should make request unwinding simpler (we just need to insert at
the head of the list rather than the tail and not have to make the
rbtree search more complicated).
v2: Avoid use-after-free when deleting a depleted priolist
v3: Michał found the solution to handling the allocation failure
gracefully. If we disable all priority scheduling following the
allocation failure, those requests will be executed in fifo and we will
ensure that this request and its dependencies are in strict fifo (even
when it doesn't realise it is only a single list). Normal scheduling is
restored once we know the device is idle, until the next failure!
Suggested-by: Michał Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170517121007.27224-8-chris@chris-wilson.co.uk
2017-05-17 20:10:03 +08:00
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
|
|
|
|
|
|
|
for_each_engine(engine, i915, id) {
|
2017-11-02 04:21:49 +08:00
|
|
|
/* Flush the residual irq tasklets first. */
|
|
|
|
intel_engine_disarm_breadcrumbs(engine);
|
2017-11-16 21:32:37 +08:00
|
|
|
tasklet_kill(&engine->execlists.tasklet);
|
2017-11-02 04:21:49 +08:00
|
|
|
|
2017-10-27 19:06:17 +08:00
|
|
|
/*
|
|
|
|
* We are committed now to parking the engines, make sure there
|
|
|
|
* will be no more interrupts arriving later and the engines
|
|
|
|
* are truly idle.
|
|
|
|
*/
|
2017-11-10 19:25:50 +08:00
|
|
|
if (wait_for(intel_engine_is_idle(engine), 10)) {
|
2017-10-27 19:06:17 +08:00
|
|
|
struct drm_printer p = drm_debug_printer(__func__);
|
|
|
|
|
2017-11-10 19:25:50 +08:00
|
|
|
dev_err(i915->drm.dev,
|
|
|
|
"%s is not idle before parking\n",
|
|
|
|
engine->name);
|
2017-12-08 09:23:00 +08:00
|
|
|
intel_engine_dump(engine, &p, NULL);
|
2017-10-27 19:06:17 +08:00
|
|
|
}
|
|
|
|
|
2018-04-11 18:39:29 +08:00
|
|
|
/* Must be reset upon idling, or we may miss the busy wakeup. */
|
|
|
|
GEM_BUG_ON(engine->execlists.queue_priority != INT_MIN);
|
|
|
|
|
2017-10-25 22:39:41 +08:00
|
|
|
if (engine->park)
|
|
|
|
engine->park(engine);
|
|
|
|
|
2018-05-18 17:02:11 +08:00
|
|
|
if (engine->pinned_default_state) {
|
|
|
|
i915_gem_object_unpin_map(engine->default_state);
|
|
|
|
engine->pinned_default_state = NULL;
|
|
|
|
}
|
|
|
|
|
2017-10-25 22:39:41 +08:00
|
|
|
i915_gem_batch_pool_fini(&engine->batch_pool);
|
2017-09-22 20:43:03 +08:00
|
|
|
engine->execlists.no_priolist = false;
|
drm/i915: Split execlist priority queue into rbtree + linked list
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list within a level. If we move the requests at one priority into a list,
we can then reduce the rbtree to the set of priorities. This should keep
the height of the rbtree small, as the number of active priorities can not
exceed the number of active requests and should be typically only a few.
Currently, we have ~2k possible different priority levels, that may
increase to allow even more fine grained selection. Allocating those in
advance seems a waste (and may be impossible), so we opt for allocating
upon first use, and freeing after its requests are depleted. To avoid
the possibility of an allocation failure causing us to lose a request,
we preallocate the default priority (0) and bump any request to that
priority if we fail to allocate it the appropriate plist. Having a
request (that is ready to run, so not leading to corruption) execute
out-of-order is better than leaking the request (and its dependency
tree) entirely.
There should be a benefit to reducing execlists_dequeue() to principally
using a simple list (and reducing the frequency of both rbtree iteration
and balancing on erase) but for typical workloads, request coalescing
should be small enough that we don't notice any change. The main gain is
from improving PI calls to schedule, and the explicit list within a
level should make request unwinding simpler (we just need to insert at
the head of the list rather than the tail and not have to make the
rbtree search more complicated).
v2: Avoid use-after-free when deleting a depleted priolist
v3: Michał found the solution to handling the allocation failure
gracefully. If we disable all priority scheduling following the
allocation failure, those requests will be executed in fifo and we will
ensure that this request and its dependencies are in strict fifo (even
when it doesn't realise it is only a single list). Normal scheduling is
restored once we know the device is idle, until the next failure!
Suggested-by: Michał Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170517121007.27224-8-chris@chris-wilson.co.uk
2017-05-17 20:10:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-25 22:39:41 +08:00
|
|
|
/**
|
|
|
|
* intel_engines_unpark: called when the GT is transitioning from idle->busy
|
|
|
|
* @i915: the i915 device
|
|
|
|
*
|
|
|
|
* The GT was idle and now about to fire up with some new user requests.
|
|
|
|
*/
|
|
|
|
void intel_engines_unpark(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
|
|
|
|
|
|
|
for_each_engine(engine, i915, id) {
|
2018-05-18 17:02:11 +08:00
|
|
|
void *map;
|
|
|
|
|
|
|
|
/* Pin the default state for fast resets from atomic context. */
|
|
|
|
map = NULL;
|
|
|
|
if (engine->default_state)
|
|
|
|
map = i915_gem_object_pin_map(engine->default_state,
|
|
|
|
I915_MAP_WB);
|
|
|
|
if (!IS_ERR_OR_NULL(map))
|
|
|
|
engine->pinned_default_state = map;
|
|
|
|
|
2017-10-25 22:39:41 +08:00
|
|
|
if (engine->unpark)
|
|
|
|
engine->unpark(engine);
|
2018-05-03 06:03:13 +08:00
|
|
|
|
|
|
|
intel_engine_init_hangcheck(engine);
|
2017-10-25 22:39:41 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-18 05:26:31 +08:00
|
|
|
/**
|
|
|
|
* intel_engine_lost_context: called when the GPU is reset into unknown state
|
|
|
|
* @engine: the engine
|
|
|
|
*
|
|
|
|
* We have either reset the GPU or otherwise about to lose state tracking of
|
|
|
|
* the current GPU logical state (e.g. suspend). On next use, it is therefore
|
|
|
|
* imperative that we make no presumptions about the current state and load
|
|
|
|
* from scratch.
|
|
|
|
*/
|
|
|
|
void intel_engine_lost_context(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-05-18 05:26:32 +08:00
|
|
|
struct intel_context *ce;
|
2018-05-18 05:26:31 +08:00
|
|
|
|
|
|
|
lockdep_assert_held(&engine->i915->drm.struct_mutex);
|
|
|
|
|
2018-05-18 05:26:32 +08:00
|
|
|
ce = fetch_and_zero(&engine->last_retired_context);
|
|
|
|
if (ce)
|
|
|
|
intel_context_unpin(ce);
|
2018-05-18 05:26:31 +08:00
|
|
|
}
|
|
|
|
|
2017-09-06 23:28:59 +08:00
|
|
|
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
switch (INTEL_GEN(engine->i915)) {
|
|
|
|
case 2:
|
|
|
|
return false; /* uses physical not virtual addresses */
|
|
|
|
case 3:
|
|
|
|
/* maybe only uses physical not virtual addresses */
|
|
|
|
return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
|
|
|
|
case 6:
|
|
|
|
return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-10 22:26:33 +08:00
|
|
|
unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
enum intel_engine_id id;
|
|
|
|
unsigned int which;
|
|
|
|
|
|
|
|
which = 0;
|
|
|
|
for_each_engine(engine, i915, id)
|
|
|
|
if (engine->default_state)
|
|
|
|
which |= BIT(engine->uabi_class);
|
|
|
|
|
|
|
|
return which;
|
|
|
|
}
|
|
|
|
|
2018-04-24 09:08:39 +08:00
|
|
|
static int print_sched_attr(struct drm_i915_private *i915,
|
|
|
|
const struct i915_sched_attr *attr,
|
|
|
|
char *buf, int x, int len)
|
2018-04-19 02:40:52 +08:00
|
|
|
{
|
|
|
|
if (attr->priority == I915_PRIORITY_INVALID)
|
2018-04-24 09:08:39 +08:00
|
|
|
return x;
|
|
|
|
|
|
|
|
x += snprintf(buf + x, len - x,
|
|
|
|
" prio=%d", attr->priority);
|
2018-04-19 02:40:52 +08:00
|
|
|
|
2018-04-24 09:08:39 +08:00
|
|
|
return x;
|
2018-04-19 02:40:52 +08:00
|
|
|
}
|
|
|
|
|
2017-10-09 19:02:57 +08:00
|
|
|
static void print_request(struct drm_printer *m,
|
2018-02-21 17:56:36 +08:00
|
|
|
struct i915_request *rq,
|
2017-10-09 19:02:57 +08:00
|
|
|
const char *prefix)
|
|
|
|
{
|
2018-03-14 18:16:30 +08:00
|
|
|
const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
|
2018-05-17 23:28:24 +08:00
|
|
|
char buf[80] = "";
|
2018-04-24 09:08:39 +08:00
|
|
|
int x = 0;
|
|
|
|
|
|
|
|
x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf));
|
2018-03-14 18:16:30 +08:00
|
|
|
|
2018-04-24 09:08:39 +08:00
|
|
|
drm_printf(m, "%s%x%s [%llx:%x]%s @ %dms: %s\n",
|
2018-04-19 02:40:52 +08:00
|
|
|
prefix,
|
2017-10-16 04:43:10 +08:00
|
|
|
rq->global_seqno,
|
2018-02-21 17:56:36 +08:00
|
|
|
i915_request_completed(rq) ? "!" : "",
|
2018-04-24 09:08:39 +08:00
|
|
|
rq->fence.context, rq->fence.seqno,
|
|
|
|
buf,
|
2017-10-09 19:02:57 +08:00
|
|
|
jiffies_to_msecs(jiffies - rq->emitted_jiffies),
|
2018-03-14 18:16:30 +08:00
|
|
|
name);
|
2017-10-09 19:02:57 +08:00
|
|
|
}
|
|
|
|
|
2017-12-23 02:25:21 +08:00
|
|
|
static void hexdump(struct drm_printer *m, const void *buf, size_t len)
|
|
|
|
{
|
|
|
|
const size_t rowsize = 8 * sizeof(u32);
|
|
|
|
const void *prev = NULL;
|
|
|
|
bool skip = false;
|
|
|
|
size_t pos;
|
|
|
|
|
|
|
|
for (pos = 0; pos < len; pos += rowsize) {
|
|
|
|
char line[128];
|
|
|
|
|
|
|
|
if (prev && !memcmp(prev, buf + pos, rowsize)) {
|
|
|
|
if (!skip) {
|
|
|
|
drm_printf(m, "*\n");
|
|
|
|
skip = true;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
|
|
|
|
rowsize, sizeof(u32),
|
|
|
|
line, sizeof(line),
|
|
|
|
false) >= sizeof(line));
|
2018-06-14 17:41:01 +08:00
|
|
|
drm_printf(m, "[%04zx] %s\n", pos, line);
|
2017-12-23 02:25:21 +08:00
|
|
|
|
|
|
|
prev = buf + pos;
|
|
|
|
skip = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-12 18:24:15 +08:00
|
|
|
static void intel_engine_print_registers(const struct intel_engine_cs *engine,
|
|
|
|
struct drm_printer *m)
|
2017-10-09 19:02:57 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2018-02-12 18:24:15 +08:00
|
|
|
const struct intel_engine_execlists * const execlists =
|
|
|
|
&engine->execlists;
|
2017-10-09 19:02:57 +08:00
|
|
|
u64 addr;
|
|
|
|
|
2018-06-14 17:41:02 +08:00
|
|
|
if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
|
|
|
|
drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
|
2018-02-12 18:24:15 +08:00
|
|
|
drm_printf(m, "\tRING_START: 0x%08x\n",
|
|
|
|
I915_READ(RING_START(engine->mmio_base)));
|
|
|
|
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
|
|
|
|
I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR);
|
|
|
|
drm_printf(m, "\tRING_TAIL: 0x%08x\n",
|
|
|
|
I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR);
|
2017-10-26 19:50:48 +08:00
|
|
|
drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
|
2017-10-09 19:02:57 +08:00
|
|
|
I915_READ(RING_CTL(engine->mmio_base)),
|
2017-10-26 19:50:48 +08:00
|
|
|
I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
|
|
|
|
if (INTEL_GEN(engine->i915) > 2) {
|
|
|
|
drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
|
|
|
|
I915_READ(RING_MI_MODE(engine->mmio_base)),
|
|
|
|
I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
|
|
|
|
}
|
2018-02-12 18:24:15 +08:00
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 6) {
|
|
|
|
drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
|
|
|
|
}
|
|
|
|
|
2017-11-21 04:55:04 +08:00
|
|
|
if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
|
2017-11-21 04:55:03 +08:00
|
|
|
drm_printf(m, "\tSYNC_0: 0x%08x\n",
|
|
|
|
I915_READ(RING_SYNC_0(engine->mmio_base)));
|
|
|
|
drm_printf(m, "\tSYNC_1: 0x%08x\n",
|
|
|
|
I915_READ(RING_SYNC_1(engine->mmio_base)));
|
|
|
|
if (HAS_VEBOX(dev_priv))
|
|
|
|
drm_printf(m, "\tSYNC_2: 0x%08x\n",
|
|
|
|
I915_READ(RING_SYNC_2(engine->mmio_base)));
|
|
|
|
}
|
2017-10-09 19:02:57 +08:00
|
|
|
|
|
|
|
addr = intel_engine_get_active_head(engine);
|
|
|
|
drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
|
|
|
|
upper_32_bits(addr), lower_32_bits(addr));
|
|
|
|
addr = intel_engine_get_last_batch_head(engine);
|
|
|
|
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
|
|
|
|
upper_32_bits(addr), lower_32_bits(addr));
|
2017-12-18 20:39:14 +08:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
|
|
addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
|
|
|
|
RING_DMA_FADD_UDW(engine->mmio_base));
|
|
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
|
|
|
addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
|
|
|
|
else
|
|
|
|
addr = I915_READ(DMA_FADD_I8XX);
|
|
|
|
drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
|
|
|
|
upper_32_bits(addr), lower_32_bits(addr));
|
|
|
|
if (INTEL_GEN(dev_priv) >= 4) {
|
|
|
|
drm_printf(m, "\tIPEIR: 0x%08x\n",
|
|
|
|
I915_READ(RING_IPEIR(engine->mmio_base)));
|
|
|
|
drm_printf(m, "\tIPEHR: 0x%08x\n",
|
|
|
|
I915_READ(RING_IPEHR(engine->mmio_base)));
|
|
|
|
} else {
|
|
|
|
drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
|
|
|
|
drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
|
|
|
|
}
|
2017-10-09 19:02:57 +08:00
|
|
|
|
2017-11-21 04:55:00 +08:00
|
|
|
if (HAS_EXECLISTS(dev_priv)) {
|
2017-10-09 19:02:57 +08:00
|
|
|
const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
|
|
|
|
unsigned int idx;
|
2018-08-21 18:11:38 +08:00
|
|
|
u8 read, write;
|
2017-10-09 19:02:57 +08:00
|
|
|
|
|
|
|
drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
|
|
|
|
I915_READ(RING_EXECLIST_STATUS_LO(engine)),
|
|
|
|
I915_READ(RING_EXECLIST_STATUS_HI(engine)));
|
|
|
|
|
2018-08-21 18:11:38 +08:00
|
|
|
read = execlists->csb_head;
|
|
|
|
write = READ_ONCE(*execlists->csb_write);
|
|
|
|
|
|
|
|
drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
|
|
|
|
read, write,
|
|
|
|
GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
|
2018-03-26 19:50:36 +08:00
|
|
|
yesno(test_bit(TASKLET_STATE_SCHED,
|
|
|
|
&engine->execlists.tasklet.state)),
|
|
|
|
enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
|
2017-10-09 19:02:57 +08:00
|
|
|
if (read >= GEN8_CSB_ENTRIES)
|
|
|
|
read = 0;
|
|
|
|
if (write >= GEN8_CSB_ENTRIES)
|
|
|
|
write = 0;
|
|
|
|
if (read > write)
|
|
|
|
write += GEN8_CSB_ENTRIES;
|
|
|
|
while (read < write) {
|
|
|
|
idx = ++read % GEN8_CSB_ENTRIES;
|
2018-08-21 18:11:38 +08:00
|
|
|
drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
|
2017-10-09 19:02:57 +08:00
|
|
|
idx,
|
|
|
|
hws[idx * 2],
|
2018-08-21 18:11:38 +08:00
|
|
|
I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
|
|
|
|
hws[idx * 2 + 1],
|
|
|
|
I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
|
2017-10-09 19:02:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
|
2018-02-21 17:56:36 +08:00
|
|
|
struct i915_request *rq;
|
2017-10-09 19:02:57 +08:00
|
|
|
unsigned int count;
|
|
|
|
|
|
|
|
rq = port_unpack(&execlists->port[idx], &count);
|
|
|
|
if (rq) {
|
2018-02-12 18:24:15 +08:00
|
|
|
char hdr[80];
|
|
|
|
|
2017-12-08 09:22:59 +08:00
|
|
|
snprintf(hdr, sizeof(hdr),
|
2018-05-02 18:41:50 +08:00
|
|
|
"\t\tELSP[%d] count=%d, ring->start=%08x, rq: ",
|
|
|
|
idx, count,
|
|
|
|
i915_ggtt_offset(rq->ring->vma));
|
2017-12-08 09:22:59 +08:00
|
|
|
print_request(m, rq, hdr);
|
2017-10-09 19:02:57 +08:00
|
|
|
} else {
|
2017-12-08 09:22:59 +08:00
|
|
|
drm_printf(m, "\t\tELSP[%d] idle\n", idx);
|
2017-10-09 19:02:57 +08:00
|
|
|
}
|
|
|
|
}
|
2017-10-24 05:32:36 +08:00
|
|
|
drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
|
2017-10-09 19:02:57 +08:00
|
|
|
rcu_read_unlock();
|
|
|
|
} else if (INTEL_GEN(dev_priv) > 6) {
|
|
|
|
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
|
|
|
|
I915_READ(RING_PP_DIR_BASE(engine)));
|
|
|
|
drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
|
|
|
|
I915_READ(RING_PP_DIR_BASE_READ(engine)));
|
|
|
|
drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
|
|
|
|
I915_READ(RING_PP_DIR_DCLV(engine)));
|
|
|
|
}
|
2018-02-12 18:24:15 +08:00
|
|
|
}
|
|
|
|
|
2018-06-14 20:21:50 +08:00
|
|
|
static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
|
|
|
|
{
|
|
|
|
void *ring;
|
|
|
|
int size;
|
|
|
|
|
|
|
|
drm_printf(m,
|
|
|
|
"[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
|
|
|
|
rq->head, rq->postfix, rq->tail,
|
|
|
|
rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
|
|
|
|
rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
|
|
|
|
|
|
|
|
size = rq->tail - rq->head;
|
|
|
|
if (rq->tail < rq->head)
|
|
|
|
size += rq->ring->size;
|
|
|
|
|
|
|
|
ring = kmalloc(size, GFP_ATOMIC);
|
|
|
|
if (ring) {
|
|
|
|
const void *vaddr = rq->ring->vaddr;
|
|
|
|
unsigned int head = rq->head;
|
|
|
|
unsigned int len = 0;
|
|
|
|
|
|
|
|
if (rq->tail < head) {
|
|
|
|
len = rq->ring->size - head;
|
|
|
|
memcpy(ring, vaddr + head, len);
|
|
|
|
head = 0;
|
|
|
|
}
|
|
|
|
memcpy(ring + len, vaddr + head, size - len);
|
|
|
|
|
|
|
|
hexdump(m, ring, size);
|
|
|
|
kfree(ring);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-12 18:24:15 +08:00
|
|
|
void intel_engine_dump(struct intel_engine_cs *engine,
|
|
|
|
struct drm_printer *m,
|
|
|
|
const char *header, ...)
|
|
|
|
{
|
2018-04-24 16:16:00 +08:00
|
|
|
const int MAX_REQUESTS_TO_SHOW = 8;
|
2018-02-12 18:24:15 +08:00
|
|
|
struct intel_breadcrumbs * const b = &engine->breadcrumbs;
|
|
|
|
const struct intel_engine_execlists * const execlists = &engine->execlists;
|
|
|
|
struct i915_gpu_error * const error = &engine->i915->gpu_error;
|
2018-04-24 16:16:00 +08:00
|
|
|
struct i915_request *rq, *last;
|
2018-05-18 17:02:10 +08:00
|
|
|
unsigned long flags;
|
2018-02-12 18:24:15 +08:00
|
|
|
struct rb_node *rb;
|
2018-04-24 16:16:00 +08:00
|
|
|
int count;
|
2018-02-12 18:24:15 +08:00
|
|
|
|
|
|
|
if (header) {
|
|
|
|
va_list ap;
|
|
|
|
|
|
|
|
va_start(ap, header);
|
|
|
|
drm_vprintf(m, header, &ap);
|
|
|
|
va_end(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i915_terminally_wedged(&engine->i915->gpu_error))
|
|
|
|
drm_printf(m, "*** WEDGED ***\n");
|
|
|
|
|
2018-04-30 21:15:00 +08:00
|
|
|
drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
|
2018-02-12 18:24:15 +08:00
|
|
|
intel_engine_get_seqno(engine),
|
|
|
|
intel_engine_last_submit(engine),
|
|
|
|
engine->hangcheck.seqno,
|
2018-04-30 21:15:00 +08:00
|
|
|
jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
|
2018-02-12 18:24:15 +08:00
|
|
|
drm_printf(m, "\tReset count: %d (global %d)\n",
|
|
|
|
i915_reset_engine_count(error, engine),
|
|
|
|
i915_reset_count(error));
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
|
|
|
|
drm_printf(m, "\tRequests:\n");
|
|
|
|
|
2018-05-03 00:38:39 +08:00
|
|
|
rq = list_first_entry(&engine->timeline.requests,
|
2018-02-21 17:56:36 +08:00
|
|
|
struct i915_request, link);
|
2018-05-03 00:38:39 +08:00
|
|
|
if (&rq->link != &engine->timeline.requests)
|
2018-02-12 18:24:15 +08:00
|
|
|
print_request(m, rq, "\t\tfirst ");
|
|
|
|
|
2018-05-03 00:38:39 +08:00
|
|
|
rq = list_last_entry(&engine->timeline.requests,
|
2018-02-21 17:56:36 +08:00
|
|
|
struct i915_request, link);
|
2018-05-03 00:38:39 +08:00
|
|
|
if (&rq->link != &engine->timeline.requests)
|
2018-02-12 18:24:15 +08:00
|
|
|
print_request(m, rq, "\t\tlast ");
|
|
|
|
|
|
|
|
rq = i915_gem_find_active_request(engine);
|
|
|
|
if (rq) {
|
|
|
|
print_request(m, rq, "\t\tactive ");
|
2018-06-14 20:21:50 +08:00
|
|
|
|
2018-03-07 21:42:24 +08:00
|
|
|
drm_printf(m, "\t\tring->start: 0x%08x\n",
|
2018-02-12 18:24:15 +08:00
|
|
|
i915_ggtt_offset(rq->ring->vma));
|
2018-03-07 21:42:24 +08:00
|
|
|
drm_printf(m, "\t\tring->head: 0x%08x\n",
|
2018-02-12 18:24:15 +08:00
|
|
|
rq->ring->head);
|
2018-03-07 21:42:24 +08:00
|
|
|
drm_printf(m, "\t\tring->tail: 0x%08x\n",
|
2018-02-12 18:24:15 +08:00
|
|
|
rq->ring->tail);
|
2018-03-07 21:42:24 +08:00
|
|
|
drm_printf(m, "\t\tring->emit: 0x%08x\n",
|
|
|
|
rq->ring->emit);
|
|
|
|
drm_printf(m, "\t\tring->space: 0x%08x\n",
|
|
|
|
rq->ring->space);
|
2018-06-14 20:21:50 +08:00
|
|
|
|
|
|
|
print_request_ring(m, rq);
|
2018-02-12 18:24:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
rcu_read_unlock();
|
|
|
|
|
|
|
|
if (intel_runtime_pm_get_if_in_use(engine->i915)) {
|
|
|
|
intel_engine_print_registers(engine, m);
|
|
|
|
intel_runtime_pm_put(engine->i915);
|
|
|
|
} else {
|
|
|
|
drm_printf(m, "\tDevice is asleep; skipping register dump\n");
|
|
|
|
}
|
2017-10-09 19:02:57 +08:00
|
|
|
|
2018-05-18 17:02:10 +08:00
|
|
|
local_irq_save(flags);
|
|
|
|
spin_lock(&engine->timeline.lock);
|
2018-04-24 16:16:00 +08:00
|
|
|
|
|
|
|
last = NULL;
|
|
|
|
count = 0;
|
2018-05-03 00:38:39 +08:00
|
|
|
list_for_each_entry(rq, &engine->timeline.requests, link) {
|
2018-04-24 16:16:00 +08:00
|
|
|
if (count++ < MAX_REQUESTS_TO_SHOW - 1)
|
|
|
|
print_request(m, rq, "\t\tE ");
|
|
|
|
else
|
|
|
|
last = rq;
|
|
|
|
}
|
|
|
|
if (last) {
|
|
|
|
if (count > MAX_REQUESTS_TO_SHOW) {
|
|
|
|
drm_printf(m,
|
|
|
|
"\t\t...skipping %d executing requests...\n",
|
|
|
|
count - MAX_REQUESTS_TO_SHOW);
|
|
|
|
}
|
|
|
|
print_request(m, last, "\t\tE ");
|
|
|
|
}
|
|
|
|
|
|
|
|
last = NULL;
|
|
|
|
count = 0;
|
2018-02-22 22:22:29 +08:00
|
|
|
drm_printf(m, "\t\tQueue priority: %d\n", execlists->queue_priority);
|
2018-06-29 15:53:20 +08:00
|
|
|
for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
|
2018-10-01 20:32:04 +08:00
|
|
|
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
|
|
|
|
int i;
|
2017-10-16 04:43:10 +08:00
|
|
|
|
2018-10-01 20:32:04 +08:00
|
|
|
priolist_for_each_request(rq, p, i) {
|
2018-04-24 16:16:00 +08:00
|
|
|
if (count++ < MAX_REQUESTS_TO_SHOW - 1)
|
|
|
|
print_request(m, rq, "\t\tQ ");
|
|
|
|
else
|
|
|
|
last = rq;
|
|
|
|
}
|
2017-10-16 04:43:10 +08:00
|
|
|
}
|
2018-04-24 16:16:00 +08:00
|
|
|
if (last) {
|
|
|
|
if (count > MAX_REQUESTS_TO_SHOW) {
|
|
|
|
drm_printf(m,
|
|
|
|
"\t\t...skipping %d queued requests...\n",
|
|
|
|
count - MAX_REQUESTS_TO_SHOW);
|
|
|
|
}
|
|
|
|
print_request(m, last, "\t\tQ ");
|
|
|
|
}
|
|
|
|
|
2018-05-18 17:02:10 +08:00
|
|
|
spin_unlock(&engine->timeline.lock);
|
2017-10-16 04:43:10 +08:00
|
|
|
|
2018-05-18 17:02:10 +08:00
|
|
|
spin_lock(&b->rb_lock);
|
2017-10-09 19:02:57 +08:00
|
|
|
for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
|
|
|
|
struct intel_wait *w = rb_entry(rb, typeof(*w), node);
|
|
|
|
|
|
|
|
drm_printf(m, "\t%s [%d] waiting for %x\n",
|
|
|
|
w->tsk->comm, w->tsk->pid, w->seqno);
|
|
|
|
}
|
2018-05-18 17:02:10 +08:00
|
|
|
spin_unlock(&b->rb_lock);
|
|
|
|
local_irq_restore(flags);
|
2017-10-09 19:02:57 +08:00
|
|
|
|
2018-06-29 04:12:10 +08:00
|
|
|
drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s)\n",
|
2017-12-08 09:23:01 +08:00
|
|
|
engine->irq_posted,
|
|
|
|
yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
|
|
|
|
&engine->irq_posted)));
|
2017-12-23 02:25:21 +08:00
|
|
|
|
|
|
|
drm_printf(m, "HWSP:\n");
|
|
|
|
hexdump(m, engine->status_page.page_addr, PAGE_SIZE);
|
|
|
|
|
2017-11-07 23:22:11 +08:00
|
|
|
drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
|
2017-10-09 19:02:57 +08:00
|
|
|
}
|
|
|
|
|
drm/i915/pmu: Expose a PMU interface for perf queries
From: Chris Wilson <chris@chris-wilson.co.uk>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
From: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system, but also
runs the risk of hanging the machine.) As an alternative we can use the
perf event counter interface to sample the ring registers periodically
and send those results to userspace.
Functionality we are exporting to userspace is via the existing perf PMU
API and can be exercised via the existing tools. For example:
perf stat -a -e i915/rcs0-busy/ -I 1000
Will print the render engine busynnes once per second. All the performance
counters can be enumerated (perf list) and have their unit of measure
correctly reported in sysfs.
v1-v2 (Chris Wilson):
v2: Use a common timer for the ring sampling.
v3: (Tvrtko Ursulin)
* Decouple uAPI from i915 engine ids.
* Complete uAPI defines.
* Refactor some code to helpers for clarity.
* Skip sampling disabled engines.
* Expose counters in sysfs.
* Pass in fake regs to avoid null ptr deref in perf core.
* Convert to class/instance uAPI.
* Use shared driver code for rc6 residency, power and frequency.
v4: (Dmitry Rogozhkin)
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)
* Introduce refcounting of event subscriptions.
* Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.
* Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.
* Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.
* End result is that only global events are supported and perf stat
works correctly.
* Deny perf driver level sampling - it is prohibited for uncore PMU.
v5: (Tvrtko Ursulin)
* Don't hardcode number of engine samplers.
* Rewrite event ref-counting for correctness and simplicity.
* Store initial counter value when starting already enabled events
to correctly report values to all listeners.
* Fix RC6 residency readout.
* Comments, GPL header.
v6:
* Add missing entry to v4 changelog.
* Fix accounting in CPU hotplug case by copying the approach from
arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin)
v7:
* Log failure message only on failure.
* Remove CPU hotplug notification state on unregister.
v8:
* Fix error unwind on failed registration.
* Checkpatch cleanup.
v9:
* Drop the energy metric, it is available via intel_rapl_perf.
(Ville Syrjälä)
* Use HAS_RC6(p). (Chris Wilson)
* Handle unsupported non-engine events. (Dmitry Rogozhkin)
* Rebase for intel_rc6_residency_ns needing caller managed
runtime pm.
* Drop HAS_RC6 checks from the read callback since creating those
events will be rejected at init time already.
* Add counter units to sysfs so perf stat output is nicer.
* Cleanup the attribute tables for brevity and readability.
v10:
* Fixed queued accounting.
v11:
* Move intel_engine_lookup_user to intel_engine_cs.c
* Commit update. (Joonas Lahtinen)
v12:
* More accurate sampling. (Chris Wilson)
* Store and report frequency in MHz for better usability from
perf stat.
* Removed metrics: queued, interrupts, rc6 counters.
* Sample engine busyness based on seqno difference only
for less MMIO (and forcewake) on all platforms. (Chris Wilson)
v13:
* Comment spelling, use mul_u32_u32 to work around potential GCC
issue and somne code alignment changes. (Chris Wilson)
v14:
* Rebase.
v15:
* Rebase for RPS refactoring.
v16:
* Use the dynamic slot in the CPU hotplug state machine so that we are
free to setup our state as multi-instance. Previously we were re-using
the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as
multi-instance, nor owned by our driver to start with.
* Register the CPU hotplug handlers after the PMU, otherwise the callback
will get called before the PMU is initialized which can end up in
perf_pmu_migrate_context with an un-initialized base.
* Added workaround for a probable bug in cpuhp core.
v17:
* Remove workaround for the cpuhp bug.
v18:
* Rebase for drm_i915_gem_engine_class getting upstream before us.
v19:
* Rebase. (trivial)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com
2017-11-22 02:18:45 +08:00
|
|
|
static u8 user_class_map[] = {
|
|
|
|
[I915_ENGINE_CLASS_RENDER] = RENDER_CLASS,
|
|
|
|
[I915_ENGINE_CLASS_COPY] = COPY_ENGINE_CLASS,
|
|
|
|
[I915_ENGINE_CLASS_VIDEO] = VIDEO_DECODE_CLASS,
|
|
|
|
[I915_ENGINE_CLASS_VIDEO_ENHANCE] = VIDEO_ENHANCEMENT_CLASS,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_engine_cs *
|
|
|
|
intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance)
|
|
|
|
{
|
|
|
|
if (class >= ARRAY_SIZE(user_class_map))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
class = user_class_map[class];
|
|
|
|
|
|
|
|
GEM_BUG_ON(class > MAX_ENGINE_CLASS);
|
|
|
|
|
|
|
|
if (instance > MAX_ENGINE_INSTANCE)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return i915->engine_class[class][instance];
|
|
|
|
}
|
|
|
|
|
2017-11-22 02:18:48 +08:00
|
|
|
/**
|
|
|
|
* intel_enable_engine_stats() - Enable engine busy tracking on engine
|
|
|
|
* @engine: engine to enable stats collection
|
|
|
|
*
|
|
|
|
* Start collecting the engine busyness data for @engine.
|
|
|
|
*
|
|
|
|
* Returns 0 on success or a negative error code.
|
|
|
|
*/
|
|
|
|
int intel_enable_engine_stats(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-01-15 17:20:41 +08:00
|
|
|
struct intel_engine_execlists *execlists = &engine->execlists;
|
2017-11-22 02:18:48 +08:00
|
|
|
unsigned long flags;
|
2018-01-15 17:20:41 +08:00
|
|
|
int err = 0;
|
2017-11-22 02:18:48 +08:00
|
|
|
|
2017-11-29 18:28:05 +08:00
|
|
|
if (!intel_engine_supports_stats(engine))
|
2017-11-22 02:18:48 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on average! Deferring our work to a tasklet allowed us to do the
processing with irqs enabled, reducing the impact to an average of about
50us.
We have since eradicated the use of forcewaked mmio from inside the CSB
processing and ELSP submission, bringing the impact down to around 5us
(on Kabylake); an order of magnitude better than our measurements 2
years ago on Broadwell and only about 2x worse on average than the
gem_syslatency on an unladen system.
In this iteration of the tasklet-vs-direct submission debate, we seek a
compromise where by we submit new requests immediately to the HW but
defer processing the CS interrupt onto a tasklet. We gain the advantage
of low-latency and ksoftirqd avoidance when waking up the HW, while
avoiding the system-wide starvation of our CS irq-storms.
Comparing the impact on the maximum latency observed (that is the time
stolen from an RT process) over a 120s interval, repeated several times
(using gem_syslatency, similar to RT's cyclictest) while the system is
fully laden with i915 nops, we see that direct submission an actually
improve the worse case.
Maximum latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 2)
x Always using tasklets (a couple of >1000us outliers removed)
+ Only using tasklets from CS irq, direct submission of requests
+------------------------------------------------------------------------+
| + |
| + |
| + |
| + + |
| + + + |
| + + + + x x x |
| +++ + + + x x x x x x |
| +++ + ++ + + *x x x x x x |
| +++ + ++ + * *x x * x x x |
| + +++ + ++ * * +*xxx * x x xx |
| * +++ + ++++* *x+**xx+ * x x xxxx x |
| **x++++*++**+*x*x****x+ * +x xx xxxx x x |
|x* ******+***************++*+***xxxxxx* xx*x xxx + x+|
| |__________MA___________| |
| |______M__A________| |
+------------------------------------------------------------------------+
N Min Max Median Avg Stddev
x 118 91 186 124 125.28814 16.279137
+ 120 92 187 109 112.00833 13.458617
Difference at 95.0% confidence
-13.2798 +/- 3.79219
-10.5994% +/- 3.02677%
(Student's t, pooled s = 14.9237)
However the mean latency is adversely affected:
Mean latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 1)
x Always using tasklets
+ Only using tasklets from CS irq, direct submission of requests
+------------------------------------------------------------------------+
| xxxxxx + ++ |
| xxxxxx + ++ |
| xxxxxx + +++ ++ |
| xxxxxxx +++++ ++ |
| xxxxxxx +++++ ++ |
| xxxxxxx +++++ +++ |
| xxxxxxx + ++++++++++ |
| xxxxxxxx ++ ++++++++++ |
| xxxxxxxx ++ ++++++++++ |
| xxxxxxxxxx +++++++++++++++ |
| xxxxxxxxxxx x +++++++++++++++ |
|x xxxxxxxxxxxxx x + + ++++++++++++++++++ +|
| |__A__| |
| |____A___| |
+------------------------------------------------------------------------+
N Min Max Median Avg Stddev
x 120 3.506 3.727 3.631 3.6321417 0.02773109
+ 120 3.834 4.149 4.039 4.0375167 0.041221676
Difference at 95.0% confidence
0.405375 +/- 0.00888913
11.1608% +/- 0.244735%
(Student's t, pooled s = 0.03513)
However, since the mean latency corresponds to the amount of irqsoff
processing we have to do for a CS interrupt, we only need to speed that
up to benefit not just system latency but our own throughput.
v2: Remember to defer submissions when under reset.
v4: Only use direct submission for new requests
v5: Be aware that with mixing direct tasklet evaluation and deferred
tasklets, we may end up idling before running the deferred tasklet.
v6: Remove the redudant likely() from tasklet_is_enabled(), restrict the
annotation to reset_in_progress().
v7: Take the full timeline.lock when enabling perf_pmu stats as the
tasklet is no longer a valid guard. A consequence is that the stats are
now only valid for engines also using the timeline.lock to process
state.
Testcase: igt/gem_exec_latency/*rthog*
References: 27af5eea54d1 ("drm/i915: Move execlists irq handler to a bottom half")
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180628201211.13837-9-chris@chris-wilson.co.uk
2018-06-29 04:12:11 +08:00
|
|
|
spin_lock_irqsave(&engine->timeline.lock, flags);
|
|
|
|
write_seqlock(&engine->stats.lock);
|
2018-01-15 17:20:41 +08:00
|
|
|
|
|
|
|
if (unlikely(engine->stats.enabled == ~0)) {
|
|
|
|
err = -EBUSY;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
2018-01-11 15:30:31 +08:00
|
|
|
if (engine->stats.enabled++ == 0) {
|
|
|
|
const struct execlist_port *port = execlists->port;
|
|
|
|
unsigned int num_ports = execlists_num_ports(execlists);
|
|
|
|
|
2017-11-22 02:18:48 +08:00
|
|
|
engine->stats.enabled_at = ktime_get();
|
2018-01-11 15:30:31 +08:00
|
|
|
|
|
|
|
/* XXX submission method oblivious? */
|
|
|
|
while (num_ports-- && port_isset(port)) {
|
|
|
|
engine->stats.active++;
|
|
|
|
port++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (engine->stats.active)
|
|
|
|
engine->stats.start = engine->stats.enabled_at;
|
|
|
|
}
|
2017-11-22 02:18:48 +08:00
|
|
|
|
2018-01-15 17:20:41 +08:00
|
|
|
unlock:
|
drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on average! Deferring our work to a tasklet allowed us to do the
processing with irqs enabled, reducing the impact to an average of about
50us.
We have since eradicated the use of forcewaked mmio from inside the CSB
processing and ELSP submission, bringing the impact down to around 5us
(on Kabylake); an order of magnitude better than our measurements 2
years ago on Broadwell and only about 2x worse on average than the
gem_syslatency on an unladen system.
In this iteration of the tasklet-vs-direct submission debate, we seek a
compromise where by we submit new requests immediately to the HW but
defer processing the CS interrupt onto a tasklet. We gain the advantage
of low-latency and ksoftirqd avoidance when waking up the HW, while
avoiding the system-wide starvation of our CS irq-storms.
Comparing the impact on the maximum latency observed (that is the time
stolen from an RT process) over a 120s interval, repeated several times
(using gem_syslatency, similar to RT's cyclictest) while the system is
fully laden with i915 nops, we see that direct submission an actually
improve the worse case.
Maximum latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 2)
x Always using tasklets (a couple of >1000us outliers removed)
+ Only using tasklets from CS irq, direct submission of requests
+------------------------------------------------------------------------+
| + |
| + |
| + |
| + + |
| + + + |
| + + + + x x x |
| +++ + + + x x x x x x |
| +++ + ++ + + *x x x x x x |
| +++ + ++ + * *x x * x x x |
| + +++ + ++ * * +*xxx * x x xx |
| * +++ + ++++* *x+**xx+ * x x xxxx x |
| **x++++*++**+*x*x****x+ * +x xx xxxx x x |
|x* ******+***************++*+***xxxxxx* xx*x xxx + x+|
| |__________MA___________| |
| |______M__A________| |
+------------------------------------------------------------------------+
N Min Max Median Avg Stddev
x 118 91 186 124 125.28814 16.279137
+ 120 92 187 109 112.00833 13.458617
Difference at 95.0% confidence
-13.2798 +/- 3.79219
-10.5994% +/- 3.02677%
(Student's t, pooled s = 14.9237)
However the mean latency is adversely affected:
Mean latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 1)
x Always using tasklets
+ Only using tasklets from CS irq, direct submission of requests
+------------------------------------------------------------------------+
| xxxxxx + ++ |
| xxxxxx + ++ |
| xxxxxx + +++ ++ |
| xxxxxxx +++++ ++ |
| xxxxxxx +++++ ++ |
| xxxxxxx +++++ +++ |
| xxxxxxx + ++++++++++ |
| xxxxxxxx ++ ++++++++++ |
| xxxxxxxx ++ ++++++++++ |
| xxxxxxxxxx +++++++++++++++ |
| xxxxxxxxxxx x +++++++++++++++ |
|x xxxxxxxxxxxxx x + + ++++++++++++++++++ +|
| |__A__| |
| |____A___| |
+------------------------------------------------------------------------+
N Min Max Median Avg Stddev
x 120 3.506 3.727 3.631 3.6321417 0.02773109
+ 120 3.834 4.149 4.039 4.0375167 0.041221676
Difference at 95.0% confidence
0.405375 +/- 0.00888913
11.1608% +/- 0.244735%
(Student's t, pooled s = 0.03513)
However, since the mean latency corresponds to the amount of irqsoff
processing we have to do for a CS interrupt, we only need to speed that
up to benefit not just system latency but our own throughput.
v2: Remember to defer submissions when under reset.
v4: Only use direct submission for new requests
v5: Be aware that with mixing direct tasklet evaluation and deferred
tasklets, we may end up idling before running the deferred tasklet.
v6: Remove the redudant likely() from tasklet_is_enabled(), restrict the
annotation to reset_in_progress().
v7: Take the full timeline.lock when enabling perf_pmu stats as the
tasklet is no longer a valid guard. A consequence is that the stats are
now only valid for engines also using the timeline.lock to process
state.
Testcase: igt/gem_exec_latency/*rthog*
References: 27af5eea54d1 ("drm/i915: Move execlists irq handler to a bottom half")
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180628201211.13837-9-chris@chris-wilson.co.uk
2018-06-29 04:12:11 +08:00
|
|
|
write_sequnlock(&engine->stats.lock);
|
|
|
|
spin_unlock_irqrestore(&engine->timeline.lock, flags);
|
2017-11-22 02:18:48 +08:00
|
|
|
|
2018-01-15 17:20:41 +08:00
|
|
|
return err;
|
2017-11-22 02:18:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
ktime_t total = engine->stats.total;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the engine is executing something at the moment
|
|
|
|
* add it to the total.
|
|
|
|
*/
|
|
|
|
if (engine->stats.active)
|
|
|
|
total = ktime_add(total,
|
|
|
|
ktime_sub(ktime_get(), engine->stats.start));
|
|
|
|
|
|
|
|
return total;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_engine_get_busy_time() - Return current accumulated engine busyness
|
|
|
|
* @engine: engine to report on
|
|
|
|
*
|
|
|
|
* Returns accumulated time @engine was busy since engine stats were enabled.
|
|
|
|
*/
|
|
|
|
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
|
|
|
|
{
|
2018-04-26 15:47:16 +08:00
|
|
|
unsigned int seq;
|
2017-11-22 02:18:48 +08:00
|
|
|
ktime_t total;
|
|
|
|
|
2018-04-26 15:47:16 +08:00
|
|
|
do {
|
|
|
|
seq = read_seqbegin(&engine->stats.lock);
|
|
|
|
total = __intel_engine_get_busy_time(engine);
|
|
|
|
} while (read_seqretry(&engine->stats.lock, seq));
|
2017-11-22 02:18:48 +08:00
|
|
|
|
|
|
|
return total;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_disable_engine_stats() - Disable engine busy tracking on engine
|
|
|
|
* @engine: engine to disable stats collection
|
|
|
|
*
|
|
|
|
* Stops collecting the engine busyness data for @engine.
|
|
|
|
*/
|
|
|
|
void intel_disable_engine_stats(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
2017-11-29 18:28:05 +08:00
|
|
|
if (!intel_engine_supports_stats(engine))
|
2017-11-22 02:18:48 +08:00
|
|
|
return;
|
|
|
|
|
2018-04-26 15:47:16 +08:00
|
|
|
write_seqlock_irqsave(&engine->stats.lock, flags);
|
2017-11-22 02:18:48 +08:00
|
|
|
WARN_ON_ONCE(engine->stats.enabled == 0);
|
|
|
|
if (--engine->stats.enabled == 0) {
|
|
|
|
engine->stats.total = __intel_engine_get_busy_time(engine);
|
|
|
|
engine->stats.active = 0;
|
|
|
|
}
|
2018-04-26 15:47:16 +08:00
|
|
|
write_sequnlock_irqrestore(&engine->stats.lock, flags);
|
2017-11-22 02:18:48 +08:00
|
|
|
}
|
|
|
|
|
2017-02-14 01:15:14 +08:00
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
|
|
|
#include "selftests/mock_engine.c"
|
2018-03-15 02:26:51 +08:00
|
|
|
#include "selftests/intel_engine_cs.c"
|
2017-02-14 01:15:14 +08:00
|
|
|
#endif
|