229 lines
5.7 KiB
C
229 lines
5.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2018 Broadcom */
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/**
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* DOC: Broadcom V3D scheduling
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*
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* The shared DRM GPU scheduler is used to coordinate submitting jobs
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* to the hardware. Each DRM fd (roughly a client process) gets its
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* own scheduler entity, which will process jobs in order. The GPU
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* scheduler will round-robin between clients to submit the next job.
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*
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* For simplicity, and in order to keep latency low for interactive
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* jobs when bulk background jobs are queued up, we submit a new job
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* to the HW only when it has completed the last one, instead of
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* filling up the CT[01]Q FIFOs with jobs. Similarly, we use
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* v3d_job_dependency() to manage the dependency between bin and
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* render, instead of having the clients submit jobs with using the
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* HW's semaphores to interlock between them.
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*/
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#include <linux/kthread.h>
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#include "v3d_trace.h"
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static struct v3d_job *
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to_v3d_job(struct drm_sched_job *sched_job)
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{
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return container_of(sched_job, struct v3d_job, base);
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}
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static void
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v3d_job_free(struct drm_sched_job *sched_job)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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v3d_exec_put(job->exec);
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}
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/**
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* Returns the fences that the bin job depends on, one by one.
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* v3d_job_run() won't be called until all of them have been signaled.
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*/
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static struct dma_fence *
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v3d_job_dependency(struct drm_sched_job *sched_job,
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struct drm_sched_entity *s_entity)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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struct v3d_exec_info *exec = job->exec;
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enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
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struct dma_fence *fence;
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fence = job->in_fence;
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if (fence) {
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job->in_fence = NULL;
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return fence;
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}
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if (q == V3D_RENDER) {
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/* If we had a bin job, the render job definitely depends on
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* it. We first have to wait for bin to be scheduled, so that
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* its done_fence is created.
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*/
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fence = exec->bin_done_fence;
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if (fence) {
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exec->bin_done_fence = NULL;
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return fence;
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}
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}
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/* XXX: Wait on a fence for switching the GMP if necessary,
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* and then do so.
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*/
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return fence;
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}
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static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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struct v3d_exec_info *exec = job->exec;
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enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
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struct v3d_dev *v3d = exec->v3d;
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struct drm_device *dev = &v3d->drm;
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struct dma_fence *fence;
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unsigned long irqflags;
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if (unlikely(job->base.s_fence->finished.error))
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return NULL;
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/* Lock required around bin_job update vs
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* v3d_overflow_mem_work().
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*/
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spin_lock_irqsave(&v3d->job_lock, irqflags);
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if (q == V3D_BIN) {
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v3d->bin_job = job->exec;
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/* Clear out the overflow allocation, so we don't
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* reuse the overflow attached to a previous job.
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*/
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V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
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} else {
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v3d->render_job = job->exec;
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}
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spin_unlock_irqrestore(&v3d->job_lock, irqflags);
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/* Can we avoid this flush when q==RENDER? We need to be
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* careful of scheduling, though -- imagine job0 rendering to
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* texture and job1 reading, and them being executed as bin0,
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* bin1, render0, render1, so that render1's flush at bin time
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* wasn't enough.
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*/
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v3d_invalidate_caches(v3d);
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fence = v3d_fence_create(v3d, q);
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if (!fence)
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return fence;
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if (job->done_fence)
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dma_fence_put(job->done_fence);
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job->done_fence = dma_fence_get(fence);
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trace_v3d_submit_cl(dev, q == V3D_RENDER, to_v3d_fence(fence)->seqno,
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job->start, job->end);
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if (q == V3D_BIN) {
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if (exec->qma) {
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V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, exec->qma);
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V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, exec->qms);
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}
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if (exec->qts) {
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V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
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V3D_CLE_CT0QTS_ENABLE |
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exec->qts);
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}
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} else {
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/* XXX: Set the QCFG */
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}
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/* Set the current and end address of the control list.
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* Writing the end register is what starts the job.
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*/
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V3D_CORE_WRITE(0, V3D_CLE_CTNQBA(q), job->start);
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V3D_CORE_WRITE(0, V3D_CLE_CTNQEA(q), job->end);
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return fence;
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}
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static void
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v3d_job_timedout(struct drm_sched_job *sched_job)
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{
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struct v3d_job *job = to_v3d_job(sched_job);
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struct v3d_exec_info *exec = job->exec;
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struct v3d_dev *v3d = exec->v3d;
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enum v3d_queue q;
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mutex_lock(&v3d->reset_lock);
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/* block scheduler */
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for (q = 0; q < V3D_MAX_QUEUES; q++) {
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struct drm_gpu_scheduler *sched = &v3d->queue[q].sched;
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kthread_park(sched->thread);
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drm_sched_hw_job_reset(sched, (sched_job->sched == sched ?
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sched_job : NULL));
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}
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/* get the GPU back into the init state */
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v3d_reset(v3d);
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/* Unblock schedulers and restart their jobs. */
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for (q = 0; q < V3D_MAX_QUEUES; q++) {
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drm_sched_job_recovery(&v3d->queue[q].sched);
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kthread_unpark(v3d->queue[q].sched.thread);
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}
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mutex_unlock(&v3d->reset_lock);
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}
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static const struct drm_sched_backend_ops v3d_sched_ops = {
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.dependency = v3d_job_dependency,
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.run_job = v3d_job_run,
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.timedout_job = v3d_job_timedout,
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.free_job = v3d_job_free
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};
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int
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v3d_sched_init(struct v3d_dev *v3d)
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{
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int hw_jobs_limit = 1;
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int job_hang_limit = 0;
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int hang_limit_ms = 500;
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int ret;
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ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
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&v3d_sched_ops,
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hw_jobs_limit, job_hang_limit,
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msecs_to_jiffies(hang_limit_ms),
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"v3d_bin");
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if (ret) {
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dev_err(v3d->dev, "Failed to create bin scheduler: %d.", ret);
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return ret;
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}
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ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
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&v3d_sched_ops,
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hw_jobs_limit, job_hang_limit,
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msecs_to_jiffies(hang_limit_ms),
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"v3d_render");
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if (ret) {
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dev_err(v3d->dev, "Failed to create render scheduler: %d.",
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ret);
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drm_sched_fini(&v3d->queue[V3D_BIN].sched);
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return ret;
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}
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return 0;
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}
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void
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v3d_sched_fini(struct v3d_dev *v3d)
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{
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enum v3d_queue q;
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for (q = 0; q < V3D_MAX_QUEUES; q++)
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drm_sched_fini(&v3d->queue[q].sched);
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}
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