2016-03-07 18:00:53 +08:00
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/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* ARM Mali DP500/DP550/DP650 driver (crtc operations)
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <linux/clk.h>
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2017-03-22 18:44:57 +08:00
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#include <linux/pm_runtime.h>
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2016-03-07 18:00:53 +08:00
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#include <video/videomode.h>
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#include "malidp_drv.h"
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#include "malidp_hw.h"
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2017-05-19 08:52:17 +08:00
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static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
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const struct drm_display_mode *mode)
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2016-03-07 18:00:53 +08:00
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{
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struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
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struct malidp_hw_device *hwdev = malidp->dev;
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/*
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* check that the hardware can drive the required clock rate,
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* but skip the check if the clock is meant to be disabled (req_rate = 0)
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*/
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long rate, req_rate = mode->crtc_clock * 1000;
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if (req_rate) {
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rate = clk_round_rate(hwdev->pxlclk, req_rate);
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if (rate != req_rate) {
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DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
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req_rate);
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2017-05-19 08:52:17 +08:00
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return MODE_NOCLOCK;
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2016-03-07 18:00:53 +08:00
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}
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}
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2017-05-19 08:52:17 +08:00
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return MODE_OK;
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2016-03-07 18:00:53 +08:00
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}
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2017-06-30 17:36:44 +08:00
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static void malidp_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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2016-03-07 18:00:53 +08:00
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{
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struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
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struct malidp_hw_device *hwdev = malidp->dev;
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struct videomode vm;
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2017-03-22 18:44:57 +08:00
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int err = pm_runtime_get_sync(crtc->dev->dev);
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2016-03-07 18:00:53 +08:00
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2017-03-22 18:44:57 +08:00
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if (err < 0) {
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DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err);
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return;
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}
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2016-03-07 18:00:53 +08:00
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2017-03-22 18:44:57 +08:00
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drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
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2016-03-07 18:00:53 +08:00
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clk_prepare_enable(hwdev->pxlclk);
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2017-02-15 22:00:15 +08:00
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/* We rely on firmware to set mclk to a sensible level. */
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2016-03-07 18:00:53 +08:00
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clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
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2017-08-31 22:48:43 +08:00
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hwdev->hw->modeset(hwdev, &vm);
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hwdev->hw->leave_config_mode(hwdev);
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2016-03-07 18:00:53 +08:00
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drm_crtc_vblank_on(crtc);
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}
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2017-06-30 17:36:45 +08:00
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static void malidp_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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2016-03-07 18:00:53 +08:00
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{
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struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
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struct malidp_hw_device *hwdev = malidp->dev;
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2017-03-22 18:44:57 +08:00
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int err;
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2016-03-07 18:00:53 +08:00
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2017-09-01 00:39:24 +08:00
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/* always disable planes on the CRTC that is being turned off */
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drm_atomic_helper_disable_planes_on_crtc(old_state, false);
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2016-03-07 18:00:53 +08:00
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drm_crtc_vblank_off(crtc);
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2017-08-31 22:48:43 +08:00
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hwdev->hw->enter_config_mode(hwdev);
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2016-03-07 18:00:53 +08:00
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clk_disable_unprepare(hwdev->pxlclk);
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2017-03-22 18:44:57 +08:00
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err = pm_runtime_put(crtc->dev->dev);
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if (err < 0) {
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DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err);
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}
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2016-03-07 18:00:53 +08:00
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}
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2017-02-01 22:48:50 +08:00
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static const struct gamma_curve_segment {
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u16 start;
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u16 end;
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} segments[MALIDP_COEFFTAB_NUM_COEFFS] = {
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/* sector 0 */
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{ 0, 0 }, { 1, 1 }, { 2, 2 }, { 3, 3 },
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{ 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
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{ 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 },
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{ 12, 12 }, { 13, 13 }, { 14, 14 }, { 15, 15 },
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/* sector 1 */
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{ 16, 19 }, { 20, 23 }, { 24, 27 }, { 28, 31 },
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/* sector 2 */
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{ 32, 39 }, { 40, 47 }, { 48, 55 }, { 56, 63 },
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/* sector 3 */
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{ 64, 79 }, { 80, 95 }, { 96, 111 }, { 112, 127 },
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/* sector 4 */
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{ 128, 159 }, { 160, 191 }, { 192, 223 }, { 224, 255 },
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/* sector 5 */
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{ 256, 319 }, { 320, 383 }, { 384, 447 }, { 448, 511 },
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/* sector 6 */
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{ 512, 639 }, { 640, 767 }, { 768, 895 }, { 896, 1023 },
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{ 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 },
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{ 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 },
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{ 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 },
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{ 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 },
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{ 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 },
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{ 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 },
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};
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#define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff)))
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static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob,
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u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS])
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{
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struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data;
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int i;
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for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) {
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u32 a, b, delta_in, out_start, out_end;
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delta_in = segments[i].end - segments[i].start;
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/* DP has 12-bit internal precision for its LUTs. */
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out_start = drm_color_lut_extract(lut[segments[i].start].green,
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12);
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out_end = drm_color_lut_extract(lut[segments[i].end].green, 12);
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a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in;
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b = out_start;
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coeffs[i] = DE_COEFTAB_DATA(a, b);
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}
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}
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/*
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* Check if there is a new gamma LUT and if it is of an acceptable size. Also,
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* reject any LUTs that use distinct red, green, and blue curves.
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*/
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static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
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struct drm_color_lut *lut;
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size_t lut_size;
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int i;
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if (!state->color_mgmt_changed || !state->gamma_lut)
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return 0;
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if (crtc->state->gamma_lut &&
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(crtc->state->gamma_lut->base.id == state->gamma_lut->base.id))
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return 0;
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if (state->gamma_lut->length % sizeof(struct drm_color_lut))
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return -EINVAL;
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lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut);
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if (lut_size != MALIDP_GAMMA_LUT_SIZE)
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return -EINVAL;
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lut = (struct drm_color_lut *)state->gamma_lut->data;
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for (i = 0; i < lut_size; ++i)
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if (!((lut[i].red == lut[i].green) &&
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(lut[i].red == lut[i].blue)))
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return -EINVAL;
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if (!state->mode_changed) {
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int ret;
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state->mode_changed = true;
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/*
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* Kerneldoc for drm_atomic_helper_check_modeset mandates that
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* it be invoked when the driver sets ->mode_changed. Since
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* changing the gamma LUT doesn't depend on any external
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* resources, it is safe to call it only once.
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*/
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ret = drm_atomic_helper_check_modeset(crtc->dev, state->state);
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if (ret)
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return ret;
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}
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malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs);
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return 0;
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}
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2017-02-13 20:49:03 +08:00
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/*
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* Check if there is a new CTM and if it contains valid input. Valid here means
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* that the number is inside the representable range for a Q3.12 number,
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* excluding truncating the fractional part of the input data.
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*
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* The COLORADJ registers can be changed atomically.
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*/
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static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
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struct drm_color_ctm *ctm;
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int i;
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if (!state->color_mgmt_changed)
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return 0;
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if (!state->ctm)
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return 0;
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if (crtc->state->ctm && (crtc->state->ctm->base.id ==
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state->ctm->base.id))
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return 0;
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/*
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* The size of the ctm is checked in
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* drm_atomic_replace_property_blob_from_id.
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*/
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ctm = (struct drm_color_ctm *)state->ctm->data;
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for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
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/* Convert from S31.32 to Q3.12. */
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s64 val = ctm->matrix[i];
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u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
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GENMASK_ULL(14, 0);
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/*
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* Convert to 2s complement and check the destination's top bit
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* for overflow. NB: Can't check before converting or it'd
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* incorrectly reject the case:
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* sign == 1
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* mag == 0x2000
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*/
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if (val & BIT_ULL(63))
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mag = ~mag + 1;
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if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
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return -EINVAL;
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mc->coloradj_coeffs[i] = mag;
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}
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return 0;
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}
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2017-02-13 23:14:05 +08:00
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static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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2017-02-13 23:09:01 +08:00
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struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
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struct malidp_hw_device *hwdev = malidp->dev;
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2017-02-13 23:14:05 +08:00
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struct malidp_crtc_state *cs = to_malidp_crtc_state(state);
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struct malidp_se_config *s = &cs->scaler_config;
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struct drm_plane *plane;
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2017-02-13 23:09:01 +08:00
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struct videomode vm;
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2017-02-13 23:14:05 +08:00
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const struct drm_plane_state *pstate;
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u32 h_upscale_factor = 0; /* U16.16 */
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u32 v_upscale_factor = 0; /* U16.16 */
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u8 scaling = cs->scaled_planes_mask;
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2017-02-13 23:09:01 +08:00
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int ret;
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2017-02-13 23:14:05 +08:00
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if (!scaling) {
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s->scale_enable = false;
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2017-02-13 23:09:01 +08:00
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goto mclk_calc;
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2017-02-13 23:14:05 +08:00
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}
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/* The scaling engine can only handle one plane at a time. */
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if (scaling & (scaling - 1))
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return -EINVAL;
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drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
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struct malidp_plane *mp = to_malidp_plane(plane);
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u32 phase;
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if (!(mp->layer->id & scaling))
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continue;
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/*
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* Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h]
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* to get the U16.16 result.
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*/
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2017-04-26 03:56:53 +08:00
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h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
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pstate->src_w);
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v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
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pstate->src_h);
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2017-02-13 23:14:05 +08:00
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2017-02-06 20:20:56 +08:00
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s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
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(v_upscale_factor >> 16) >= 2);
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2017-12-20 00:20:16 +08:00
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if (pstate->rotation & MALIDP_ROTATED_MASK) {
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s->input_w = pstate->src_h >> 16;
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s->input_h = pstate->src_w >> 16;
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} else {
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s->input_w = pstate->src_w >> 16;
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s->input_h = pstate->src_h >> 16;
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}
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2017-02-13 23:14:05 +08:00
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s->output_w = pstate->crtc_w;
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s->output_h = pstate->crtc_h;
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#define SE_N_PHASE 4
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#define SE_SHIFT_N_PHASE 12
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/* Calculate initial_phase and delta_phase for horizontal. */
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phase = s->input_w;
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s->h_init_phase =
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((phase << SE_N_PHASE) / s->output_w + 1) / 2;
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phase = s->input_w;
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phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
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s->h_delta_phase = phase / s->output_w;
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|
|
|
/* Same for vertical. */
|
|
|
|
phase = s->input_h;
|
|
|
|
s->v_init_phase =
|
|
|
|
((phase << SE_N_PHASE) / s->output_h + 1) / 2;
|
|
|
|
|
|
|
|
phase = s->input_h;
|
|
|
|
phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
|
|
|
|
s->v_delta_phase = phase / s->output_h;
|
|
|
|
#undef SE_N_PHASE
|
|
|
|
#undef SE_SHIFT_N_PHASE
|
|
|
|
s->plane_src_id = mp->layer->id;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->scale_enable = true;
|
|
|
|
s->hcoeff = malidp_se_select_coeffs(h_upscale_factor);
|
|
|
|
s->vcoeff = malidp_se_select_coeffs(v_upscale_factor);
|
2017-02-13 23:09:01 +08:00
|
|
|
|
|
|
|
mclk_calc:
|
|
|
|
drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
|
2017-08-31 22:48:43 +08:00
|
|
|
ret = hwdev->hw->se_calc_mclk(hwdev, s, &vm);
|
2017-02-13 23:09:01 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return -EINVAL;
|
2017-02-13 23:14:05 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-07 18:00:53 +08:00
|
|
|
static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *state)
|
|
|
|
{
|
|
|
|
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
|
|
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
struct drm_plane *plane;
|
|
|
|
const struct drm_plane_state *pstate;
|
|
|
|
u32 rot_mem_free, rot_mem_usable;
|
|
|
|
int rotated_planes = 0;
|
2017-02-13 20:49:03 +08:00
|
|
|
int ret;
|
2016-03-07 18:00:53 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* check if there is enough rotation memory available for planes
|
|
|
|
* that need 90° and 270° rotation. Each plane has set its required
|
|
|
|
* memory size in the ->plane_check() callback, here we only make
|
|
|
|
* sure that the sums are less that the total usable memory.
|
|
|
|
*
|
|
|
|
* The rotation memory allocation algorithm (for each plane):
|
|
|
|
* a. If no more rotated planes exist, all remaining rotate
|
|
|
|
* memory in the bank is available for use by the plane.
|
|
|
|
* b. If other rotated planes exist, and plane's layer ID is
|
|
|
|
* DE_VIDEO1, it can use all the memory from first bank if
|
|
|
|
* secondary rotation memory bank is available, otherwise it can
|
|
|
|
* use up to half the bank's memory.
|
|
|
|
* c. If other rotated planes exist, and plane's layer ID is not
|
|
|
|
* DE_VIDEO1, it can use half of the available memory
|
|
|
|
*
|
|
|
|
* Note: this algorithm assumes that the order in which the planes are
|
|
|
|
* checked always has DE_VIDEO1 plane first in the list if it is
|
|
|
|
* rotated. Because that is how we create the planes in the first
|
|
|
|
* place, under current DRM version things work, but if ever the order
|
|
|
|
* in which drm_atomic_crtc_state_for_each_plane() iterates over planes
|
|
|
|
* changes, we need to pre-sort the planes before validation.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* first count the number of rotated planes */
|
|
|
|
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
|
|
|
|
if (pstate->rotation & MALIDP_ROTATED_MASK)
|
|
|
|
rotated_planes++;
|
|
|
|
}
|
|
|
|
|
|
|
|
rot_mem_free = hwdev->rotation_memory[0];
|
|
|
|
/*
|
|
|
|
* if we have more than 1 plane using rotation memory, use the second
|
|
|
|
* block of rotation memory as well
|
|
|
|
*/
|
|
|
|
if (rotated_planes > 1)
|
|
|
|
rot_mem_free += hwdev->rotation_memory[1];
|
|
|
|
|
|
|
|
/* now validate the rotation memory requirements */
|
|
|
|
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
|
|
|
|
struct malidp_plane *mp = to_malidp_plane(plane);
|
|
|
|
struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
|
|
|
|
|
|
|
|
if (pstate->rotation & MALIDP_ROTATED_MASK) {
|
|
|
|
/* process current plane */
|
|
|
|
rotated_planes--;
|
|
|
|
|
|
|
|
if (!rotated_planes) {
|
|
|
|
/* no more rotated planes, we can use what's left */
|
|
|
|
rot_mem_usable = rot_mem_free;
|
|
|
|
} else {
|
|
|
|
if ((mp->layer->id != DE_VIDEO1) ||
|
|
|
|
(hwdev->rotation_memory[1] == 0))
|
|
|
|
rot_mem_usable = rot_mem_free / 2;
|
|
|
|
else
|
|
|
|
rot_mem_usable = hwdev->rotation_memory[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
rot_mem_free -= rot_mem_usable;
|
|
|
|
|
|
|
|
if (ms->rotmem_size > rot_mem_usable)
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-02-13 20:49:03 +08:00
|
|
|
ret = malidp_crtc_atomic_check_gamma(crtc, state);
|
|
|
|
ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state);
|
2017-02-13 23:14:05 +08:00
|
|
|
ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state);
|
2017-02-13 20:49:03 +08:00
|
|
|
|
|
|
|
return ret;
|
2016-03-07 18:00:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
|
2017-05-19 08:52:17 +08:00
|
|
|
.mode_valid = malidp_crtc_mode_valid,
|
2016-03-07 18:00:53 +08:00
|
|
|
.atomic_check = malidp_crtc_atomic_check,
|
2017-06-30 17:36:44 +08:00
|
|
|
.atomic_enable = malidp_crtc_atomic_enable,
|
2017-06-30 17:36:45 +08:00
|
|
|
.atomic_disable = malidp_crtc_atomic_disable,
|
2016-03-07 18:00:53 +08:00
|
|
|
};
|
|
|
|
|
2017-02-01 22:48:49 +08:00
|
|
|
static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
|
|
|
|
{
|
2017-02-01 22:48:50 +08:00
|
|
|
struct malidp_crtc_state *state, *old_state;
|
2017-02-01 22:48:49 +08:00
|
|
|
|
|
|
|
if (WARN_ON(!crtc->state))
|
|
|
|
return NULL;
|
|
|
|
|
2017-02-01 22:48:50 +08:00
|
|
|
old_state = to_malidp_crtc_state(crtc->state);
|
2017-02-01 22:48:49 +08:00
|
|
|
state = kmalloc(sizeof(*state), GFP_KERNEL);
|
|
|
|
if (!state)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
|
2017-02-01 22:48:50 +08:00
|
|
|
memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
|
|
|
|
sizeof(state->gamma_coeffs));
|
2017-02-13 20:49:03 +08:00
|
|
|
memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
|
|
|
|
sizeof(state->coloradj_coeffs));
|
2017-02-13 23:14:05 +08:00
|
|
|
memcpy(&state->scaler_config, &old_state->scaler_config,
|
|
|
|
sizeof(state->scaler_config));
|
|
|
|
state->scaled_planes_mask = 0;
|
2017-02-01 22:48:49 +08:00
|
|
|
|
|
|
|
return &state->base;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void malidp_crtc_reset(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct malidp_crtc_state *state = NULL;
|
|
|
|
|
|
|
|
if (crtc->state) {
|
|
|
|
state = to_malidp_crtc_state(crtc->state);
|
|
|
|
__drm_atomic_helper_crtc_destroy_state(crtc->state);
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(state);
|
|
|
|
state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
|
|
if (state) {
|
|
|
|
crtc->state = &state->base;
|
|
|
|
crtc->state->crtc = crtc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *state)
|
|
|
|
{
|
|
|
|
struct malidp_crtc_state *mali_state = NULL;
|
|
|
|
|
|
|
|
if (state) {
|
|
|
|
mali_state = to_malidp_crtc_state(state);
|
|
|
|
__drm_atomic_helper_crtc_destroy_state(state);
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(mali_state);
|
|
|
|
}
|
|
|
|
|
2017-02-07 17:16:17 +08:00
|
|
|
static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
|
|
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
|
|
|
|
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
|
2017-08-31 22:48:43 +08:00
|
|
|
hwdev->hw->map.de_irq_map.vsync_irq);
|
2017-02-07 17:16:17 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
|
|
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
|
|
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
|
2017-08-31 22:48:43 +08:00
|
|
|
hwdev->hw->map.de_irq_map.vsync_irq);
|
2017-02-07 17:16:17 +08:00
|
|
|
}
|
|
|
|
|
2016-03-07 18:00:53 +08:00
|
|
|
static const struct drm_crtc_funcs malidp_crtc_funcs = {
|
2017-02-01 22:48:50 +08:00
|
|
|
.gamma_set = drm_atomic_helper_legacy_gamma_set,
|
2016-03-07 18:00:53 +08:00
|
|
|
.destroy = drm_crtc_cleanup,
|
|
|
|
.set_config = drm_atomic_helper_set_config,
|
|
|
|
.page_flip = drm_atomic_helper_page_flip,
|
2017-02-01 22:48:49 +08:00
|
|
|
.reset = malidp_crtc_reset,
|
|
|
|
.atomic_duplicate_state = malidp_crtc_duplicate_state,
|
|
|
|
.atomic_destroy_state = malidp_crtc_destroy_state,
|
2017-02-07 17:16:17 +08:00
|
|
|
.enable_vblank = malidp_crtc_enable_vblank,
|
|
|
|
.disable_vblank = malidp_crtc_disable_vblank,
|
2016-03-07 18:00:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
int malidp_crtc_init(struct drm_device *drm)
|
|
|
|
{
|
|
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
|
|
struct drm_plane *primary = NULL, *plane;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = malidp_de_planes_init(drm);
|
|
|
|
if (ret < 0) {
|
|
|
|
DRM_ERROR("Failed to initialise planes\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_for_each_plane(plane, drm) {
|
|
|
|
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
|
|
|
|
primary = plane;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!primary) {
|
|
|
|
DRM_ERROR("no primary plane found\n");
|
2018-01-18 05:55:29 +08:00
|
|
|
return -EINVAL;
|
2016-03-07 18:00:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
|
|
|
|
&malidp_crtc_funcs, NULL);
|
2017-02-01 22:48:50 +08:00
|
|
|
if (ret)
|
2018-01-18 05:55:29 +08:00
|
|
|
return ret;
|
2016-03-07 18:00:53 +08:00
|
|
|
|
2017-02-01 22:48:50 +08:00
|
|
|
drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
|
|
|
|
drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
|
2017-02-06 20:20:56 +08:00
|
|
|
/* No inverse-gamma: it is per-plane. */
|
2017-02-13 20:49:03 +08:00
|
|
|
drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
|
2017-02-01 22:48:50 +08:00
|
|
|
|
2017-02-06 20:20:56 +08:00
|
|
|
malidp_se_set_enh_coeffs(malidp->dev);
|
|
|
|
|
2017-02-01 22:48:50 +08:00
|
|
|
return 0;
|
2016-03-07 18:00:53 +08:00
|
|
|
}
|