2020-01-07 21:40:09 +08:00
|
|
|
/* SPDX-License-Identifier: MIT */
|
|
|
|
/*
|
|
|
|
* Copyright © 2020 Intel Corporation
|
|
|
|
*
|
|
|
|
* Please try to maintain the following order within this file unless it makes
|
|
|
|
* sense to do otherwise. From top to bottom:
|
|
|
|
* 1. typedefs
|
|
|
|
* 2. #defines, and macros
|
|
|
|
* 3. structure definitions
|
|
|
|
* 4. function prototypes
|
|
|
|
*
|
|
|
|
* Within each section, please try to order by generation in ascending order,
|
|
|
|
* from top to bottom (ie. gen6 on the top, gen8 on the bottom).
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __INTEL_GTT_H__
|
|
|
|
#define __INTEL_GTT_H__
|
|
|
|
|
|
|
|
#include <linux/io-mapping.h>
|
|
|
|
#include <linux/kref.h>
|
|
|
|
#include <linux/mm.h>
|
|
|
|
#include <linux/pagevec.h>
|
|
|
|
#include <linux/scatterlist.h>
|
|
|
|
#include <linux/workqueue.h>
|
|
|
|
|
|
|
|
#include <drm/drm_mm.h>
|
|
|
|
|
|
|
|
#include "gt/intel_reset.h"
|
|
|
|
#include "i915_selftest.h"
|
|
|
|
#include "i915_vma_types.h"
|
|
|
|
|
|
|
|
#define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
|
|
|
|
#define DBG(...) trace_printk(__VA_ARGS__)
|
|
|
|
#else
|
|
|
|
#define DBG(...)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
|
|
|
|
|
|
|
|
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
|
|
|
|
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
|
|
|
|
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
|
|
|
|
|
|
|
|
#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
|
|
|
|
#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
|
|
|
|
|
|
|
|
#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
|
|
|
|
|
|
|
|
#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
|
|
|
|
|
|
|
|
#define I915_FENCE_REG_NONE -1
|
|
|
|
#define I915_MAX_NUM_FENCES 32
|
|
|
|
/* 32 fences + sign bit for FENCE_REG_NONE */
|
|
|
|
#define I915_MAX_NUM_FENCE_BITS 6
|
|
|
|
|
|
|
|
typedef u32 gen6_pte_t;
|
|
|
|
typedef u64 gen8_pte_t;
|
|
|
|
|
|
|
|
#define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
|
|
|
|
|
|
|
|
#define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
|
|
|
|
#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
|
|
|
|
#define I915_PDES 512
|
|
|
|
#define I915_PDE_MASK (I915_PDES - 1)
|
|
|
|
|
|
|
|
/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
|
|
|
|
#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
|
|
|
|
#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
|
|
|
|
#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
|
|
|
|
#define GEN6_PTE_CACHE_LLC (2 << 1)
|
|
|
|
#define GEN6_PTE_UNCACHED (1 << 1)
|
|
|
|
#define GEN6_PTE_VALID REG_BIT(0)
|
|
|
|
|
|
|
|
#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
|
|
|
|
#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
|
|
|
|
#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
|
|
|
|
#define GEN6_PDE_SHIFT 22
|
|
|
|
#define GEN6_PDE_VALID REG_BIT(0)
|
|
|
|
#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
|
|
|
|
|
|
|
|
#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
|
|
|
|
|
|
|
|
#define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
|
|
|
|
#define BYT_PTE_WRITEABLE REG_BIT(1)
|
|
|
|
|
2021-02-04 01:12:31 +08:00
|
|
|
#define GEN12_PPGTT_PTE_LM BIT_ULL(11)
|
|
|
|
|
|
|
|
#define GEN12_GGTT_PTE_LM BIT_ULL(1)
|
2021-02-04 01:12:30 +08:00
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
/*
|
|
|
|
* Cacheability Control is a 4-bit value. The low three bits are stored in bits
|
|
|
|
* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
|
|
|
|
*/
|
|
|
|
#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
|
|
|
|
(((bits) & 0x8) << (11 - 3)))
|
|
|
|
#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
|
|
|
|
#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
|
|
|
|
#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
|
|
|
|
#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
|
|
|
|
#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
|
|
|
|
#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
|
|
|
|
#define HSW_PTE_UNCACHED (0)
|
|
|
|
#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
|
|
|
|
#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GEN8 32b style address is defined as a 3 level page table:
|
|
|
|
* 31:30 | 29:21 | 20:12 | 11:0
|
|
|
|
* PDPE | PDE | PTE | offset
|
|
|
|
* The difference as compared to normal x86 3 level page table is the PDPEs are
|
|
|
|
* programmed via register.
|
|
|
|
*
|
|
|
|
* GEN8 48b style address is defined as a 4 level page table:
|
|
|
|
* 47:39 | 38:30 | 29:21 | 20:12 | 11:0
|
|
|
|
* PML4E | PDPE | PDE | PTE | offset
|
|
|
|
*/
|
|
|
|
#define GEN8_3LVL_PDPES 4
|
|
|
|
|
|
|
|
#define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
|
|
|
|
#define PPAT_CACHED_PDE 0 /* WB LLC */
|
|
|
|
#define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
|
|
|
|
#define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
|
|
|
|
|
|
|
|
#define CHV_PPAT_SNOOP REG_BIT(6)
|
|
|
|
#define GEN8_PPAT_AGE(x) ((x)<<4)
|
|
|
|
#define GEN8_PPAT_LLCeLLC (3<<2)
|
|
|
|
#define GEN8_PPAT_LLCELLC (2<<2)
|
|
|
|
#define GEN8_PPAT_LLC (1<<2)
|
|
|
|
#define GEN8_PPAT_WB (3<<0)
|
|
|
|
#define GEN8_PPAT_WT (2<<0)
|
|
|
|
#define GEN8_PPAT_WC (1<<0)
|
|
|
|
#define GEN8_PPAT_UC (0<<0)
|
|
|
|
#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
|
|
|
|
#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
|
|
|
|
|
2021-12-07 05:52:45 +08:00
|
|
|
#define GEN8_PAGE_PRESENT BIT_ULL(0)
|
|
|
|
#define GEN8_PAGE_RW BIT_ULL(1)
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
#define GEN8_PDE_IPS_64K BIT(11)
|
|
|
|
#define GEN8_PDE_PS_2M BIT(7)
|
|
|
|
|
2020-07-30 00:42:18 +08:00
|
|
|
enum i915_cache_level;
|
|
|
|
|
|
|
|
struct drm_i915_gem_object;
|
2020-03-16 19:38:46 +08:00
|
|
|
struct i915_fence_reg;
|
2020-07-30 00:42:18 +08:00
|
|
|
struct i915_vma;
|
|
|
|
struct intel_gt;
|
2020-03-16 19:38:46 +08:00
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
#define for_each_sgt_daddr(__dp, __iter, __sgt) \
|
|
|
|
__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
|
|
|
|
|
|
|
|
struct i915_page_table {
|
2020-07-30 00:42:18 +08:00
|
|
|
struct drm_i915_gem_object *base;
|
2020-07-30 00:42:17 +08:00
|
|
|
union {
|
|
|
|
atomic_t used;
|
|
|
|
struct i915_page_table *stash;
|
|
|
|
};
|
2020-01-07 21:40:09 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct i915_page_directory {
|
|
|
|
struct i915_page_table pt;
|
|
|
|
spinlock_t lock;
|
drm/i915/gt: Shrink i915_page_directory's slab bucket
kmalloc uses power-of-two slab buckets for small allocations (up to a
few pages). Since i915_page_directory is a page of pointers, plus a
couple more, this is rounded up to 8K, and we waste nearly 50% of that
allocation. Long terms this leads to poor memory utilisation, bloating
the kernel footprint, but the problem is exacerbated by our conservative
preallocation scheme for binding VMA. As we are required to allocate all
levels for each vma just in case we need to insert them upon binding,
this leads to a large multiplication factor for a single page vma. By
halving the allocation we need for the page directory structure, we
halve the impact of that factor, bringing workloads that once fitted into
memory, hopefully back to fitting into memory.
We maintain the split between i915_page_directory and i915_page_table as
we only need half the allocation for the lowest, most populous, level.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200729164219.5737-3-chris@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2020-07-30 00:42:19 +08:00
|
|
|
void **entry;
|
2020-01-07 21:40:09 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
#define __px_choose_expr(x, type, expr, other) \
|
|
|
|
__builtin_choose_expr( \
|
|
|
|
__builtin_types_compatible_p(typeof(x), type) || \
|
|
|
|
__builtin_types_compatible_p(typeof(x), const type), \
|
|
|
|
({ type __x = (type)(x); expr; }), \
|
|
|
|
other)
|
|
|
|
|
|
|
|
#define px_base(px) \
|
2020-07-30 00:42:18 +08:00
|
|
|
__px_choose_expr(px, struct drm_i915_gem_object *, __x, \
|
|
|
|
__px_choose_expr(px, struct i915_page_table *, __x->base, \
|
|
|
|
__px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \
|
|
|
|
(void)0)))
|
|
|
|
|
|
|
|
struct page *__px_page(struct drm_i915_gem_object *p);
|
|
|
|
dma_addr_t __px_dma(struct drm_i915_gem_object *p);
|
|
|
|
#define px_dma(px) (__px_dma(px_base(px)))
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2021-04-27 16:54:13 +08:00
|
|
|
void *__px_vaddr(struct drm_i915_gem_object *p);
|
|
|
|
#define px_vaddr(px) (__px_vaddr(px_base(px)))
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
#define px_pt(px) \
|
|
|
|
__px_choose_expr(px, struct i915_page_table *, __x, \
|
|
|
|
__px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
|
|
|
|
(void)0))
|
|
|
|
#define px_used(px) (&px_pt(px)->used)
|
|
|
|
|
2020-07-30 00:42:17 +08:00
|
|
|
struct i915_vm_pt_stash {
|
|
|
|
/* preallocated chains of page tables/directories */
|
|
|
|
struct i915_page_table *pt[2];
|
|
|
|
};
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
struct i915_vma_ops {
|
|
|
|
/* Map an object into an address space with the given cache flags. */
|
2020-07-30 00:42:17 +08:00
|
|
|
void (*bind_vma)(struct i915_address_space *vm,
|
|
|
|
struct i915_vm_pt_stash *stash,
|
|
|
|
struct i915_vma *vma,
|
|
|
|
enum i915_cache_level cache_level,
|
|
|
|
u32 flags);
|
2020-01-07 21:40:09 +08:00
|
|
|
/*
|
|
|
|
* Unmap an object from an address space. This usually consists of
|
|
|
|
* setting the valid PTE entries to a reserved scratch page.
|
|
|
|
*/
|
2020-07-03 18:25:19 +08:00
|
|
|
void (*unbind_vma)(struct i915_address_space *vm,
|
|
|
|
struct i915_vma *vma);
|
2020-01-07 21:40:09 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct i915_address_space {
|
|
|
|
struct kref ref;
|
drm/i915: Stop rcu support for i915_address_space
The full audit is quite a bit of work:
- i915_dpt has very simple lifetime (somehow we create a display pagetable vm
per object, so its _very_ simple, there's only ever a single vma in there),
and uses i915_vm_close(), which internally does a i915_vm_put(). No rcu.
Aside: wtf is i915_dpt doing in the intel_display.c garbage collector as a new
feature, instead of added as a separate file with some clean-ish interface.
Also, i915_dpt unfortunately re-introduces some coding patterns from
pre-dma_resv_lock conversion times.
- i915_gem_proto_ctx is fully refcounted and no rcu, all protected by
fpriv->proto_context_lock.
- i915_gem_context is itself rcu protected, and that might leak to anything it
points at. Before
commit cf977e18610e66e48c31619e7e0cfa871be9eada
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Dec 2 11:21:40 2020 +0000
drm/i915/gem: Spring clean debugfs
and
commit db80a1294c231b6ac725085f046bb2931e00c9db
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Jan 18 11:08:54 2021 +0000
drm/i915/gem: Remove per-client stats from debugfs/i915_gem_objects
we had a bunch of debugfs files that relied on rcu protecting everything, but
those are gone now. The main one was removed even earlier with
There doesn't seem to be anything left that's actually protecting
stuff now that the ctx->vm itself is invariant. See
commit ccbc1b97948ab671335e950271e39766729736c3
Author: Jason Ekstrand <jason@jlekstrand.net>
Date: Thu Jul 8 10:48:30 2021 -0500
drm/i915/gem: Don't allow changing the VM on running contexts (v4)
Note that we drop the vm refcount before the final release of the gem context
refcount, so this is all very dangerous even without rcu. Note that aside from
later on creating new engines (a defunct feature) and debug output we're never
looked at gem_ctx->vm for anything functional, hence why this is ok.
Fingers crossed.
Preceeding patches removed all vestiges of rcu use from gem_ctx->vm
derferencing to make it clear it's really not used.
The gem_ctx->rcu protection was introduced in
commit a4e7ccdac38ec8335d9e4e2656c1a041c77feae1
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Oct 4 14:40:09 2019 +0100
drm/i915: Move context management under GEM
The commit message is somewhat entertaining because it fails to
mention this fact completely, and compensates that by an in-commit
changelog entry that claims that ctx->vm is protected by ctx->mutex.
Which was the case _before_ this commit, but no longer after it.
- intel_context holds a full reference. Unfortunately intel_context is also rcu
protected and the reference to the ->vm is dropped before the
rcu barrier - only the kfree is delayed. So again we need to check
whether that leaks anywhere on the intel_context->vm. RCU is only
used to protect intel_context sitting on the breadcrumb lists, which
don't look at the vm anywhere, so we are fine.
Nothing else relies on rcu protection of intel_context and hence is
fully protected by the kref refcount alone, which protects
intel_context->vm in turn.
The breadcrumbs rcu usage was added in
commit c744d50363b714783bbc88d986cc16def13710f7
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Nov 26 14:04:06 2020 +0000
drm/i915/gt: Split the breadcrumb spinlock between global and contexts
its parent commit added the intel_context rcu protection:
commit 14d1eaf08845c534963c83f754afe0cb14cb2512
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Nov 26 14:04:05 2020 +0000
drm/i915/gt: Protect context lifetime with RCU
given some credence to my claim that I've actually caught them all.
- drm_i915_gem_object's shares_resv_from pointer has a full refcount to the
dma_resv, which is a sub-refcount that's released after the final
i915_vm_put() has been called. Safe.
Aside: Maybe we should have a struct dma_resv_shared which is just dma_resv +
kref as a stand-alone thing. It's a pretty useful pattern which other drivers
might want to copy.
For a bit more context see
commit 4d8151ae5329cf50781a02fd2298a909589a5bab
Author: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Date: Tue Jun 1 09:46:41 2021 +0200
drm/i915: Don't free shared locks while shared
- the fpriv->vm_xa was relying on rcu_read_lock for lookup, but that
was updated in a prep patch too to just be a spinlock-protected
lookup.
- intel_gt->vm is set at driver load in intel_gt_init() and released
in intel_gt_driver_release(). There seems to be some issue that
in some error paths this is called twice, but otherwise no rcu to be
found anywhere. This was added in the below commit, which
unfortunately doesn't explain why this complication exists.
commit e6ba76480299a0d77c51d846f7467b1673aad25b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Dec 21 16:03:24 2019 +0000
drm/i915: Remove i915->kernel_context
The proper fix most likely for this is to start using drmm_ at large
scale, but that's also huge amounts of work.
- i915_vma->vm is some real pain, because rcu is rcu protected, at
least in the vma lookup in the context lookup cache in
eb_lookup_vma(). This was added in
commit 4ff4b44cbb70c269259958cbcc48d7b8a2cb9ec8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jun 16 15:05:16 2017 +0100
drm/i915: Store a direct lookup from object handle to vma
This was changed to a radix tree from the hashtable in, but with the
locking unchanged, in
commit d1b48c1e7184d9bc4ae6d7f9fe2eed9efed11ffc
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Aug 16 09:52:08 2017 +0100
drm/i915: Replace execbuf vma ht with an idr
In
commit 93159e12353c2a47e5576d642845a91fa00530bf
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Mar 23 09:28:41 2020 +0000
drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
the locking was changed from dev->struct_mutex to rcu, which added
the requirement to rcu protect i915_vma. Somehow this was missed in
review (or I'm completely blind).
Irrespective of all that the vma lookup cache rcu_read_lock grabs a
full reference of the vma and the rcu doesn't leak further. So no
impact on i915_address_space from that.
I have not found any other rcu use for i915_vma, but given that it
seems broken I also didn't bother to do a careful in-depth audit.
Alltogether there's nothing left in-tree anymore which requires that a
pointer deref to an i915_address_space is safe undre rcu_read_lock
only.
rcu protection of i915_address_space was introduced in
commit b32fa811156328aea5a3c2ff05cc096490382456
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Jun 20 19:37:05 2019 +0100
drm/i915/gtt: Defer address space cleanup to an RCU worker
by mixing up a bugfixing (i915_address_space needs to be released from
a worker) with enabling rcu support. The commit message also seems
somewhat confused, because it talks about cleanup of WC pages
requiring sleep, while the code and linked bugzilla are about a
requirement to take dev->struct_mutex (which yes sleeps but it's a
much more specific problem). Since final kref_put can be called from
pretty much anywhere (including hardirq context through the
scheduler's i915_active cleanup) we need a worker here. Hence that
part must be kept.
Ideally all these reclaim workers should have some kind of integration
with our shrinkers, but for some of these it's rather tricky. Anyway,
that's a preexisting condition in the codeebase that we wont fix in
this patch here.
We also remove the rcu_barrier in ggtt_cleanup_hw added in
commit 60a4233a4952729089e4df152e730f8f4d0e82ce
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Jul 29 14:24:12 2019 +0100
drm/i915: Flush the i915_vm_release before ggtt shutdown
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20210902142057.929669-11-daniel.vetter@ffwll.ch
2021-09-02 22:20:57 +08:00
|
|
|
struct work_struct release_work;
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
struct drm_mm mm;
|
|
|
|
struct intel_gt *gt;
|
|
|
|
struct drm_i915_private *i915;
|
|
|
|
struct device *dma;
|
|
|
|
u64 total; /* size addr space maps (ex. 2GB for ggtt) */
|
|
|
|
u64 reserved; /* size addr space reserved */
|
|
|
|
|
|
|
|
unsigned int bind_async_flags;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Each active user context has its own address space (in full-ppgtt).
|
|
|
|
* Since the vm may be shared between multiple contexts, we count how
|
|
|
|
* many contexts keep us "open". Once open hits zero, we are closed
|
|
|
|
* and do not allow any new attachments, and proceed to shutdown our
|
|
|
|
* vma and page directories.
|
|
|
|
*/
|
|
|
|
atomic_t open;
|
|
|
|
|
|
|
|
struct mutex mutex; /* protects vma and our lists */
|
2021-06-01 15:46:41 +08:00
|
|
|
|
|
|
|
struct kref resv_ref; /* kref to keep the reservation lock alive. */
|
|
|
|
struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */
|
2020-01-07 21:40:09 +08:00
|
|
|
#define VM_CLASS_GGTT 0
|
|
|
|
#define VM_CLASS_PPGTT 1
|
2021-05-07 00:19:24 +08:00
|
|
|
#define VM_CLASS_DPT 2
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2020-07-30 00:42:18 +08:00
|
|
|
struct drm_i915_gem_object *scratch[4];
|
2020-01-07 21:40:09 +08:00
|
|
|
/**
|
|
|
|
* List of vma currently bound.
|
|
|
|
*/
|
|
|
|
struct list_head bound_list;
|
|
|
|
|
|
|
|
/* Global GTT */
|
|
|
|
bool is_ggtt:1;
|
|
|
|
|
2021-05-07 00:19:24 +08:00
|
|
|
/* Display page table */
|
|
|
|
bool is_dpt:1;
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
/* Some systems support read-only mappings for GGTT and/or PPGTT */
|
|
|
|
bool has_read_only:1;
|
|
|
|
|
2020-07-30 00:42:17 +08:00
|
|
|
u8 top;
|
|
|
|
u8 pd_shift;
|
|
|
|
u8 scratch_order;
|
|
|
|
|
2021-09-22 14:25:25 +08:00
|
|
|
/* Flags used when creating page-table objects for this vm */
|
|
|
|
unsigned long lmem_pt_obj_flags;
|
|
|
|
|
2020-07-30 00:42:18 +08:00
|
|
|
struct drm_i915_gem_object *
|
|
|
|
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
|
2021-12-08 22:16:12 +08:00
|
|
|
struct drm_i915_gem_object *
|
|
|
|
(*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
|
2020-07-30 00:42:18 +08:00
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
u64 (*pte_encode)(dma_addr_t addr,
|
|
|
|
enum i915_cache_level level,
|
|
|
|
u32 flags); /* Create a valid PTE */
|
|
|
|
#define PTE_READ_ONLY BIT(0)
|
2021-02-04 01:12:30 +08:00
|
|
|
#define PTE_LM BIT(1)
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2020-07-30 00:42:17 +08:00
|
|
|
void (*allocate_va_range)(struct i915_address_space *vm,
|
|
|
|
struct i915_vm_pt_stash *stash,
|
|
|
|
u64 start, u64 length);
|
2020-01-07 21:40:09 +08:00
|
|
|
void (*clear_range)(struct i915_address_space *vm,
|
|
|
|
u64 start, u64 length);
|
|
|
|
void (*insert_page)(struct i915_address_space *vm,
|
|
|
|
dma_addr_t addr,
|
|
|
|
u64 offset,
|
|
|
|
enum i915_cache_level cache_level,
|
|
|
|
u32 flags);
|
|
|
|
void (*insert_entries)(struct i915_address_space *vm,
|
|
|
|
struct i915_vma *vma,
|
|
|
|
enum i915_cache_level cache_level,
|
|
|
|
u32 flags);
|
|
|
|
void (*cleanup)(struct i915_address_space *vm);
|
|
|
|
|
2021-06-17 14:30:11 +08:00
|
|
|
void (*foreach)(struct i915_address_space *vm,
|
|
|
|
u64 start, u64 length,
|
|
|
|
void (*fn)(struct i915_address_space *vm,
|
|
|
|
struct i915_page_table *pt,
|
|
|
|
void *data),
|
|
|
|
void *data);
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
struct i915_vma_ops vma_ops;
|
|
|
|
|
|
|
|
I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
|
|
|
|
I915_SELFTEST_DECLARE(bool scrub_64K);
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The Graphics Translation Table is the way in which GEN hardware translates a
|
|
|
|
* Graphics Virtual Address into a Physical Address. In addition to the normal
|
|
|
|
* collateral associated with any va->pa translations GEN hardware also has a
|
|
|
|
* portion of the GTT which can be mapped by the CPU and remain both coherent
|
|
|
|
* and correct (in cases like swizzling). That region is referred to as GMADR in
|
|
|
|
* the spec.
|
|
|
|
*/
|
|
|
|
struct i915_ggtt {
|
|
|
|
struct i915_address_space vm;
|
|
|
|
|
|
|
|
struct io_mapping iomap; /* Mapping to our CPU mappable region */
|
|
|
|
struct resource gmadr; /* GMADR resource */
|
|
|
|
resource_size_t mappable_end; /* End offset that we can CPU map */
|
|
|
|
|
|
|
|
/** "Graphics Stolen Memory" holds the global PTEs */
|
|
|
|
void __iomem *gsm;
|
|
|
|
void (*invalidate)(struct i915_ggtt *ggtt);
|
|
|
|
|
|
|
|
/** PPGTT used for aliasing the PPGTT with the GTT */
|
|
|
|
struct i915_ppgtt *alias;
|
|
|
|
|
|
|
|
bool do_idle_maps;
|
|
|
|
|
|
|
|
int mtrr;
|
|
|
|
|
|
|
|
/** Bit 6 swizzling required for X tiling */
|
|
|
|
u32 bit_6_swizzle_x;
|
|
|
|
/** Bit 6 swizzling required for Y tiling */
|
|
|
|
u32 bit_6_swizzle_y;
|
|
|
|
|
|
|
|
u32 pin_bias;
|
|
|
|
|
|
|
|
unsigned int num_fences;
|
2020-03-16 19:38:46 +08:00
|
|
|
struct i915_fence_reg *fence_regs;
|
2020-01-07 21:40:09 +08:00
|
|
|
struct list_head fence_list;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* List of all objects in gtt_space, currently mmaped by userspace.
|
|
|
|
* All objects within this list must also be on bound_list.
|
|
|
|
*/
|
|
|
|
struct list_head userfault_list;
|
|
|
|
|
|
|
|
/* Manual runtime pm autosuspend delay for user GGTT mmaps */
|
|
|
|
struct intel_wakeref_auto userfault_wakeref;
|
|
|
|
|
2020-01-10 20:30:56 +08:00
|
|
|
struct mutex error_mutex;
|
2020-01-07 21:40:09 +08:00
|
|
|
struct drm_mm_node error_capture;
|
|
|
|
struct drm_mm_node uc_fw;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct i915_ppgtt {
|
|
|
|
struct i915_address_space vm;
|
|
|
|
|
|
|
|
struct i915_page_directory *pd;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
|
2021-05-07 00:19:24 +08:00
|
|
|
#define i915_is_dpt(vm) ((vm)->is_dpt)
|
2021-05-25 01:27:02 +08:00
|
|
|
#define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm))
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2021-03-23 23:50:29 +08:00
|
|
|
int __must_check
|
|
|
|
i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
static inline bool
|
|
|
|
i915_vm_is_4lvl(const struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
return (vm->total - 1) >> 32;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
i915_vm_has_scratch_64K(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
i915_vm_has_cache_coloring(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
return i915_is_ggtt(vm) && vm->mm.color_adjust;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct i915_ggtt *
|
|
|
|
i915_vm_to_ggtt(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
|
|
|
|
GEM_BUG_ON(!i915_is_ggtt(vm));
|
|
|
|
return container_of(vm, struct i915_ggtt, vm);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct i915_ppgtt *
|
|
|
|
i915_vm_to_ppgtt(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
|
2021-05-25 01:27:02 +08:00
|
|
|
GEM_BUG_ON(i915_is_ggtt_or_dpt(vm));
|
2020-01-07 21:40:09 +08:00
|
|
|
return container_of(vm, struct i915_ppgtt, vm);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct i915_address_space *
|
|
|
|
i915_vm_get(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
kref_get(&vm->ref);
|
|
|
|
return vm;
|
|
|
|
}
|
|
|
|
|
2021-06-01 15:46:41 +08:00
|
|
|
/**
|
|
|
|
* i915_vm_resv_get - Obtain a reference on the vm's reservation lock
|
|
|
|
* @vm: The vm whose reservation lock we want to share.
|
|
|
|
*
|
|
|
|
* Return: A pointer to the vm's reservation lock.
|
|
|
|
*/
|
|
|
|
static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
kref_get(&vm->resv_ref);
|
|
|
|
return &vm->_resv;
|
|
|
|
}
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
void i915_vm_release(struct kref *kref);
|
|
|
|
|
2021-06-01 15:46:41 +08:00
|
|
|
void i915_vm_resv_release(struct kref *kref);
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
static inline void i915_vm_put(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
kref_put(&vm->ref, i915_vm_release);
|
|
|
|
}
|
|
|
|
|
2021-06-01 15:46:41 +08:00
|
|
|
/**
|
|
|
|
* i915_vm_resv_put - Release a reference on the vm's reservation lock
|
|
|
|
* @resv: Pointer to a reservation lock obtained from i915_vm_resv_get()
|
|
|
|
*/
|
|
|
|
static inline void i915_vm_resv_put(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
kref_put(&vm->resv_ref, i915_vm_resv_release);
|
|
|
|
}
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
static inline struct i915_address_space *
|
|
|
|
i915_vm_open(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
GEM_BUG_ON(!atomic_read(&vm->open));
|
|
|
|
atomic_inc(&vm->open);
|
|
|
|
return i915_vm_get(vm);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
i915_vm_tryopen(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
if (atomic_add_unless(&vm->open, 1, 0))
|
|
|
|
return i915_vm_get(vm);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void __i915_vm_close(struct i915_address_space *vm);
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
i915_vm_close(struct i915_address_space *vm)
|
|
|
|
{
|
|
|
|
GEM_BUG_ON(!atomic_read(&vm->open));
|
2020-02-27 16:57:13 +08:00
|
|
|
__i915_vm_close(vm);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
i915_vm_put(vm);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_address_space_init(struct i915_address_space *vm, int subclass);
|
|
|
|
void i915_address_space_fini(struct i915_address_space *vm);
|
|
|
|
|
|
|
|
static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
|
|
|
|
{
|
|
|
|
const u32 mask = NUM_PTE(pde_shift) - 1;
|
|
|
|
|
|
|
|
return (address >> PAGE_SHIFT) & mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Helper to counts the number of PTEs within the given length. This count
|
|
|
|
* does not cross a page table boundary, so the max value would be
|
|
|
|
* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
|
|
|
|
*/
|
|
|
|
static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
|
|
|
|
{
|
|
|
|
const u64 mask = ~((1ULL << pde_shift) - 1);
|
|
|
|
u64 end;
|
|
|
|
|
|
|
|
GEM_BUG_ON(length == 0);
|
|
|
|
GEM_BUG_ON(offset_in_page(addr | length));
|
|
|
|
|
|
|
|
end = addr + length;
|
|
|
|
|
|
|
|
if ((addr & mask) != (end & mask))
|
|
|
|
return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
|
|
|
|
|
|
|
|
return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 i915_pde_index(u64 addr, u32 shift)
|
|
|
|
{
|
|
|
|
return (addr >> shift) & I915_PDE_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct i915_page_table *
|
|
|
|
i915_pt_entry(const struct i915_page_directory * const pd,
|
|
|
|
const unsigned short n)
|
|
|
|
{
|
|
|
|
return pd->entry[n];
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct i915_page_directory *
|
|
|
|
i915_pd_entry(const struct i915_page_directory * const pdp,
|
|
|
|
const unsigned short n)
|
|
|
|
{
|
|
|
|
return pdp->entry[n];
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline dma_addr_t
|
|
|
|
i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
|
|
|
|
{
|
2020-07-30 00:42:18 +08:00
|
|
|
struct i915_page_table *pt = ppgtt->pd->entry[n];
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2020-07-30 00:42:18 +08:00
|
|
|
return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
|
2020-01-07 21:40:09 +08:00
|
|
|
}
|
|
|
|
|
2021-09-22 14:25:25 +08:00
|
|
|
void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
|
|
|
|
unsigned long lmem_pt_obj_flags);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
int i915_ggtt_probe_hw(struct drm_i915_private *i915);
|
|
|
|
int i915_ggtt_init_hw(struct drm_i915_private *i915);
|
|
|
|
int i915_ggtt_enable_hw(struct drm_i915_private *i915);
|
|
|
|
void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
|
|
|
|
void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
|
|
|
|
int i915_init_ggtt(struct drm_i915_private *i915);
|
|
|
|
void i915_ggtt_driver_release(struct drm_i915_private *i915);
|
2021-06-01 15:46:41 +08:00
|
|
|
void i915_ggtt_driver_late_release(struct drm_i915_private *i915);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
|
|
|
|
{
|
|
|
|
return ggtt->mappable_end > 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int i915_ppgtt_init_hw(struct intel_gt *gt);
|
|
|
|
|
2021-09-22 14:25:25 +08:00
|
|
|
struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
|
|
|
|
unsigned long lmem_pt_obj_flags);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2021-11-02 02:35:50 +08:00
|
|
|
void i915_ggtt_suspend_vm(struct i915_address_space *vm);
|
|
|
|
bool i915_ggtt_resume_vm(struct i915_address_space *vm);
|
2020-01-31 02:17:09 +08:00
|
|
|
void i915_ggtt_suspend(struct i915_ggtt *gtt);
|
|
|
|
void i915_ggtt_resume(struct i915_ggtt *ggtt);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
void
|
2020-07-30 00:42:18 +08:00
|
|
|
fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
|
|
|
|
#define fill32_px(px, v) do { \
|
|
|
|
u64 v__ = lower_32_bits(v); \
|
|
|
|
fill_px((px), v__ << 32 | v__); \
|
|
|
|
} while (0)
|
|
|
|
|
2020-07-30 00:42:18 +08:00
|
|
|
int setup_scratch_page(struct i915_address_space *vm);
|
2020-01-07 21:40:09 +08:00
|
|
|
void free_scratch(struct i915_address_space *vm);
|
|
|
|
|
2020-07-30 00:42:18 +08:00
|
|
|
struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
|
2021-04-27 16:54:14 +08:00
|
|
|
struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz);
|
2020-01-07 21:40:09 +08:00
|
|
|
struct i915_page_table *alloc_pt(struct i915_address_space *vm);
|
|
|
|
struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
|
drm/i915/gt: Shrink i915_page_directory's slab bucket
kmalloc uses power-of-two slab buckets for small allocations (up to a
few pages). Since i915_page_directory is a page of pointers, plus a
couple more, this is rounded up to 8K, and we waste nearly 50% of that
allocation. Long terms this leads to poor memory utilisation, bloating
the kernel footprint, but the problem is exacerbated by our conservative
preallocation scheme for binding VMA. As we are required to allocate all
levels for each vma just in case we need to insert them upon binding,
this leads to a large multiplication factor for a single page vma. By
halving the allocation we need for the page directory structure, we
halve the impact of that factor, bringing workloads that once fitted into
memory, hopefully back to fitting into memory.
We maintain the split between i915_page_directory and i915_page_table as
we only need half the allocation for the lowest, most populous, level.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200729164219.5737-3-chris@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2020-07-30 00:42:19 +08:00
|
|
|
struct i915_page_directory *__alloc_pd(int npde);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
2021-04-27 16:54:13 +08:00
|
|
|
int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
|
|
|
|
int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
drm/i915/gt: Shrink i915_page_directory's slab bucket
kmalloc uses power-of-two slab buckets for small allocations (up to a
few pages). Since i915_page_directory is a page of pointers, plus a
couple more, this is rounded up to 8K, and we waste nearly 50% of that
allocation. Long terms this leads to poor memory utilisation, bloating
the kernel footprint, but the problem is exacerbated by our conservative
preallocation scheme for binding VMA. As we are required to allocate all
levels for each vma just in case we need to insert them upon binding,
this leads to a large multiplication factor for a single page vma. By
halving the allocation we need for the page directory structure, we
halve the impact of that factor, bringing workloads that once fitted into
memory, hopefully back to fitting into memory.
We maintain the split between i915_page_directory and i915_page_table as
we only need half the allocation for the lowest, most populous, level.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200729164219.5737-3-chris@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2020-07-30 00:42:19 +08:00
|
|
|
void free_px(struct i915_address_space *vm,
|
|
|
|
struct i915_page_table *pt, int lvl);
|
|
|
|
#define free_pt(vm, px) free_px(vm, px, 0)
|
|
|
|
#define free_pd(vm, px) free_px(vm, px_pt(px), 1)
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
void
|
|
|
|
__set_pd_entry(struct i915_page_directory * const pd,
|
|
|
|
const unsigned short idx,
|
2020-07-30 00:42:18 +08:00
|
|
|
struct i915_page_table *pt,
|
2020-01-07 21:40:09 +08:00
|
|
|
u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
|
|
|
|
|
|
|
|
#define set_pd_entry(pd, idx, to) \
|
2020-07-30 00:42:18 +08:00
|
|
|
__set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode)
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
void
|
|
|
|
clear_pd_entry(struct i915_page_directory * const pd,
|
|
|
|
const unsigned short idx,
|
2020-07-30 00:42:18 +08:00
|
|
|
const struct drm_i915_gem_object * const scratch);
|
2020-01-07 21:40:09 +08:00
|
|
|
|
|
|
|
bool
|
|
|
|
release_pd_entry(struct i915_page_directory * const pd,
|
|
|
|
const unsigned short idx,
|
|
|
|
struct i915_page_table * const pt,
|
2020-07-30 00:42:18 +08:00
|
|
|
const struct drm_i915_gem_object * const scratch);
|
2020-01-07 21:40:09 +08:00
|
|
|
void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
|
|
|
|
|
2020-07-30 00:42:17 +08:00
|
|
|
void ppgtt_bind_vma(struct i915_address_space *vm,
|
|
|
|
struct i915_vm_pt_stash *stash,
|
|
|
|
struct i915_vma *vma,
|
|
|
|
enum i915_cache_level cache_level,
|
|
|
|
u32 flags);
|
2020-07-03 18:25:19 +08:00
|
|
|
void ppgtt_unbind_vma(struct i915_address_space *vm,
|
|
|
|
struct i915_vma *vma);
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
void gtt_write_workarounds(struct intel_gt *gt);
|
|
|
|
|
|
|
|
void setup_private_pat(struct intel_uncore *uncore);
|
|
|
|
|
2020-07-30 00:42:17 +08:00
|
|
|
int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
|
|
|
|
struct i915_vm_pt_stash *stash,
|
|
|
|
u64 size);
|
2021-04-27 16:54:13 +08:00
|
|
|
int i915_vm_map_pt_stash(struct i915_address_space *vm,
|
2020-07-30 00:42:18 +08:00
|
|
|
struct i915_vm_pt_stash *stash);
|
2020-07-30 00:42:17 +08:00
|
|
|
void i915_vm_free_pt_stash(struct i915_address_space *vm,
|
|
|
|
struct i915_vm_pt_stash *stash);
|
|
|
|
|
2020-12-19 10:03:43 +08:00
|
|
|
struct i915_vma *
|
|
|
|
__vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size);
|
|
|
|
|
2021-03-23 23:50:13 +08:00
|
|
|
struct i915_vma *
|
|
|
|
__vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size);
|
|
|
|
|
2020-01-07 21:40:09 +08:00
|
|
|
static inline struct sgt_dma {
|
|
|
|
struct scatterlist *sg;
|
|
|
|
dma_addr_t dma, max;
|
|
|
|
} sgt_dma(struct i915_vma *vma) {
|
|
|
|
struct scatterlist *sg = vma->pages->sgl;
|
|
|
|
dma_addr_t addr = sg_dma_address(sg);
|
|
|
|
|
2020-10-06 17:25:07 +08:00
|
|
|
return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
|
2020-01-07 21:40:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|