OpenCloudOS-Kernel/include/dt-bindings/clock/gxbb-clkc.h

/*
 * GXBB clock tree IDs
 */

#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H

#define CLKID_CPUCLK		1
#define CLKID_HDMI_PLL		2
#define CLKID_FCLK_DIV2		4
#define CLKID_FCLK_DIV3		5
#define CLKID_FCLK_DIV4		6
#define CLKID_CLK81		12
#define CLKID_MPLL2		15
#define CLKID_SPI		34
#define CLKID_ETH		36
#define CLKID_USB0		50
#define CLKID_USB1		51
#define CLKID_USB		55
#define CLKID_USB1_DDR_BRIDGE	64
#define CLKID_USB0_DDR_BRIDGE	65
#define CLKID_SD_EMMC_A		94
#define CLKID_SD_EMMC_B		95
#define CLKID_SD_EMMC_C		96

#endif /* __GXBB_CLKC_H */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-24 06:44:26 +08:00			`/*`
			`* GXBB clock tree IDs`
			`*/`

			`#ifndef __GXBB_CLKC_H`
			`#define __GXBB_CLKC_H`

			`#define CLKID_CPUCLK 1`
clk: meson-gxbb: Export PWM related clocks for DT Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com 2016-08-22 20:49:37 +08:00			`#define CLKID_HDMI_PLL 2`
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-08-03 05:40:11 +08:00			`#define CLKID_FCLK_DIV2 4`
clk: meson-gxbb: Export PWM related clocks for DT Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com 2016-08-22 20:49:37 +08:00			`#define CLKID_FCLK_DIV3 5`
			`#define CLKID_FCLK_DIV4 6`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-24 06:44:26 +08:00			`#define CLKID_CLK81 12`
clk: gxbb: expose MPLL2 clock for use by DT This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-07 05:38:44 +08:00			`#define CLKID_MPLL2 15`
clk: gxbb: expose spifc clock SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-07 23:13:39 +08:00			`#define CLKID_SPI 34`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-24 06:44:26 +08:00			`#define CLKID_ETH 36`
clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-05 05:31:46 +08:00			`#define CLKID_USB0 50`
			`#define CLKID_USB1 51`
			`#define CLKID_USB 55`
			`#define CLKID_USB1_DDR_BRIDGE 64`
			`#define CLKID_USB0_DDR_BRIDGE 65`
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-08-03 05:40:11 +08:00			`#define CLKID_SD_EMMC_A 94`
			`#define CLKID_SD_EMMC_B 95`
			`#define CLKID_SD_EMMC_C 96`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-24 06:44:26 +08:00
			`#endif /* __GXBB_CLKC_H */`