2013-07-20 03:36:52 +08:00
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "i915_drv.h"
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#include "intel_drv.h"
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#define FORCEWAKE_ACK_TIMEOUT_MS 2
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2013-07-20 03:36:53 +08:00
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#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
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#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
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#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
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#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
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#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
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#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
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#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
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#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
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#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
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2013-07-20 03:36:52 +08:00
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static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
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{
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u32 gt_thread_status_mask;
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if (IS_HASWELL(dev_priv->dev))
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gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
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else
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gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
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/* w/a for a sporadic read returning 0 by waiting for the GT
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* thread to wake up.
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*/
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
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2013-07-20 03:36:52 +08:00
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DRM_ERROR("GT thread status wait timed out\n");
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}
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static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE, 0);
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/* something from same cacheline, but !FORCEWAKE */
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__raw_posting_read(dev_priv, ECOBUS);
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2013-07-20 03:36:52 +08:00
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}
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static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE, 1);
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/* something from same cacheline, but !FORCEWAKE */
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__raw_posting_read(dev_priv, ECOBUS);
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2013-07-20 03:36:52 +08:00
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
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/* WaRsForcewakeWaitTC0:snb */
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
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2013-07-20 03:36:52 +08:00
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/* something from same cacheline, but !FORCEWAKE_MT */
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2013-07-20 03:36:53 +08:00
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__raw_posting_read(dev_priv, ECOBUS);
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2013-07-20 03:36:52 +08:00
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}
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static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
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{
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u32 forcewake_ack;
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if (IS_HASWELL(dev_priv->dev))
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forcewake_ack = FORCEWAKE_ACK_HSW;
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else
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forcewake_ack = FORCEWAKE_MT_ACK;
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE_MT,
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_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
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2013-07-20 03:36:52 +08:00
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/* something from same cacheline, but !FORCEWAKE_MT */
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2013-07-20 03:36:53 +08:00
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__raw_posting_read(dev_priv, ECOBUS);
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2013-07-20 03:36:52 +08:00
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
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/* WaRsForcewakeWaitTC0:ivb,hsw */
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
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{
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u32 gtfifodbg;
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2013-07-20 03:36:53 +08:00
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gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
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2013-07-20 03:36:52 +08:00
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if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
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"MMIO read or write has been dropped %x\n", gtfifodbg))
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
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2013-07-20 03:36:52 +08:00
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}
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static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE, 0);
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2013-07-20 03:36:52 +08:00
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/* something from same cacheline, but !FORCEWAKE */
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2013-07-20 03:36:53 +08:00
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__raw_posting_read(dev_priv, ECOBUS);
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2013-07-20 03:36:52 +08:00
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gen6_gt_check_fifodbg(dev_priv);
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}
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static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE_MT,
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_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
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2013-07-20 03:36:52 +08:00
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/* something from same cacheline, but !FORCEWAKE_MT */
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2013-07-20 03:36:53 +08:00
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__raw_posting_read(dev_priv, ECOBUS);
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2013-07-20 03:36:52 +08:00
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gen6_gt_check_fifodbg(dev_priv);
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}
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static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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int ret = 0;
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if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
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int loop = 500;
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2013-07-20 03:36:53 +08:00
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u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
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2013-07-20 03:36:52 +08:00
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while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
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udelay(10);
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2013-07-20 03:36:53 +08:00
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fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
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2013-07-20 03:36:52 +08:00
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}
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if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
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++ret;
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dev_priv->uncore.fifo_count = fifo;
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}
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dev_priv->uncore.fifo_count--;
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return ret;
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}
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static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
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_MASKED_BIT_DISABLE(0xffff));
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2013-07-20 03:36:52 +08:00
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/* something from same cacheline, but !FORCEWAKE_VLV */
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2013-07-20 03:36:53 +08:00
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__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
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2013-07-20 03:36:52 +08:00
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}
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static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
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_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
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__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
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2013-07-20 03:36:52 +08:00
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_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
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2013-07-20 03:36:53 +08:00
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if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) &
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2013-07-20 03:36:52 +08:00
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FORCEWAKE_KERNEL),
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FORCEWAKE_ACK_TIMEOUT_MS))
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DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
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/* WaRsForcewakeWaitTC0:vlv */
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
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{
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
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_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
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__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
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2013-07-20 03:36:52 +08:00
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_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
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/* The below doubles as a POSTING_READ */
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gen6_gt_check_fifodbg(dev_priv);
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}
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2013-08-26 20:46:09 +08:00
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static void gen6_force_wake_work(struct work_struct *work)
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{
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struct drm_i915_private *dev_priv =
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container_of(work, typeof(*dev_priv), uncore.force_wake_work.work);
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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if (--dev_priv->uncore.forcewake_count == 0)
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dev_priv->uncore.funcs.force_wake_put(dev_priv);
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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2013-07-20 03:36:52 +08:00
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void intel_uncore_early_sanitize(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (HAS_FPGA_DBG_UNCLAIMED(dev))
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2013-07-20 03:36:53 +08:00
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__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
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2013-10-05 12:22:50 +08:00
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if (IS_HASWELL(dev) &&
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(__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
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/* The docs do not explain exactly how the calculation can be
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* made. It is somewhat guessable, but for now, it's always
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* 128MB.
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* NB: We can't write IDICR yet because we do not have gt funcs
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* set up */
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dev_priv->ellc_size = 128;
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DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
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}
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2013-07-20 03:36:52 +08:00
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}
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2013-08-23 21:52:30 +08:00
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static void intel_uncore_forcewake_reset(struct drm_device *dev)
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2013-07-20 03:36:52 +08:00
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (IS_VALLEYVIEW(dev)) {
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vlv_force_wake_reset(dev_priv);
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} else if (INTEL_INFO(dev)->gen >= 6) {
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__gen6_gt_force_wake_reset(dev_priv);
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if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
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__gen6_gt_force_wake_mt_reset(dev_priv);
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}
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2013-08-23 21:52:30 +08:00
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}
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void intel_uncore_sanitize(struct drm_device *dev)
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{
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2013-10-03 23:16:17 +08:00
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg_val;
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2013-08-23 21:52:30 +08:00
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intel_uncore_forcewake_reset(dev);
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2013-07-20 03:36:52 +08:00
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/* BIOS often leaves RC6 enabled, but disable it for hw init */
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intel_disable_gt_powersave(dev);
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2013-10-03 23:16:17 +08:00
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/* Turn off power gate, require especially for the BIOS less system */
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if (IS_VALLEYVIEW(dev)) {
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mutex_lock(&dev_priv->rps.hw_lock);
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reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
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if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
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vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
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mutex_unlock(&dev_priv->rps.hw_lock);
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}
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2013-07-20 03:36:52 +08:00
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}
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/*
|
|
|
|
* Generally this is called implicitly by the register read function. However,
|
|
|
|
* if some sequence requires the GT to not power down then this function should
|
|
|
|
* be called at the beginning of the sequence followed by a call to
|
|
|
|
* gen6_gt_force_wake_put() at the end of the sequence.
|
|
|
|
*/
|
|
|
|
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
if (dev_priv->uncore.forcewake_count++ == 0)
|
|
|
|
dev_priv->uncore.funcs.force_wake_get(dev_priv);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* see gen6_gt_force_wake_get()
|
|
|
|
*/
|
|
|
|
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
2013-08-26 20:46:09 +08:00
|
|
|
if (--dev_priv->uncore.forcewake_count == 0) {
|
|
|
|
dev_priv->uncore.forcewake_count++;
|
|
|
|
mod_delayed_work(dev_priv->wq,
|
|
|
|
&dev_priv->uncore.force_wake_work,
|
|
|
|
1);
|
|
|
|
}
|
2013-07-20 03:36:52 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We give fast paths for the really cool registers */
|
|
|
|
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
|
|
|
|
((HAS_FORCE_WAKE((dev_priv)->dev)) && \
|
|
|
|
((reg) < 0x40000) && \
|
|
|
|
((reg) != FORCEWAKE))
|
|
|
|
|
|
|
|
static void
|
|
|
|
ilk_dummy_write(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
|
|
|
|
* the chip from rc6 before touching it for real. MI_MODE is masked,
|
|
|
|
* hence harmless to write 0 into. */
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write32(dev_priv, MI_MODE, 0);
|
2013-07-20 03:36:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
|
|
|
|
{
|
|
|
|
if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
|
2013-07-20 03:36:53 +08:00
|
|
|
(__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
|
2013-07-20 03:36:52 +08:00
|
|
|
DRM_ERROR("Unknown unclaimed register before writing to %x\n",
|
|
|
|
reg);
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
|
2013-07-20 03:36:52 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
|
|
|
|
{
|
|
|
|
if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
|
2013-07-20 03:36:53 +08:00
|
|
|
(__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
|
2013-07-20 03:36:52 +08:00
|
|
|
DRM_ERROR("Unclaimed write to %x\n", reg);
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
|
2013-07-20 03:36:52 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-05 12:24:53 +08:00
|
|
|
#define REG_READ_HEADER(x) \
|
|
|
|
unsigned long irqflags; \
|
|
|
|
u##x val = 0; \
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
|
|
|
|
|
|
|
|
#define REG_READ_FOOTER \
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
|
|
|
|
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
|
|
|
|
return val
|
|
|
|
|
2013-07-20 03:36:53 +08:00
|
|
|
#define __i915_read(x) \
|
2013-10-05 12:22:51 +08:00
|
|
|
static u##x \
|
|
|
|
i915_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
|
2013-10-05 12:24:53 +08:00
|
|
|
REG_READ_HEADER(x); \
|
2013-07-20 03:36:55 +08:00
|
|
|
if (dev_priv->info->gen == 5) \
|
2013-07-20 03:36:52 +08:00
|
|
|
ilk_dummy_write(dev_priv); \
|
|
|
|
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
|
|
|
if (dev_priv->uncore.forcewake_count == 0) \
|
|
|
|
dev_priv->uncore.funcs.force_wake_get(dev_priv); \
|
2013-07-20 03:36:53 +08:00
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
2013-07-20 03:36:52 +08:00
|
|
|
if (dev_priv->uncore.forcewake_count == 0) \
|
|
|
|
dev_priv->uncore.funcs.force_wake_put(dev_priv); \
|
|
|
|
} else { \
|
2013-07-20 03:36:53 +08:00
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
2013-07-20 03:36:52 +08:00
|
|
|
} \
|
2013-10-05 12:24:53 +08:00
|
|
|
REG_READ_FOOTER; \
|
2013-07-20 03:36:52 +08:00
|
|
|
}
|
|
|
|
|
2013-07-20 03:36:53 +08:00
|
|
|
__i915_read(8)
|
|
|
|
__i915_read(16)
|
|
|
|
__i915_read(32)
|
|
|
|
__i915_read(64)
|
2013-07-20 03:36:52 +08:00
|
|
|
#undef __i915_read
|
2013-10-05 12:24:53 +08:00
|
|
|
#undef REG_READ_FOOTER
|
|
|
|
#undef REG_READ_HEADER
|
|
|
|
|
|
|
|
#define REG_WRITE_HEADER \
|
|
|
|
unsigned long irqflags; \
|
|
|
|
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
|
2013-07-20 03:36:52 +08:00
|
|
|
|
2013-07-20 03:36:53 +08:00
|
|
|
#define __i915_write(x) \
|
2013-10-05 12:22:51 +08:00
|
|
|
static void \
|
|
|
|
i915_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
|
2013-07-20 03:36:52 +08:00
|
|
|
u32 __fifo_ret = 0; \
|
2013-10-05 12:24:53 +08:00
|
|
|
REG_WRITE_HEADER; \
|
2013-07-20 03:36:52 +08:00
|
|
|
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
|
|
|
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
|
|
|
|
} \
|
2013-07-20 03:36:55 +08:00
|
|
|
if (dev_priv->info->gen == 5) \
|
2013-07-20 03:36:52 +08:00
|
|
|
ilk_dummy_write(dev_priv); \
|
|
|
|
hsw_unclaimed_reg_clear(dev_priv, reg); \
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
2013-07-20 03:36:52 +08:00
|
|
|
if (unlikely(__fifo_ret)) { \
|
|
|
|
gen6_gt_check_fifodbg(dev_priv); \
|
|
|
|
} \
|
|
|
|
hsw_unclaimed_reg_check(dev_priv, reg); \
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
|
|
|
|
}
|
2013-07-20 03:36:53 +08:00
|
|
|
__i915_write(8)
|
|
|
|
__i915_write(16)
|
|
|
|
__i915_write(32)
|
|
|
|
__i915_write(64)
|
2013-07-20 03:36:52 +08:00
|
|
|
#undef __i915_write
|
2013-10-05 12:24:53 +08:00
|
|
|
#undef REG_WRITE_HEADER
|
2013-07-20 03:36:52 +08:00
|
|
|
|
2013-10-05 12:22:51 +08:00
|
|
|
void intel_uncore_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work,
|
|
|
|
gen6_force_wake_work);
|
|
|
|
|
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put;
|
|
|
|
} else if (IS_HASWELL(dev)) {
|
|
|
|
dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
|
|
|
|
} else if (IS_IVYBRIDGE(dev)) {
|
|
|
|
u32 ecobus;
|
|
|
|
|
|
|
|
/* IVB configs may use multi-threaded forcewake */
|
|
|
|
|
|
|
|
/* A small trick here - if the bios hasn't configured
|
|
|
|
* MT forcewake, and if the device is in RC6, then
|
|
|
|
* force_wake_mt_get will not wake the device and the
|
|
|
|
* ECOBUS read will return zero. Which will be
|
|
|
|
* (correctly) interpreted by the test below as MT
|
|
|
|
* forcewake being disabled.
|
|
|
|
*/
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
__gen6_gt_force_wake_mt_get(dev_priv);
|
|
|
|
ecobus = __raw_i915_read32(dev_priv, ECOBUS);
|
|
|
|
__gen6_gt_force_wake_mt_put(dev_priv);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
if (ecobus & FORCEWAKE_MT_ENABLE) {
|
|
|
|
dev_priv->uncore.funcs.force_wake_get =
|
|
|
|
__gen6_gt_force_wake_mt_get;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
|
|
|
__gen6_gt_force_wake_mt_put;
|
|
|
|
} else {
|
|
|
|
DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
|
|
|
|
DRM_INFO("when using vblank-synced partial screen updates.\n");
|
|
|
|
dev_priv->uncore.funcs.force_wake_get =
|
|
|
|
__gen6_gt_force_wake_get;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
|
|
|
__gen6_gt_force_wake_put;
|
|
|
|
}
|
|
|
|
} else if (IS_GEN6(dev)) {
|
|
|
|
dev_priv->uncore.funcs.force_wake_get =
|
|
|
|
__gen6_gt_force_wake_get;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
|
|
|
__gen6_gt_force_wake_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->uncore.funcs.mmio_readb = i915_read8;
|
|
|
|
dev_priv->uncore.funcs.mmio_readw = i915_read16;
|
|
|
|
dev_priv->uncore.funcs.mmio_readl = i915_read32;
|
|
|
|
dev_priv->uncore.funcs.mmio_readq = i915_read64;
|
|
|
|
dev_priv->uncore.funcs.mmio_writeb = i915_write8;
|
|
|
|
dev_priv->uncore.funcs.mmio_writew = i915_write16;
|
|
|
|
dev_priv->uncore.funcs.mmio_writel = i915_write32;
|
|
|
|
dev_priv->uncore.funcs.mmio_writeq = i915_write64;
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_uncore_fini(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
flush_delayed_work(&dev_priv->uncore.force_wake_work);
|
|
|
|
|
|
|
|
/* Paranoia: make sure we have disabled everything before we exit. */
|
|
|
|
intel_uncore_sanitize(dev);
|
|
|
|
}
|
|
|
|
|
2013-07-20 03:36:52 +08:00
|
|
|
static const struct register_whitelist {
|
|
|
|
uint64_t offset;
|
|
|
|
uint32_t size;
|
|
|
|
uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
|
|
|
|
} whitelist[] = {
|
|
|
|
{ RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
int i915_reg_read_ioctl(struct drm_device *dev,
|
|
|
|
void *data, struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_reg_read *reg = data;
|
|
|
|
struct register_whitelist const *entry = whitelist;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
|
|
|
|
if (entry->offset == reg->offset &&
|
|
|
|
(1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == ARRAY_SIZE(whitelist))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (entry->size) {
|
|
|
|
case 8:
|
|
|
|
reg->val = I915_READ64(reg->offset);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
reg->val = I915_READ(reg->offset);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
reg->val = I915_READ16(reg->offset);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
reg->val = I915_READ8(reg->offset);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN_ON(1);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i965_reset_complete(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
u8 gdrst;
|
|
|
|
pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
|
|
|
|
return (gdrst & GRDOM_RESET_ENABLE) == 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i965_do_reset(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the domains we want to reset (GRDOM/bits 2 and 3) as
|
|
|
|
* well as the reset bit (GR/bit 0). Setting the GR bit
|
|
|
|
* triggers the reset; when done, the hardware will clear it.
|
|
|
|
*/
|
|
|
|
pci_write_config_byte(dev->pdev, I965_GDRST,
|
|
|
|
GRDOM_RENDER | GRDOM_RESET_ENABLE);
|
|
|
|
ret = wait_for(i965_reset_complete(dev), 500);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* We can't reset render&media without also resetting display ... */
|
|
|
|
pci_write_config_byte(dev->pdev, I965_GDRST,
|
|
|
|
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
|
|
|
|
|
|
|
|
ret = wait_for(i965_reset_complete(dev), 500);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pci_write_config_byte(dev->pdev, I965_GDRST, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ironlake_do_reset(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 gdrst;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
|
|
|
|
gdrst &= ~GRDOM_MASK;
|
|
|
|
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
|
|
|
|
gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
|
|
|
|
ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* We can't reset render&media without also resetting display ... */
|
|
|
|
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
|
|
|
|
gdrst &= ~GRDOM_MASK;
|
|
|
|
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
|
|
|
|
gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
|
|
|
|
return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int gen6_do_reset(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
/* Hold uncore.lock across reset to prevent any register access
|
|
|
|
* with forcewake not set correctly
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
|
|
|
|
/* Reset the chip */
|
|
|
|
|
|
|
|
/* GEN6_GDRST is not in the gt power well, no need to check
|
|
|
|
* for fifo space for the write or forcewake the chip for
|
|
|
|
* the read
|
|
|
|
*/
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
|
2013-07-20 03:36:52 +08:00
|
|
|
|
|
|
|
/* Spin waiting for the device to ack the reset request */
|
2013-07-20 03:36:53 +08:00
|
|
|
ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
|
2013-07-20 03:36:52 +08:00
|
|
|
|
2013-08-23 21:52:30 +08:00
|
|
|
intel_uncore_forcewake_reset(dev);
|
|
|
|
|
2013-07-20 03:36:52 +08:00
|
|
|
/* If reset with a user forcewake, try to restore, otherwise turn it off */
|
|
|
|
if (dev_priv->uncore.forcewake_count)
|
|
|
|
dev_priv->uncore.funcs.force_wake_get(dev_priv);
|
|
|
|
else
|
|
|
|
dev_priv->uncore.funcs.force_wake_put(dev_priv);
|
|
|
|
|
|
|
|
/* Restore fifo count */
|
2013-07-20 03:36:53 +08:00
|
|
|
dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
|
2013-07-20 03:36:52 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int intel_gpu_reset(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
switch (INTEL_INFO(dev)->gen) {
|
|
|
|
case 7:
|
|
|
|
case 6: return gen6_do_reset(dev);
|
|
|
|
case 5: return ironlake_do_reset(dev);
|
|
|
|
case 4: return i965_do_reset(dev);
|
|
|
|
default: return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_uncore_clear_errors(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-07-20 03:36:53 +08:00
|
|
|
/* XXX needs spinlock around caller's grouping */
|
2013-07-20 03:36:52 +08:00
|
|
|
if (HAS_FPGA_DBG_UNCLAIMED(dev))
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
|
2013-07-20 03:36:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_uncore_check_errors(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
|
2013-07-20 03:36:53 +08:00
|
|
|
(__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
|
2013-07-20 03:36:52 +08:00
|
|
|
DRM_ERROR("Unclaimed register before interrupt\n");
|
2013-07-20 03:36:53 +08:00
|
|
|
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
|
2013-07-20 03:36:52 +08:00
|
|
|
}
|
|
|
|
}
|